| /linux/drivers/phy/ti/ |
| H A D | phy-dm816x-usb.c | 1 // SPDX-License-Identifier: GPL-2.0-only
15 #include <linux/phy/phy.h>
17 #include <linux/mfd/syscon.h>
22 * phy as being SR70LX Synopsys USB 2.0 OTG nanoPHY. It also seems at
32 * Finally, the phy on dm814x and am335x is different from dm816x.
34 #define DM816X_USB_CTRL_PHYCLKSRC BIT(8) /* 1 = PLL ref clock */
35 #define DM816X_USB_CTRL_PHYSLEEP1 BIT(1) /* Enable the first phy */
36 #define DM816X_USB_CTRL_PHYSLEEP0 BIT(0) /* Enable the second phy */
43 struct regmap *syscon; member
46 struct clk *refclk; member
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| H A D | phy-ti-pipe3.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * phy-ti-pipe3 - PIPE3 PHY driver.
5 * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com
13 #include <linux/phy/phy.h>
20 #include <linux/phy/omap_control_phy.h>
22 #include <linux/mfd/syscon.h>
172 struct clk *refclk; member
178 unsigned int dpll_reset_reg; /* reg. index within syscon */
179 unsigned int power_reg; /* power reg. index within syscon */
180 unsigned int pcie_pcs_reg; /* pcs reg. index in syscon */
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| H A D | phy-am654-serdes.c | 1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (C) 2018 - 2019 Texas Instruments Incorporated - http://www.ti.com/
9 #include <dt-bindings/phy/phy.h>
12 #include <linux/clk-provider.h>
15 #include <linux/mfd/syscon.h>
18 #include <linux/phy/phy.h>
106 /* CMU PLL Control */
141 /* Mid-speed initial calibration control */
144 /* High-speed initial calibration control */
147 /* Mid-speed recalibration control */
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| /linux/Documentation/devicetree/bindings/usb/ |
| H A D | ti,am62-usb.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/usb/ti,am62-usb.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: TI's AM62 wrapper module for the Synopsys USBSS-DRD controller
10 - Aswath Govindraju <a-govindraju@ti.com>
14 const: ti,am62-usb
19 - description: USB CFG register space
20 - description: USB PHY2 register space
24 power-domains:
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| /linux/Documentation/devicetree/bindings/phy/ |
| H A D | ti,phy-j721e-wiz.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2 # Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com/
4 ---
5 $id: http://devicetree.org/schemas/phy/ti,phy-j721e-wiz.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - Kishon Vijay Abraham I <kishon@ti.com>
16 - ti,j721e-wiz-16g
17 - ti,j721e-wiz-10g
18 - ti,j721s2-wiz-10g
19 - ti,am64-wiz-10g
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| /linux/arch/mips/boot/dts/brcm/ |
| H A D | bcm63268.dtsi | 1 // SPDX-License-Identifier: GPL-2.0
3 #include "dt-bindings/clock/bcm63268-clock.h"
4 #include "dt-bindings/reset/bcm63268-reset.h"
5 #include "dt-bindings/soc/bcm63268-pm.h"
8 #address-cells = <1>;
9 #size-cells = <1>;
13 #address-cells = <1>;
14 #size-cells = <0>;
16 mips-hpt-frequency = <200000000>;
32 periph_osc: periph-osc {
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| H A D | bcm6362.dtsi | 1 // SPDX-License-Identifier: GPL-2.0
3 #include "dt-bindings/clock/bcm6362-clock.h"
4 #include "dt-bindings/reset/bcm6362-reset.h"
5 #include "dt-bindings/soc/bcm6362-pm.h"
8 #address-cells = <1>;
9 #size-cells = <1>;
13 #address-cells = <1>;
14 #size-cells = <0>;
16 mips-hpt-frequency = <200000000>;
32 periph_osc: periph-osc {
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| H A D | bcm6328.dtsi | 1 // SPDX-License-Identifier: GPL-2.0
3 #include "dt-bindings/clock/bcm6328-clock.h"
4 #include "dt-bindings/reset/bcm6328-reset.h"
5 #include "dt-bindings/soc/bcm6328-pm.h"
8 #address-cells = <1>;
9 #size-cells = <1>;
13 #address-cells = <1>;
14 #size-cells = <0>;
16 mips-hpt-frequency = <160000000>;
32 periph_osc: periph-osc {
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| /linux/drivers/phy/freescale/ |
| H A D | phy-fsl-imx8m-pcie.c | 1 // SPDX-License-Identifier: GPL-2.0+
11 #include <linux/mfd/syscon.h>
12 #include <linux/mfd/syscon/imx7-iomuxc-gpr.h>
15 #include <linux/phy/phy.h>
20 #include <dt-bindings/phy/phy-imx8-pcie.h>
62 struct phy *phy; member
73 static int imx8_pcie_phy_power_on(struct phy *phy) in imx8_pcie_phy_power_on() argument
77 struct imx8_pcie_phy *imx8_phy = phy_get_drvdata(phy); in imx8_pcie_phy_power_on()
79 pad_mode = imx8_phy->refclk_pad_mode; in imx8_pcie_phy_power_on()
80 switch (imx8_phy->drvdata->variant) { in imx8_pcie_phy_power_on()
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| /linux/drivers/phy/marvell/ |
| H A D | phy-mvebu-a3700-utmi.c | 1 // SPDX-License-Identifier: GPL-2.0
9 * Marvell A3700 UTMI PHY driver
14 #include <linux/mfd/syscon.h>
17 #include <linux/phy/phy.h>
21 /* Armada 3700 UTMI PHY registers */
59 * struct mvebu_a3700_utmi_caps - PHY capabilities
61 * @usb32: Flag indicating which PHY is in use (impacts the register map):
62 * - The UTMI PHY wired to the USB3/USB2 controller (otg)
63 * - The UTMI PHY wired to the USB2 controller (host only)
64 * @ops: PHY operations
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| H A D | phy-mvebu-a3700-comphy.c | 1 // SPDX-License-Identifier: GPL-2.0
11 * Structure inspired from phy-mvebu-cp110-comphy.c written by Antoine Tenart.
20 #include <linux/mfd/syscon.h>
23 #include <linux/phy.h>
24 #include <linux/phy/phy.h>
36 /* SATA and USB3 PHY offset compared to SATA PHY */
40 * When accessing common PHY lane registers directly, we need to shift by 1,
41 * since the registers are 16-bit.
175 * This register is not from PHY lane register space. It only exists in the
176 * indirect register space, before the actual PHY lane 2 registers. So the
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| /linux/drivers/phy/rockchip/ |
| H A D | phy-rockchip-naneng-combphy.c | 1 // SPDX-License-Identifier: GPL-2.0
3 * Rockchip PIPE USB3.0 PCIE SATA Combo Phy driver
8 #include <dt-bindings/phy/phy.h>
10 #include <linux/mfd/syscon.h>
12 #include <linux/phy/phy.h>
23 /* RK3528 COMBO PHY REG */
62 /* RK3568 COMBO PHY REG */
122 /* RK3588 COMBO PHY registers */
126 /* RK3576 COMBO PHY registers */
201 struct phy *phy; member
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| H A D | phy-rockchip-usbdp.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Rockchip USBDP Combo PHY with Samsung IP block driver
5 * Copyright (C) 2021-2024 Rockchip Electronics Co., Ltd
9 #include <dt-bindings/phy/phy.h>
15 #include <linux/mfd/syscon.h>
19 #include <linux/phy/phy.h>
28 /* USBDP PHY Register Definitions */
115 /* u2phy-grf */
119 /* usb-grf */
123 /* usbdpphy-grf */
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| H A D | phy-rockchip-samsung-hdptx.c | 1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (c) 2021-2022 Rockchip Electronics Co., Ltd.
6 * Author: Algea Cao <algea.cao@rock-chips.com>
11 #include <linux/clk-provider.h>
13 #include <linux/mfd/syscon.h>
17 #include <linux/phy/phy.h>
396 struct phy *phy; member
693 /* voltage swing 0, pre-emphasis 0->3 */
701 /* voltage swing 1, pre-emphasis 0->2 */
708 /* voltage swing 2, pre-emphasis 0->1 */
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| H A D | phy-rockchip-inno-usb2.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Rockchip USB2.0 PHY with Innosilicon IP block driver
9 #include <linux/clk-provider.h>
11 #include <linux/extcon-provider.h>
21 #include <linux/phy/phy.h>
26 #include <linux/mfd/syscon.h>
50 * enum usb_chg_state - Different states involved in USB charger detection.
89 * struct rockchip_chg_det_reg - usb charger detect registers
115 * struct rockchip_usb2phy_port_cfg - usb-phy port configuration.
116 * @phy_sus: phy suspend register.
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| /linux/arch/arm/boot/dts/arm/ |
| H A D | arm-realview-pbx.dtsi | 23 #include <dt-bindings/interrupt-controller/irq.h>
24 #include <dt-bindings/gpio/gpio.h>
27 #address-cells = <1>;
28 #size-cells = <1>;
29 compatible = "arm,realview-pbx";
49 vmmc: regulator-vmmc {
50 compatible = "regulator-fixed";
51 regulator-name = "vmmc";
52 regulator-min-microvolt = <3300000>;
53 regulator-max-microvolt = <3300000>;
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| H A D | arm-realview-pb11mp.dts | 23 /dts-v1/;
24 #include <dt-bindings/interrupt-controller/irq.h>
25 #include <dt-bindings/gpio/gpio.h>
28 #address-cells = <1>;
29 #size-cells = <1>;
31 compatible = "arm,realview-pb11mp";
52 #address-cells = <1>;
53 #size-cells = <0>;
54 enable-method = "arm,realview-smp";
60 next-level-cache = <&L2>;
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| /linux/arch/arm64/boot/dts/broadcom/bcmbca/ |
| H A D | bcm4908.dtsi | 1 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
3 #include <dt-bindings/interrupt-controller/irq.h>
4 #include <dt-bindings/interrupt-controller/arm-gic.h>
5 #include <dt-bindings/phy/phy.h>
6 #include <dt-bindings/soc/bcm-pmb.h>
8 /dts-v1/;
11 interrupt-parent = <&gic>;
13 #address-cells = <2>;
14 #size-cells = <2>;
21 stdout-path = "serial0:115200n8";
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| /linux/drivers/pci/controller/dwc/ |
| H A D | pci-imx6.c | 1 // SPDX-License-Identifier: GPL-2.0
16 #include <linux/mfd/syscon.h>
17 #include <linux/mfd/syscon/imx6q-iomuxc-gpr.h>
18 #include <linux/mfd/syscon/imx7-iomuxc-gpr.h>
31 #include <linux/phy/pcie.h>
32 #include <linux/phy/phy.h>
37 #include "pcie-designware.h"
82 #define to_imx_pcie(x) dev_get_drvdata((x)->dev)
118 #define imx_check_flag(pci, val) (pci->drvdata->flags & val)
170 /* power domain for pcie phy */
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