/linux/tools/arch/arm64/include/asm/ |
H A D | sysreg.h | 38 #define sys_reg(op0, op1, crn, crm, op2) \ macro 43 #define sys_insn sys_reg 129 * come from here. The header relies on the definition of sys_reg() 138 #define SYS_SVCR_SMSTOP_SM_EL0 sys_reg(0, 3, 4, 2, 3) 139 #define SYS_SVCR_SMSTART_SM_EL0 sys_reg(0, 3, 4, 3, 3) 140 #define SYS_SVCR_SMSTOP_SMZA_EL0 sys_reg(0, 3, 4, 6, 3) 142 #define SYS_DBGBVRn_EL1(n) sys_reg(2, 0, 0, n, 4) 143 #define SYS_DBGBCRn_EL1(n) sys_reg(2, 0, 0, n, 5) 144 #define SYS_DBGWVRn_EL1(n) sys_reg(2, 0, 0, n, 6) 145 #define SYS_DBGWCRn_EL1(n) sys_reg(2, 0, 0, n, 7) [all …]
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/linux/arch/arm64/include/asm/ |
H A D | sysreg.h | 39 #define sys_reg(op0, op1, crn, crm, op2) \ macro 44 #define sys_insn sys_reg 113 #define SYS_PSTATE_PAN sys_reg(3, 0, 4, 2, 3) 164 * come from here. The header relies on the definition of sys_reg() 173 #define SYS_SVCR_SMSTOP_SM_EL0 sys_reg(0, 3, 4, 2, 3) 174 #define SYS_SVCR_SMSTART_SM_EL0 sys_reg(0, 3, 4, 3, 3) 175 #define SYS_SVCR_SMSTOP_SMZA_EL0 sys_reg(0, 3, 4, 6, 3) 177 #define SYS_DBGBVRn_EL1(n) sys_reg(2, 0, 0, n, 4) 178 #define SYS_DBGBCRn_EL1(n) sys_reg(2, 0, 0, n, 5) 179 #define SYS_DBGWVRn_EL1(n) sys_reg(2, 0, 0, n, 6) [all …]
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H A D | apple_m1_pmu.h | 10 #define SYS_IMP_APL_PMC0_EL1 sys_reg(3, 2, 15, 0, 0) 11 #define SYS_IMP_APL_PMC1_EL1 sys_reg(3, 2, 15, 1, 0) 12 #define SYS_IMP_APL_PMC2_EL1 sys_reg(3, 2, 15, 2, 0) 13 #define SYS_IMP_APL_PMC3_EL1 sys_reg(3, 2, 15, 3, 0) 14 #define SYS_IMP_APL_PMC4_EL1 sys_reg(3, 2, 15, 4, 0) 15 #define SYS_IMP_APL_PMC5_EL1 sys_reg(3, 2, 15, 5, 0) 16 #define SYS_IMP_APL_PMC6_EL1 sys_reg(3, 2, 15, 6, 0) 17 #define SYS_IMP_APL_PMC7_EL1 sys_reg(3, 2, 15, 7, 0) 18 #define SYS_IMP_APL_PMC8_EL1 sys_reg(3, 2, 15, 9, 0) 19 #define SYS_IMP_APL_PMC9_EL1 sys_reg(3, 2, 15, 10, 0) [all …]
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H A D | arm_dsu_pmu.h | 18 #define CLUSTERPMCR_EL1 sys_reg(3, 0, 15, 5, 0) 19 #define CLUSTERPMCNTENSET_EL1 sys_reg(3, 0, 15, 5, 1) 20 #define CLUSTERPMCNTENCLR_EL1 sys_reg(3, 0, 15, 5, 2) 21 #define CLUSTERPMOVSSET_EL1 sys_reg(3, 0, 15, 5, 3) 22 #define CLUSTERPMOVSCLR_EL1 sys_reg(3, 0, 15, 5, 4) 23 #define CLUSTERPMSELR_EL1 sys_reg(3, 0, 15, 5, 5) 24 #define CLUSTERPMINTENSET_EL1 sys_reg(3, 0, 15, 5, 6) 25 #define CLUSTERPMINTENCLR_EL1 sys_reg(3, 0, 15, 5, 7) 26 #define CLUSTERPMCCNTR_EL1 sys_reg(3, 0, 15, 6, 0) 27 #define CLUSTERPMXEVTYPER_EL1 sys_reg(3, 0, 15, 6, 1) [all …]
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H A D | esr.h | 274 sys_reg((((e) & ESR_ELx_SYS64_ISS_OP0_MASK) >> \ 286 sys_reg(3, \
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/linux/drivers/input/misc/ |
H A D | iqs626a.c | 446 struct iqs626_sys_reg sys_reg; member 463 struct iqs626_sys_reg *sys_reg = &iqs626->sys_reg; in iqs626_parse_events() local 473 thresh = sys_reg->ch_reg_ulp.thresh; in iqs626_parse_events() 474 hyst = &sys_reg->ch_reg_ulp.hyst; in iqs626_parse_events() 479 thresh = &sys_reg->tp_grp_reg.ch_reg_tp[0].thresh; in iqs626_parse_events() 480 hyst = &sys_reg->tp_grp_reg.hyst; in iqs626_parse_events() 487 thresh = sys_reg->ch_reg_gen[i].thresh; in iqs626_parse_events() 488 hyst = &sys_reg->ch_reg_gen[i].hyst; in iqs626_parse_events() 492 thresh = &sys_reg->ch_reg_hall.thresh; in iqs626_parse_events() 493 hyst = &sys_reg->ch_reg_hall.hyst; in iqs626_parse_events() [all …]
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/linux/arch/arm64/kvm/ |
H A D | emulate-nested.c | 578 sys_reg(3, 0, 0, 7, 7), CGT_HCR_TID3), 582 SR_RANGE_TRAP(sys_reg(3, 0, 11, 0, 0), 583 sys_reg(3, 0, 11, 15, 7), CGT_HCR_TIDCP), 584 SR_RANGE_TRAP(sys_reg(3, 1, 11, 0, 0), 585 sys_reg(3, 1, 11, 15, 7), CGT_HCR_TIDCP), 586 SR_RANGE_TRAP(sys_reg(3, 2, 11, 0, 0), 587 sys_reg(3, 2, 11, 15, 7), CGT_HCR_TIDCP), 588 SR_RANGE_TRAP(sys_reg(3, 3, 11, 0, 0), 589 sys_reg(3, 3, 11, 15, 7), CGT_HCR_TIDCP), 590 SR_RANGE_TRAP(sys_reg(3, 4, 11, 0, 0), [all …]
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H A D | sys_regs.h | 17 sys_reg((u32)(x)->Op0, (u32)(x)->Op1, \ 80 /* Index into sys_reg[], or 0 if we don't need to save it. */
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H A D | reset.c | 244 * Must be done after all the sys_reg reset. in kvm_reset_vcpu()
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H A D | sys_regs.c | 73 "sys_reg read to write-only register"); in read_from_write_only() 81 "sys_reg write to read-only register"); in write_to_read_only() 3640 kvm_err("sys_reg table %pS entry %d (%s) lacks reset\n", in check_sysreg_table() 3646 kvm_err("sys_reg table %pS entry %d (%s -> %s) out of order\n", in check_sysreg_table() 3686 * emulate_cp -- tries to match a sys_reg access in a handling table, and 3991 "Unsupported guest sys_reg access at: %lx [%08lx]\n", in emulate_sys_reg() 4240 /* We only do sys_reg for now. */ in id_to_sys_reg_desc() 4246 /* Not saved in the sys_reg array and not otherwise accessible? */ in id_to_sys_reg_desc() 4254 * These are the invariant sys_reg registers: we let the guest see the
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/linux/tools/testing/selftests/kvm/aarch64/ |
H A D | aarch32_id_regs.c | 43 GUEST_ASSERT_REG_RAZ(sys_reg(3, 0, 0, 3, 3)); in guest_main() 47 GUEST_ASSERT_REG_RAZ(sys_reg(3, 0, 0, 3, 7)); in guest_main() 116 KVM_ARM64_SYS_REG(sys_reg(3, 0, 0, 3, 3)), 118 KVM_ARM64_SYS_REG(sys_reg(3, 0, 0, 3, 7)),
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/linux/drivers/soc/qcom/ |
H A D | kryo-l2-accessors.c | 11 #define L2CPUSRSELR_EL1 sys_reg(3, 3, 15, 0, 6) 12 #define L2CPUSRDR_EL1 sys_reg(3, 3, 15, 0, 7)
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/linux/arch/arm/boot/dts/nvidia/ |
H A D | tegra20-tamonten.dtsi | 322 vin-sm0-supply = <&sys_reg>; 323 vin-sm1-supply = <&sys_reg>; 324 vin-sm2-supply = <&sys_reg>; 332 sys_reg: sys { label
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H A D | tegra20-paz00.dts | 342 vin-sm0-supply = <&sys_reg>; 343 vin-sm1-supply = <&sys_reg>; 344 vin-sm2-supply = <&sys_reg>; 352 sys_reg: sys { label
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H A D | tegra20-ventana.dts | 387 vin-sm0-supply = <&sys_reg>; 388 vin-sm1-supply = <&sys_reg>; 389 vin-sm2-supply = <&sys_reg>; 397 sys_reg: sys { label
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H A D | tegra20-harmony.dts | 329 vin-sm0-supply = <&sys_reg>; 330 vin-sm1-supply = <&sys_reg>; 331 vin-sm2-supply = <&sys_reg>; 339 sys_reg: sys { label
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H A D | tegra20-seaboard.dts | 402 vin-sm0-supply = <&sys_reg>; 403 vin-sm1-supply = <&sys_reg>; 404 vin-sm2-supply = <&sys_reg>; 412 sys_reg: sys { label
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H A D | tegra20-asus-tf101.dts | 617 vin-sm0-supply = <&sys_reg>; 618 vin-sm1-supply = <&sys_reg>; 619 vin-sm2-supply = <&sys_reg>; 627 sys_reg: sys { label
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H A D | tegra20-acer-a500-picasso.dts | 553 vin-sm0-supply = <&sys_reg>; 554 vin-sm1-supply = <&sys_reg>; 555 vin-sm2-supply = <&sys_reg>; 563 sys_reg: sys { label
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/linux/arch/arm/boot/dts/samsung/ |
H A D | exynos4.dtsi | 172 sys_reg: syscon@10010000 { label 221 samsung,sysreg = <&sys_reg>; 234 samsung,sysreg = <&sys_reg>; 247 samsung,sysreg = <&sys_reg>; 260 samsung,sysreg = <&sys_reg>; 711 samsung,sysreg = <&sys_reg>;
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/linux/arch/arm64/kernel/ |
H A D | cpufeature.c | 151 .sys_reg = SYS_##reg, \ 825 * its sys_reg() encoding. With the array arm64_ftr_regs sorted in the 849 * its sys_reg() encoding. This calls get_arm64_ftr_reg_nowarn(). 960 static void init_cpu_ftr_reg(u32 sys_reg, u64 new) in init_cpu_ftr_reg() argument 968 struct arm64_ftr_reg *reg = get_arm64_ftr_reg(sys_reg); in init_cpu_ftr_reg() 1578 return read_sanitised_ftr_reg(entry->sys_reg); in read_scoped_sysreg() 1580 return __read_sysreg_by_encoding(entry->sys_reg); in read_scoped_sysreg() 1590 regp = get_arm64_ftr_reg(entry->sys_reg); in has_user_cpuid_feature() 2186 boot_val = cpuid_feature_extract_field(read_sanitised_ftr_reg(entry->sys_reg), in has_address_auth_cpucap() 2191 sec_val = cpuid_feature_extract_field(__read_sysreg_by_encoding(entry->sys_reg), in has_address_auth_cpucap() [all …]
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/linux/Documentation/devicetree/bindings/regulator/ |
H A D | tps6586x.txt | 57 sys_reg: sys {
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/linux/Documentation/devicetree/bindings/display/samsung/ |
H A D | samsung,fimd.yaml | 179 samsung,sysreg = <&sys_reg>;
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/linux/arch/arm64/tools/ |
H A D | gen-sysreg.awk | 165 define("SYS_" reg, "sys_reg(" op0 ", " op1 ", " crn ", " crm ", " op2 ")")
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/linux/Documentation/devicetree/bindings/media/ |
H A D | samsung,fimc.yaml | 144 samsung,sysreg = <&sys_reg>;
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