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/linux/sound/pci/
H A Dad1889.h9 #define AD_DS_WSMC 0x00 /* wave/synthesis channel mixer control */
10 #define AD_DS_WSMC_SYEN 0x0004 /* synthesis channel enable */
31 #define AD_DS_SYDA 0x06 /* synthesis channel mix attenuation */
32 #define AD_DS_SYDA_RSYM 0x0080 /* right synthesis mute */
33 #define AD_DS_SYDA_RSYA 0x001f /* right synthesis attenuation */
34 #define AD_DS_SYDA_LSYM 0x8000 /* left synthesis mute */
35 #define AD_DS_SYDA_LSYA 0x3e00 /* left synthesis attenuation */
46 #define AD_DS_CCS_SYU 0x0004 /* synthesis channel underflow */
110 #define AD_DMA_DISR_SYNI 0x000004 /* synthesis channel interrupt */
129 #define AD_DMA_CHSS_SYNS 0x000004 /* synthesis channel stopped */
H A Dad1889.c640 snd_iprintf(buffer, "Synthesis output: %s\n", in snd_ad1889_proc_read()
648 snd_iprintf(buffer, "Synthesis FIFO: %d %s words\n\n", tmp, in snd_ad1889_proc_read()
H A Dcs4281.c301 #define BA0_FMSR 0x0730 /* FM Synthesis Status (ro) */
313 #define BA0_SSPM_FMEN (1<<1) /* FM Synthesis Block Enable */
329 #define BA0_FMLVC 0x0754 /* FM Synthesis Left Volume Control */
330 #define BA0_FMRVC 0x0758 /* FM Synthesis Right Volume Control */
/linux/tools/perf/bench/
H A Dsynthesize.c3 * Benchmark synthesis of perf events such as at the start of a 'perf
4 * record'. Synthesis is done on the current process and the 'dummy' event
137 "Computing performance of single threaded perf event synthesis by\n" in run_single_threaded()
200 printf(" Average synthesis took: %.3f usec (+- %.3f usec)\n", in do_run_multi_threaded()
227 "Computing performance of multi threaded perf event synthesis by\n" in run_multi_threaded()
238 printf(" Number of synthesis threads: %u\n", in run_multi_threaded()
/linux/drivers/staging/iio/frequency/
H A DKconfig3 # Direct Digital Synthesis drivers
5 menu "Direct Digital Synthesis"
H A DMakefile3 # Makefile for Direct Digital Synthesis drivers
/linux/Documentation/devicetree/bindings/display/
H A Dxylon,logicvc-display.yaml20 synthesis time. As a result, many of the device-tree bindings are meant to
21 reflect the synthesis configuration and must not be configured differently.
22 Matching synthesis parameters are provided when applicable.
/linux/drivers/accessibility/
H A DKconfig9 That includes braille devices, speech synthesis, keyboard
/linux/Documentation/devicetree/bindings/gpio/
H A Dbrcm,kona-gpio.yaml10 The Broadcom GPIO Controller IP can be configured prior to synthesis to
/linux/drivers/iio/frequency/
H A DKconfig4 # Direct Digital Synthesis drivers (DDS)
/linux/drivers/accessibility/speakup/
H A Dbuffers.c80 /* We have written something to the speech synthesis, so we are not in synth_buffer_add()
H A Dspeakup_soft.c449 /* We want to set the the speech synthesis punctuation level in softsynth_adjust()
/linux/Documentation/trace/rv/
H A Dlinear_temporal_logic.rst88 Monitor synthesis
/linux/drivers/clk/sunxi-ng/
H A Dccu_sdm.c78 * synthesis, in essence allowing the PLL to output any frequency
/linux/drivers/irqchip/
H A Dirq-dw-apb-ictl.c160 * have been removed by synthesis tool. in dw_apb_ictl_init()
/linux/tools/perf/util/
H A Dsession.h52 /** @itrace_synth_opts: AUX area tracing synthesis options. */
/linux/include/sound/
H A Dcs4231-regs.h148 #define CS4236_LEFT_MIX_CTRL 0x48 /* synthesis and left input mixer control */
/linux/tools/perf/Documentation/
H A Dperf-bench.txt310 Suite for evaluating perf's event synthesis performance.
/linux/tools/perf/
H A Dbuiltin-bench.c94 { "synthesize", "Benchmark perf event synthesis", bench_synthesize },
/linux/drivers/atm/
H A Dsuni.h24 #define SUNI_CSCS 0x06 /* Clock Synthesis Control and Status */
/linux/Documentation/ABI/testing/
H A Dsysfs-platform-dfl-fme22 data, which includes the synthesis date, seed and other
/linux/drivers/net/ethernet/xilinx/
H A Dll_temac.h309 /* TEMAC Synthesis features */
/linux/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/
H A Dnv04.c281 * synthesis of six nv4x traces, nearly each card doing a subtly in setPLL_double_lowregs()
/linux/drivers/zorro/
H A Dzorro.ids229 0820 Hardital Synthesis
/linux/drivers/spi/
H A Dspi-cadence.c517 * The depth of the TX FIFO is a synthesis configuration parameter of the SPI

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