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/linux/Documentation/fb/
H A Dviafb.modes10 # 640x480, 60 Hz, Non-Interlaced (25.175 MHz dotclock)
15 # Sync Width 3.813 us 0.064 ms
21 # Active Time 25.422 us 15.253 ms
28 mode "640x480-60"
31 timings 39722 48 16 33 10 96 2 endmode mode "480x640-60"
35 # 640x480, 75 Hz, Non-Interlaced (31.50 MHz dotclock)
40 # Sync Width 2.032 us 0.080 ms
46 # Active Time 20.317 us 12.800 ms
52 mode "640x480-75"
56 # 640x480, 85 Hz, Non-Interlaced (36.000 MHz dotclock)
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H A Dep93xx-fb.rst24 Note that the pixel clock value is in pico-seconds. You can use the
57 EP93XXFB_SYNC_BLANK_HIGH Blank signal is active high. By
58 default the blank signal is active low.
60 EP93XXFB_SYNC_HORIZ_HIGH Horizontal sync is active high. By
61 default the horizontal sync is active low.
63 EP93XXFB_SYNC_VERT_HIGH Vertical sync is active high. By
64 default the vertical sync is active high.
96 struct ep93xxfb_mach_info *mach_info = pdev->dev.platform_data;
107 video=XRESxYRES[-BPP][@REFRESH]
109 If the EP93xx video driver is built-in then the video mode is set on
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H A Dpxafb.rst10 modprobe pxafb options=vmem:2M,mode:640x480-8,passive
14 video=pxafb:vmem:2M,mode:640x480-8,passive
21 mode:XRESxYRES[-BPP]
47 Display margins and sync times
53 active | passive => LCCR0_PAS
55 Active (TFT) or Passive (STN) display
67 Horizontal and vertical sync. 0 => active low, 1 => active
76 Output Enable Polarity. 0 => active low, 1 => active high
87 PXA27x and later processors support overlay1 and overlay2 on-top of the
88 base framebuffer (although under-neath the base is also possible). They
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/linux/include/video/
H A Ddisplay_timing.h1 /* SPDX-License-Identifier: GPL-2.0-only */
30 /* drive sync on pos. edge */
32 /* drive sync on neg. edge */
52 * Example: hsync active high, vsync active low
54 * Active Video
56 * |<- sync ->|<- back ->|<----- active ----->|<- front ->|<- sync..
66 struct timing_entry hactive; /* hor. active video */
69 struct timing_entry hsync_len; /* hor. sync len */
71 struct timing_entry vactive; /* ver. active video */
74 struct timing_entry vsync_len; /* ver. sync len */
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/linux/Documentation/devicetree/bindings/soc/fsl/cpm_qe/
H A Dfsl,qe-tsa.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/soc/fsl/cpm_qe/fsl,qe-tsa.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: PowerQUICC QE Time-slot assigner (TSA) controller
10 - Herve Codina <herve.codina@bootlin.com>
13 The TSA is the time-slot assigner that can be found on some PowerQUICC SoC.
14 Its purpose is to route some TDM time-slots to other internal serial
20 - enum:
21 - fsl,mpc8321-tsa
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/linux/drivers/net/wireless/intel/iwlwifi/mvm/
H A Dtime-sync.c1 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
7 #include "time-sync.h"
12 skb_queue_head_init(&data->frame_list); in iwl_mvm_init_time_sync()
17 struct ieee80211_mgmt *mgmt = (void *)skb->data; in iwl_mvm_is_skb_match()
21 skb_dialog_token = mgmt->u.action.u.wnm_timing_msr.dialog_token; in iwl_mvm_is_skb_match()
23 skb_dialog_token = mgmt->u.action.u.ftm.dialog_token; in iwl_mvm_is_skb_match()
25 if ((ether_addr_equal(mgmt->sa, addr) || in iwl_mvm_is_skb_match()
26 ether_addr_equal(mgmt->da, addr)) && in iwl_mvm_is_skb_match()
39 * in the queue, they did not get a time sync notification and are in iwl_mvm_time_sync_find_skb()
42 while ((skb = skb_dequeue(&mvm->time_sync.frame_list))) { in iwl_mvm_time_sync_find_skb()
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/linux/include/drm/
H A Ddrm_modes.h3 * Copyright © 2007-2008 Dave Airlie
4 * Copyright © 2007-2008 Intel Corporation
46 * enum drm_mode_status - hardware support status of a mode
68 * @MODE_HSYNC_NARROW: horizontal sync too narrow
69 * @MODE_HSYNC_WIDE: horizontal sync too wide
72 * @MODE_VSYNC_NARROW: vertical sync too narrow
73 * @MODE_VSYNC_WIDE: vertical sync too wide
129 MODE_STALE = -3,
130 MODE_BAD = -2,
131 MODE_ERROR = -1
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/linux/Documentation/devicetree/bindings/display/tilcdc/
H A Dpanel.txt1 Device-Tree bindings for tilcdc DRM generic panel output driver
4 - compatible: value should be "ti,tilcdc,panel".
5 - panel-info: configuration info to configure LCDC correctly for the panel
6 - ac-bias: AC Bias Pin Frequency
7 - ac-bias-intrpt: AC Bias Pin Transitions per Interrupt
8 - dma-burst-sz: DMA burst size
9 - bpp: Bits per pixel
10 - fdd: FIFO DMA Request Delay
11 - sync-edge: Horizontal and Vertical Sync Edge: 0=rising 1=falling
12 - sync-ctrl: Horizontal and Vertical Sync: Control: 0=ignore
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/linux/drivers/accel/habanalabs/common/
H A Dstate_dump.c1 // SPDX-License-Identifier: GPL-2.0
13 * hl_format_as_binary - helper function, format an integer as binary
37 buf_len -= 3; in hl_format_as_binary()
43 bit = n & (1 << (sizeof(n) * BITS_PER_BYTE - 1)); in hl_format_as_binary()
58 * resize_to_fit - helper function, resize buffer to fit given amount of data
79 return -ENOMEM; in resize_to_fit()
89 * hl_snprintf_resize() - print formatted data to buffer, resize as needed
113 return -EINVAL; in hl_snprintf_resize()
116 length = vsnprintf(*buf + *offset, *size - *offset, format, args); in hl_snprintf_resize()
125 length = vsnprintf(*buf + *offset, *size - *offset, format, in hl_snprintf_resize()
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/linux/drivers/gpu/drm/mcde/
H A Dmcde_display_regs.h1 /* SPDX-License-Identifier: GPL-2.0 */
236 #define MCDE_TVBL1_BSL1_SHIFT 16 /* VSW vertical sync pulse width 11 bits */
253 * 0 = 1 pixel HBP, 255 = 256 pixels, so actual value - 1
262 #define MCDE_TVLBALW_LBW_SHIFT 0 /* HSW horizonal sync width, line blanking width 11 bits */
263 #define MCDE_TVLBALW_ALW_SHIFT 16 /* HFP horizontal front porch, active line width 11 bits */
281 /* inverted vertical sync pulse for HRTFT 0 = active low, 1 active high */
283 /* inverted vertical sync, 0 = active high (the normal), 1 = active low */
285 /* inverted horizontal sync, 0 = active high (the normal), 1 = active low */
289 /* invert output enable 0 = active high, 1 = active low */
333 #define MCDE_VSCRC_VSPOL BIT(27) /* 0 active high, 1 active low */
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/linux/drivers/net/ethernet/intel/ice/
H A Dice_dpll.h1 /* SPDX-License-Identifier: GPL-2.0 */
12 * enum ice_dpll_pin_sw - enumerate ice software pin indices:
23 /** ice_dpll_pin - store info about pins
35 * @ref_sync: store id of reference sync pin
54 bool active; member
58 /** ice_dpll - store info required for DPLL control
66 * @phase_offset: phase offset of active pin vs dpll signal
67 * @prev_phase_offset: previous phase offset of active pin vs dpll signal
69 * @dpll_state: current dpll sync state
70 * @prev_dpll_state: last dpll sync state
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/linux/tools/testing/selftests/sync/
H A Dsync_wait.c2 * sync fence wait tests
3 * Copyright 2015-2016 Collabora Ltd.
28 #include "sync.h"
36 int valid, active, signaled, ret; in test_fence_multi_timeline_wait() local
53 active = sync_fence_count_with_status(merged, FENCE_STATUS_ACTIVE); in test_fence_multi_timeline_wait()
54 ASSERT(active == 3, "Fence signaled too early!\n"); in test_fence_multi_timeline_wait()
61 active = sync_fence_count_with_status(merged, FENCE_STATUS_ACTIVE); in test_fence_multi_timeline_wait()
63 ASSERT(active == 2 && signaled == 1, in test_fence_multi_timeline_wait()
67 active = sync_fence_count_with_status(merged, FENCE_STATUS_ACTIVE); in test_fence_multi_timeline_wait()
69 ASSERT(active == 1 && signaled == 2, in test_fence_multi_timeline_wait()
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H A Dsync_fence.c2 * sync fence tests with one timeline
3 * Copyright 2015-2016 Collabora Ltd.
28 #include "sync.h"
48 /* Advance timeline from 0 -> 1 */ in test_fence_one_timeline_wait()
96 /* confirm all fences have one active point (even d) */ in test_fence_one_timeline_merge()
98 "a has too many active fences!\n"); in test_fence_one_timeline_merge()
100 "b has too many active fences!\n"); in test_fence_one_timeline_merge()
102 "c has too many active fences!\n"); in test_fence_one_timeline_merge()
104 "d has too many active fences!\n"); in test_fence_one_timeline_merge()
/linux/drivers/media/i2c/
H A Dths8200.c2 * ths8200 - Texas Instruments THS8200 video encoder driver
23 #include <linux/v4l2-dv-timings.h>
25 #include <media/v4l2-dv-timings.h>
26 #include <media/v4l2-async.h>
27 #include <media/v4l2-device.h>
33 MODULE_PARM_DESC(debug, "debug level (0-2)");
93 /* To set specific bits in the register, a clear-mask is given (to be AND-ed),
94 * and then the value-mask (to be OR-ed).
108 reg->val = ths8200_read(sd, reg->reg & 0xff); in ths8200_g_register()
109 reg->size = 1; in ths8200_g_register()
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/linux/drivers/net/wireless/ralink/rt2x00/
H A Drt2x00config.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 Copyright (C) 2004 - 2009 Ivo van Doorn <IvDoorn@gmail.com>
31 conf.sync = TSF_SYNC_ADHOC; in rt2x00lib_config_intf()
35 conf.sync = TSF_SYNC_AP_NONE; in rt2x00lib_config_intf()
38 conf.sync = TSF_SYNC_INFRA; in rt2x00lib_config_intf()
41 conf.sync = TSF_SYNC_NONE; in rt2x00lib_config_intf()
60 if (mac || (!rt2x00dev->intf_ap_count && !rt2x00dev->intf_sta_count)) in rt2x00lib_config_intf()
62 if (bssid || (!rt2x00dev->intf_ap_count && !rt2x00dev->intf_sta_count)) in rt2x00lib_config_intf()
65 rt2x00dev->ops->lib->config_intf(rt2x00dev, intf, &conf, flags); in rt2x00lib_config_intf()
79 erp.short_preamble = bss_conf->use_short_preamble; in rt2x00lib_config_erp()
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/linux/Documentation/devicetree/bindings/media/
H A Drenesas,drif.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Renesas R-Car Gen3 Digital Radio Interface Controller (DRIF)
10 - Ramesh Shanmugasundaram <rashanmu@gmail.com>
11 - Fabrizio Castro <fabrizio.castro.jz@renesas.com>
14 R-Car Gen3 DRIF is a SPI like receive only slave device. A general
17 +---------------------+ +---------------------+
18 | |-----SCK------->|CLK |
19 | Master |-----SS-------->|SYNC DRIFn (slave) |
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/linux/include/uapi/linux/
H A Dnet_tstamp.h1 /* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
50 SOF_TIMESTAMPING_MASK = (SOF_TIMESTAMPING_LAST - 1) |
66 * struct so_timestamping - SO_TIMESTAMPING parameter
78 * struct hwtstamp_config - %SIOCGHWTSTAMP and %SIOCSHWTSTAMP parameter
96 /* possible values for hwtstamp_config->flags */
99 * With this flag, the user could get bond active interfac
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H A Dip_vs.h1 /* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
23 #define IP_VS_SVC_F_ONEPACKET 0x0004 /* one-packet scheduling */
38 * IPVS sync daemon states
88 #define IP_VS_CONN_F_SYNC 0x0020 /* entry created by sync */
168 /* thresholds for active connections */
236 __u32 activeconns; /* active connections */
281 /* sync daemon state (master/backup) */
321 IPVS_CMD_NEW_DAEMON, /* start sync daemon */
322 IPVS_CMD_DEL_DAEMON, /* stop sync daemon */
323 IPVS_CMD_GET_DAEMON, /* get sync daemon status */
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/linux/fs/netfs/
H A Ddirect_read.c1 // SPDX-License-Identifier: GPL-2.0-or-later
21 struct netfs_io_request *rreq = subreq->rreq; in netfs_prepare_dio_read_iterator()
24 rsize = umin(subreq->len, rreq->io_streams[0].sreq_max_len); in netfs_prepare_dio_read_iterator()
25 subreq->len = rsize; in netfs_prepare_dio_read_iterator()
27 if (unlikely(rreq->io_streams[0].sreq_max_segs)) { in netfs_prepare_dio_read_iterator()
28 size_t limit = netfs_limit_iter(&rreq->buffer.iter, 0, rsize, in netfs_prepare_dio_read_iterator()
29 rreq->io_streams[0].sreq_max_segs); in netfs_prepare_dio_read_iterator()
32 subreq->len = limit; in netfs_prepare_dio_read_iterator()
39 subreq->io_iter = rreq->buffer.iter; in netfs_prepare_dio_read_iterator()
40 iov_iter_truncate(&subreq->io_iter, subreq->len); in netfs_prepare_dio_read_iterator()
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/linux/Documentation/wmi/devices/
H A Dlenovo-wmi-gamezone.rst1 .. SPDX-License-Identifier: GPL-2.0-or-later
4 Lenovo WMI Interface Gamezone Driver (lenovo-wmi-gamezone)
15 -------------
17 WMI GUID ``887B54E3-DDDC-4B2C-8B88-68A26A8835D0``
19 The Gamezone Data WMI interface provides platform-profile and fan curve
27 - low-power, blue LED
28 - balanced, white LED
29 - performance, red LED
30 - max-power, purple LED
31 - custom, purple LED
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/linux/arch/mips/cavium-octeon/executive/
H A Dcvmx-spi.c7 * Copyright (c) 2003-2008 Cavium Networks
14 * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
21 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
34 #include <asm/octeon/cvmx-config.h>
36 #include <asm/octeon/cvmx-pko.h>
37 #include <asm/octeon/cvmx-spi.h>
39 #include <asm/octeon/cvmx-spxx-defs.h>
40 #include <asm/octeon/cvmx-stxx-defs.h>
41 #include <asm/octeon/cvmx-srxx-defs.h>
98 * active) or as a halfplex (either the Tx data path is
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/linux/drivers/gpu/drm/bridge/analogix/
H A Danalogix-i2c-txcommon.h1 /* SPDX-License-Identifier: GPL-2.0-only */
104 /* Active Line Status Low Byte Register */
107 /* Active Line Status High Byte Register */
113 /* Vertical SYNC Width Status Register */
125 /* Active Pixel Status Low Byte Register */
128 /* Active Pixel Status High Byte Register */
137 /* Horizontal SYNC Width Status Low Byte Register */
140 /* Horizontal SYNC Width Status High Byte Register */
200 #define SP_COMMON_INT_STATUS_BASE (0xf1 - 1)
224 #define SP_COMMON_INT_MASK_BASE (0xf8 - 1)
/linux/Documentation/userspace-api/media/v4l/
H A Dvidioc-g-dv-timings.rst1 .. SPDX-License-Identifier: GFDL-1.1-no-invariants-or-later
13 VIDIOC_G_DV_TIMINGS - VIDIOC_S_DV_TIMINGS - VIDIOC_SUBDEV_G_DV_TIMINGS - VIDIOC_SUBDEV_S_DV_TIMINGS…
56 registered in read-only mode is not allowed. An error is returned and the errno
57 variable is set to ``-EPERM``.
59 The ``linux/v4l2-dv-timings.h`` header can be used to get the timings of
68 On success 0 is returned, on error -1 and the ``errno`` variable is set
70 :ref:`Generic Error Codes <gen-errors>` chapter.
83 ``VIDIOC_SUBDEV_S_DV_TIMINGS`` has been called on a read-only subdevice.
91 .. flat-table:: struct v4l2_bt_timings
92 :header-rows: 0
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/linux/Documentation/devicetree/bindings/mux/
H A Dadi,adg792a.txt4 - compatible : "adi,adg792a" or "adi,adg792g"
5 - #mux-control-cells : <0> if parallel (the three muxes are bound together
8 * Standard mux-controller bindings as described in mux-controller.yaml
11 - gpio-controller : if present, #gpio-cells below is required.
12 - #gpio-cells : should be <2>
13 - First cell is the GPO line number, i.e. 0 or 1
14 - Second cell is used to specify active high (0)
15 or active low (1)
18 - idle-state : if present, array of states that the mux controllers will have
32 mux: mux-controller@50 {
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/linux/drivers/macintosh/
H A Dvia-cuda.c1 // SPDX-License-Identifier: GPL-2.0
38 /* VIA registers - spaced 0x200 bytes apart */
40 #define B 0 /* B-side data */
41 #define A RS /* A-side data */
42 #define DIRB (2*RS) /* B-side direction (1=output) */
43 #define DIRA (3*RS) /* A-side direction (1=output) */
55 #define ANH (15*RS) /* A-side data, no handshake */
62 * ----------------+------------------------------------------
63 * PB3 (input) | Transceiver session (active low)
64 * PB4 (output) | VIA full (active high)
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