Home
last modified time | relevance | path

Searched full:switch (Results 1 – 25 of 7695) sorted by relevance

12345678910>>...308

/linux/sound/soc/codecs/
H A Dlm49453.c227 SOC_DAPM_SINGLE("Port1_1 Switch", LM49453_P0_DACHPL1_REG, 0, 1, 0),
228 SOC_DAPM_SINGLE("Port1_2 Switch", LM49453_P0_DACHPL1_REG, 1, 1, 0),
229 SOC_DAPM_SINGLE("Port1_3 Switch", LM49453_P0_DACHPL1_REG, 2, 1, 0),
230 SOC_DAPM_SINGLE("Port1_4 Switch", LM49453_P0_DACHPL1_REG, 3, 1, 0),
231 SOC_DAPM_SINGLE("Port1_5 Switch", LM49453_P0_DACHPL1_REG, 4, 1, 0),
232 SOC_DAPM_SINGLE("Port1_6 Switch", LM49453_P0_DACHPL1_REG, 5, 1, 0),
233 SOC_DAPM_SINGLE("Port1_7 Switch", LM49453_P0_DACHPL1_REG, 6, 1, 0),
234 SOC_DAPM_SINGLE("Port1_8 Switch", LM49453_P0_DACHPL1_REG, 7, 1, 0),
235 SOC_DAPM_SINGLE("DMIC1L Switch", LM49453_P0_DACHPL2_REG, 0, 1, 0),
236 SOC_DAPM_SINGLE("DMIC1R Switch", LM49453_P0_DACHPL2_REG, 1, 1, 0),
[all …]
H A Disabelle.c233 SOC_DAPM_SINGLE("DAC1L Playback Switch", ISABELLE_HSDRV_CFG1_REG, 7, 1, 0),
234 SOC_DAPM_SINGLE("APGA1 Playback Switch", ISABELLE_HSDRV_CFG1_REG, 6, 1, 0),
238 SOC_DAPM_SINGLE("DAC1R Playback Switch", ISABELLE_HSDRV_CFG1_REG, 5, 1, 0),
239 SOC_DAPM_SINGLE("APGA2 Playback Switch", ISABELLE_HSDRV_CFG1_REG, 4, 1, 0),
243 SOC_DAPM_SINGLE("DAC2L Playback Switch", ISABELLE_HFLPGA_CFG_REG, 7, 1, 0),
244 SOC_DAPM_SINGLE("APGA1 Playback Switch", ISABELLE_HFLPGA_CFG_REG, 6, 1, 0),
248 SOC_DAPM_SINGLE("DAC2R Playback Switch", ISABELLE_HFRPGA_CFG_REG, 7, 1, 0),
249 SOC_DAPM_SINGLE("APGA2 Playback Switch", ISABELLE_HFRPGA_CFG_REG, 6, 1, 0),
253 SOC_DAPM_SINGLE("DAC2L Playback Switch", ISABELLE_EARDRV_CFG1_REG, 7, 1, 0),
254 SOC_DAPM_SINGLE("APGA1 Playback Switch", ISABELLE_EARDRV_CFG1_REG, 6, 1, 0),
[all …]
H A Dtlv320aic3x.c126 switch (reg) { in aic3x_volatile_reg()
212 switch (event) { in mic_bias_event()
386 SOC_DOUBLE_R("Line Playback Switch", LLOPM_CTRL, RLOPM_CTRL, 3,
390 SOC_DOUBLE_R("HP Playback Switch", HPLOUT_CTRL, HPROUT_CTRL, 3,
394 SOC_DOUBLE_R("HPCOM Playback Switch", HPLCOM_CTRL, HPRCOM_CTRL, 3,
401 SOC_DOUBLE_R("AGC Switch", LAGC_CTRL_A, RAGC_CTRL_A, 7, 0x01, 0),
410 SOC_DOUBLE("De-emphasis Switch", AIC3X_CODEC_DFILT_CTRL, 2, 0, 0x01, 0),
415 SOC_DOUBLE_R("PGA Capture Switch", LADC_VOL, RADC_VOL, 7, 0x01, 1),
474 SOC_SINGLE("Mono Playback Switch", MONOLOPM_CTRL, 3, 0x01, 0),
506 SOC_DAPM_SINGLE("PGAL Bypass Switch", PGAL_2_LLOPM_VOL, 7, 1, 0),
[all …]
H A Dwm9090.c70 switch (reg) { in wm9090_volatile()
85 switch (reg) { in wm9090_readable()
170 SOC_SINGLE("IN1A Switch", WM9090_IN1_LINE_INPUT_A_VOLUME, 7, 1, 1),
171 SOC_SINGLE("IN1A ZC Switch", WM9090_IN1_LINE_INPUT_A_VOLUME, 6, 1, 0),
175 SOC_SINGLE("IN2A Switch", WM9090_IN2_LINE_INPUT_A_VOLUME, 7, 1, 1),
176 SOC_SINGLE("IN2A ZC Switch", WM9090_IN2_LINE_INPUT_A_VOLUME, 6, 1, 0),
178 SOC_SINGLE("MIXOUTL Switch", WM9090_OUTPUT_MIXER3, 8, 1, 1),
184 SOC_SINGLE("MIXOUTR Switch", WM9090_OUTPUT_MIXER4, 8, 1, 1),
190 SOC_SINGLE("SPKMIX Switch", WM9090_SPKMIXL_ATTENUATION, 8, 1, 1),
198 SOC_DOUBLE_R("Headphone Switch", WM9090_LEFT_OUTPUT_VOLUME,
[all …]
H A Dak4535.c57 switch (reg) { in ak4535_volatile()
80 SOC_SINGLE("ALC2 Switch", AK4535_SIG1, 1, 1, 0),
86 SOC_SINGLE("Mic Boost (+20dB) Switch", AK4535_MIC, 0, 1, 0),
91 SOC_SINGLE("ALC 1 Switch", AK4535_ALC1, 5, 1, 0),
92 SOC_SINGLE("ALC 2 Switch", AK4535_ALC1, 6, 1, 0),
103 SOC_DAPM_SINGLE("Mic Sidetone Switch", AK4535_SIG1, 4, 1, 0),
104 SOC_DAPM_SINGLE("Mono Playback Switch", AK4535_SIG1, 5, 1, 0),
109 SOC_DAPM_SINGLE("Mic Sidetone Switch", AK4535_SIG2, 4, 1, 0),
110 SOC_DAPM_SINGLE("Playback Switch", AK4535_SIG2, 7, 1, 0),
111 SOC_DAPM_SINGLE("Aux Bypass Switch", AK4535_SIG2, 5, 1, 0),
[all …]
H A Drt5645.c490 switch (reg) { in rt5645_volatile_register()
526 switch (reg) { in rt5645_readable_register()
800 SOC_DOUBLE("Speaker Channel Switch", RT5645_SPK_VOL,
811 SOC_DOUBLE("Headphone Channel Switch", RT5645_HP_VOL,
817 SOC_DOUBLE("OUT Playback Switch", RT5645_LOUT1,
819 SOC_DOUBLE("OUT Channel Switch", RT5645_LOUT1,
825 SOC_DOUBLE("DAC2 Playback Switch", RT5645_DAC_CTRL,
843 SOC_DOUBLE("ADC Capture Switch", RT5645_STO1_ADC_DIG_VOL,
847 SOC_DOUBLE("Mono ADC Capture Switch", RT5645_MONO_ADC_DIG_VOL,
861 SOC_SINGLE("I2S2 Func Switch", RT5645_GPIO_CTRL1, RT5645_I2S2_SEL_SFT,
[all …]
/linux/sound/soc/mediatek/mt8186/
H A Dmt8186-dai-i2s.c223 SOC_DAPM_SINGLE_AUTODISABLE("DL1_CH1 Switch", AFE_CONN0,
225 SOC_DAPM_SINGLE_AUTODISABLE("DL2_CH1 Switch", AFE_CONN0,
227 SOC_DAPM_SINGLE_AUTODISABLE("DL3_CH1 Switch", AFE_CONN0,
229 SOC_DAPM_SINGLE_AUTODISABLE("DL12_CH1 Switch", AFE_CONN0,
231 SOC_DAPM_SINGLE_AUTODISABLE("DL12_CH3 Switch", AFE_CONN0,
233 SOC_DAPM_SINGLE_AUTODISABLE("DL6_CH1 Switch", AFE_CONN0_1,
235 SOC_DAPM_SINGLE_AUTODISABLE("DL4_CH1 Switch", AFE_CONN0_1,
237 SOC_DAPM_SINGLE_AUTODISABLE("DL5_CH1 Switch", AFE_CONN0_1,
239 SOC_DAPM_SINGLE_AUTODISABLE("DL8_CH1 Switch", AFE_CONN0_1,
241 SOC_DAPM_SINGLE_AUTODISABLE("GAIN1_OUT_CH1 Switch", AFE_CONN0,
[all …]
H A Dmt8186-dai-adda.c60 SOC_DAPM_SINGLE_AUTODISABLE("DL1_CH1 Switch", AFE_CONN3, I_DL1_CH1, 1, 0),
61 SOC_DAPM_SINGLE_AUTODISABLE("DL12_CH1 Switch", AFE_CONN3, I_DL12_CH1, 1, 0),
62 SOC_DAPM_SINGLE_AUTODISABLE("DL2_CH1 Switch", AFE_CONN3, I_DL2_CH1, 1, 0),
63 SOC_DAPM_SINGLE_AUTODISABLE("DL3_CH1 Switch", AFE_CONN3, I_DL3_CH1, 1, 0),
64 SOC_DAPM_SINGLE_AUTODISABLE("DL4_CH1 Switch", AFE_CONN3_1, I_DL4_CH1, 1, 0),
65 SOC_DAPM_SINGLE_AUTODISABLE("DL5_CH1 Switch", AFE_CONN3_1, I_DL5_CH1, 1, 0),
66 SOC_DAPM_SINGLE_AUTODISABLE("DL6_CH1 Switch", AFE_CONN3_1, I_DL6_CH1, 1, 0),
67 SOC_DAPM_SINGLE_AUTODISABLE("DL8_CH1 Switch", AFE_CONN3_1, I_DL8_CH1, 1, 0),
68 SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH2 Switch", AFE_CONN3,
70 SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH1 Switch", AFE_CONN3,
[all …]
H A Dmt8186-dai-hostless.c24 {"ADDA_DL_CH1", "ADDA_UL_CH1 Switch", "Hostless LPBK DL"},
25 {"ADDA_DL_CH1", "ADDA_UL_CH2 Switch", "Hostless LPBK DL"},
26 {"ADDA_DL_CH2", "ADDA_UL_CH1 Switch", "Hostless LPBK DL"},
27 {"ADDA_DL_CH2", "ADDA_UL_CH2 Switch", "Hostless LPBK DL"},
28 {"I2S1_CH1", "ADDA_UL_CH1 Switch", "Hostless LPBK DL"},
29 {"I2S1_CH2", "ADDA_UL_CH2 Switch", "Hostless LPBK DL"},
30 {"I2S3_CH1", "ADDA_UL_CH1 Switch", "Hostless LPBK DL"},
31 {"I2S3_CH1", "ADDA_UL_CH2 Switch", "Hostless LPBK DL"},
32 {"I2S3_CH2", "ADDA_UL_CH1 Switch", "Hostless LPBK DL"},
33 {"I2S3_CH2", "ADDA_UL_CH2 Switch", "Hostless LPBK DL"},
[all …]
H A Dmt8186-dai-src.c101 switch (rate) { in mtk_get_src_freq_mode()
337 switch (event) { in mtk_hw_src_event()
379 SOC_DAPM_SINGLE_AUTODISABLE("DL1_CH1 Switch", AFE_CONN40,
381 SOC_DAPM_SINGLE_AUTODISABLE("DL2_CH1 Switch", AFE_CONN40,
383 SOC_DAPM_SINGLE_AUTODISABLE("DL3_CH1 Switch", AFE_CONN40,
385 SOC_DAPM_SINGLE_AUTODISABLE("DL4_CH1 Switch", AFE_CONN40_1,
387 SOC_DAPM_SINGLE_AUTODISABLE("DL6_CH1 Switch", AFE_CONN40_1,
389 SOC_DAPM_SINGLE_AUTODISABLE("I2S0_CH1 Switch", AFE_CONN40,
391 SOC_DAPM_SINGLE_AUTODISABLE("DL5_CH1 Switch", AFE_CONN40_1,
396 SOC_DAPM_SINGLE_AUTODISABLE("DL1_CH2 Switch", AFE_CONN41,
[all …]
/linux/sound/soc/mediatek/mt8195/
H A Dmt8195-dai-etdm.c142 switch (id) { in mt8195_afe_etdm_is_valid()
162 switch (id) { in mt8195_afe_hdmitx_dptx_is_valid()
199 switch (dai_id) { in get_etdm_reg()
249 switch (dai_id) { in get_etdm_dir()
283 switch (source_sel) { in sync_to_dai_id()
319 SOC_DAPM_SINGLE_AUTODISABLE("I020 Switch", AFE_CONN48, 20, 1, 0),
320 SOC_DAPM_SINGLE_AUTODISABLE("I022 Switch", AFE_CONN48, 22, 1, 0),
321 SOC_DAPM_SINGLE_AUTODISABLE("I046 Switch", AFE_CONN48_1, 14, 1, 0),
322 SOC_DAPM_SINGLE_AUTODISABLE("I070 Switch", AFE_CONN48_2, 6, 1, 0),
326 SOC_DAPM_SINGLE_AUTODISABLE("I021 Switch", AFE_CONN49, 21, 1, 0),
[all …]
/linux/sound/soc/sunxi/
H A Dsun50i-codec-analog.c131 SOC_DAPM_DOUBLE_R("Mic1 Playback Switch",
135 SOC_DAPM_DOUBLE_R("Mic2 Playback Switch",
139 SOC_DAPM_DOUBLE_R("Line In Playback Switch",
143 SOC_DAPM_DOUBLE_R("DAC Playback Switch",
147 SOC_DAPM_DOUBLE_R("DAC Reversed Playback Switch",
155 SOC_DAPM_DOUBLE_R("Mic1 Capture Switch",
159 SOC_DAPM_DOUBLE_R("Mic2 Capture Switch",
163 SOC_DAPM_DOUBLE_R("Line In Capture Switch",
167 SOC_DAPM_DOUBLE_R("Mixer Capture Switch",
171 SOC_DAPM_DOUBLE_R("Mixer Reversed Capture Switch",
[all …]
H A Dsun8i-codec-analog.c117 SOC_DAPM_DOUBLE_R("DAC Playback Switch",
121 SOC_DAPM_DOUBLE_R("DAC Reversed Playback Switch",
125 SOC_DAPM_DOUBLE_R("Line In Playback Switch",
129 SOC_DAPM_DOUBLE_R("Mic1 Playback Switch",
133 SOC_DAPM_DOUBLE_R("Mic2 Playback Switch",
141 SOC_DAPM_DOUBLE_R("DAC Playback Switch",
145 SOC_DAPM_DOUBLE_R("DAC Reversed Playback Switch",
149 SOC_DAPM_DOUBLE_R("Mic1 Playback Switch",
157 SOC_DAPM_DOUBLE_R("Mixer Capture Switch",
161 SOC_DAPM_DOUBLE_R("Mixer Reversed Capture Switch",
[all …]
/linux/Documentation/networking/dsa/
H A Ddsa.rst5 This document describes the **Distributed Switch Architecture (DSA)** subsystem
13 The Distributed Switch Architecture subsystem was primarily designed to
19 they configured/queried a switch port network device or a regular network
22 An Ethernet switch typically comprises multiple front-panel ports and one
25 receiving Ethernet frames from the switch. This is a very common setup for all
34 of multiple switches connected to each other is called a "switch tree".
41 The ideal case for using DSA is when an Ethernet switch supports a "switch tag"
42 which is a hardware feature making the switch insert a specific tag for each
57 - the "cpu" port is the Ethernet switch facing side of the management
69 Switch tagging protocols
[all …]
H A Dbcm_sf2.rst2 Broadcom Starfighter 2 Ethernet switch driver
5 Broadcom's Starfighter 2 Ethernet switch hardware block is commonly found and
12 The switch is typically deployed in a configuration involving between 5 to 13
21 The switch also supports specific congestion control features which allow MoCA
26 The switch hardware block is typically interfaced using MMIO accesses and
29 - ``SWITCH_CORE``: common switch registers
30 - ``SWITCH_REG``: external interfaces switch register
45 The SF2 switch is configured to enable a Broadcom specific 4-bytes switch tag
46 which gets inserted by the switch for every packet forwarded to the CPU
60 device_node pointers which are then accessible by the switch driver setup
[all …]
/linux/drivers/usb/roles/
H A Dclass.c3 * USB Role Switch Support
50 ret = sysfs_create_link(&connector->kobj, &dev->kobj, "usb-role-switch"); in connector_bind()
59 sysfs_remove_link(&connector->kobj, "usb-role-switch"); in connector_unbind()
69 * usb_role_switch_set_role - Set USB role for a switch
70 * @sw: USB role switch
100 * usb_role_switch_get_role - Get the USB role for a switch
101 * @sw: USB role switch
103 * Depending on the role-switch-driver this function returns either a cached
145 if (!fwnode_property_present(parent, "usb-role-switch")) { in usb_role_switch_is_parent()
156 * usb_role_switch_get - Find USB role switch linked with the caller
[all …]
/linux/drivers/net/dsa/
H A DKconfig2 menu "Distributed Switch Architecture drivers"
8 tristate "Broadcom Starfighter 2 Ethernet switch support"
17 switch chips.
20 tristate "DSA mock-up Ethernet switch chip support"
24 This enables support for a fake mock-up switch chip which
38 tristate "MediaTek MT7530 and MT7531 Ethernet switch support"
45 switch chips. Multi-chip module MT7530 in MT7621AT, MT7621DAT,
46 MT7621ST and MT7623AI SoCs, and built-in switch in MT7988 SoC are
55 This enables support for the MediaTek MT7530 and MT7531 switch
66 This enables support for the built-in Ethernet switch found
[all …]
/linux/Documentation/devicetree/bindings/net/dsa/
H A Dbrcm,sf2.yaml7 title: Broadcom Starfighter 2 integrated switch
16 - brcm,bcm4908-switch
17 - brcm,bcm7278-switch-v4.0
18 - brcm,bcm7278-switch-v4.8
19 - brcm,bcm7445-switch-v4.0
47 const: switch
52 - description: switch's main clock
53 - description: dividing of the switch core clock
63 description: maximum number of integrated gigabit PHYs in the switch
67 description: maximum number of RGMII interfaces supported by the switch
[all …]
H A Dmarvell,mv88e6xxx.yaml7 title: Marvell MV88E6xxx DSA switch family
13 The Marvell MV88E6xxx switch series has been produced and sold
14 by Marvell since at least 2008. The switch has a few compatibles which
15 just indicate the base address of the switch, then operating systems
16 can investigate switch ID registers to find out which actual version
17 of the switch it is dealing with.
27 marvell,mv88e6085: This switch uses base address 0x10.
28 This switch and its siblings will be autodetected from
29 ID registers found in the switch, so only "marvell,mv88e6085" should be
33 marvell,mv88e6190: This switch uses base address 0x00.
[all …]
/linux/drivers/gpu/drm/omapdrm/dss/
H A Ddispc.h111 switch (channel) { in DISPC_DEFAULT_COLOR()
128 switch (channel) { in DISPC_TRANS_COLOR()
145 switch (channel) { in DISPC_TIMING_H()
163 switch (channel) { in DISPC_TIMING_V()
181 switch (channel) { in DISPC_POL_FREQ()
199 switch (channel) { in DISPC_DIVISORo()
218 switch (channel) { in DISPC_SIZE_MGR()
235 switch (channel) { in DISPC_DATA_CYCLE1()
253 switch (channel) { in DISPC_DATA_CYCLE2()
271 switch (channel) { in DISPC_DATA_CYCLE3()
[all …]
/linux/drivers/video/fbdev/omap2/omapfb/dss/
H A Ddispc.h108 switch (channel) { in DISPC_DEFAULT_COLOR()
125 switch (channel) { in DISPC_TRANS_COLOR()
142 switch (channel) { in DISPC_TIMING_H()
160 switch (channel) { in DISPC_TIMING_V()
178 switch (channel) { in DISPC_POL_FREQ()
196 switch (channel) { in DISPC_DIVISORo()
215 switch (channel) { in DISPC_SIZE_MGR()
232 switch (channel) { in DISPC_DATA_CYCLE1()
250 switch (channel) { in DISPC_DATA_CYCLE2()
268 switch (channel) { in DISPC_DATA_CYCLE3()
[all …]
/linux/Documentation/networking/device_drivers/ethernet/freescale/dpaa2/
H A Dswitch-driver.rst5 DPAA2 Switch driver
10 The DPAA2 Switch driver probes on the Datapath Switch (DPSW) object which can
14 The driver uses the switch device driver model and exposes each switch port as
24 [dpaa2-eth] [dpaa2-eth] [ dpaa2-switch ]
35 Creating an Ethernet Switch
38 The dpaa2-switch driver probes on DPSW devices found on the fsl-mc bus. These
43 At the moment, the dpaa2-switch driver imposes the following restrictions on
46 * The minimum number of FDBs should be at least equal to the number of switch
47 interfaces. This is necessary so that separation of switch ports can be
48 done, ie when not under a bridge, each switch port will have its own FDB.
[all …]
/linux/drivers/soc/fsl/qe/
H A Ducc.c61 switch (ucc_num) { in ucc_set_type()
137 switch (reg_num) { in ucc_set_qe_mux_rxtx()
139 switch (clock) { in ucc_set_qe_mux_rxtx()
154 switch (clock) { in ucc_set_qe_mux_rxtx()
169 switch (clock) { in ucc_set_qe_mux_rxtx()
185 switch (clock) { in ucc_set_qe_mux_rxtx()
226 switch (tdm_num) { in ucc_get_tdm_common_clk()
231 switch (clock) { in ucc_get_tdm_common_clk()
252 switch (clock) { in ucc_get_tdm_common_clk()
280 switch (tdm_num) { in ucc_get_tdm_rx_clk()
[all …]
/linux/include/linux/platform_data/
H A Ddsa.h14 * How to access the switch configuration registers.
24 /* set to size of eeprom if supported by the switch */
27 /* Device tree node pointer for this specific switch chip
28 * used during switch setup in case additional properties
34 * The names of the switch's ports. Use "cpu" to
35 * designate the switch port that the cpu is connected to,
37 * another switch, NULL to indicate the port is unused,
45 * switch should be used to send packets to that are destined
46 * for switch a. Can be NULL if there is only one switch chip.
54 * to the root switch chip of the tree.
[all …]
/linux/arch/mips/include/asm/octeon/
H A Dcvmx-pow.h38 * - Requesting a POW operation with an active tag switch in
40 * - Waiting for a tag switch to complete for an excessively
70 * The work queue entry from the order - NEVER tag switch from
74 /* A tag switch to NULL, and there is no space reserved in POW
75 * - NEVER tag switch to NULL_NULL
76 * - NEVER tag switch from NULL_NULL
79 * load can also switch the state to NULL
97 * switch the tag (only) for this PP
99 * - tag switch response required
104 * switch the tag for this PP, with full information
[all …]

12345678910>>...308