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/linux/tools/testing/selftests/net/
H A Dtest_bridge_backup_port.sh2 # SPDX-License-Identifier: GPL-2.0
11 # +-------
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H A Dtest_bridge_neigh_suppress.sh2 # SPDX-License-Identifier: GPL-2.0
10 # +-------
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/linux/arch/arm64/boot/dts/renesas/
H A Dr9a07g043u11-smarc.dts1 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 * Device Tree Source for the RZ/G2UL Type-1 SMARC EVK board
8 /dts-v1/;
11 * DIP-Switch SW1 setting
13 * SW1-2 : SW_SD0_DEV_SEL (0: uSD; 1: eMMC)
14 * SW1-3 : SW_ET0_EN_N (0: ETHER0; 1: CAN0, CAN1, SSI1, RSPI1)
15 * Please change below macros according to SW1 setting on the SoM
22 * - Set DIP-Switch SW1-3 to On position.
23 * - Set PMOD_MTU3 macro to 1.
32 #include "rzg2ul-smarc-som.dtsi"
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H A Dr9a07g044c2-smarc.dts1 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
8 /dts-v1/;
11 * DIP-Switch SW1 setting on SoM
13 * SW1-2 : SW_SD0_DEV_SEL (1: eMMC; 0: uSD)
14 * SW1-3 : SW_SCIF_CAN (1: CAN1; 0: SCIF1)
15 * SW1-4 : SW_RSPI_CAN (1: CAN1; 0: RSPI1)
16 * SW1-5 : SW_I2S0_I2S1 (1: I2S2 (HDMI audio); 0: I2S0)
17 * Please change below macros according to SW1 setting
40 * - Set DIP-Switch SW1-4 to Off position.
41 * - Set SW_RSPI_CAN macro to 0.
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H A Drzg2l-smarc-som.dtsi1 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/interrupt-controller/irqc-rzg2l.h>
10 #include <dt-bindings/pinctrl/rzg2l-pinctrl.h>
12 /* SW1[2] should be at position 2/OFF to enable 64 GB eMMC */
17 * SW1[2] should be at position 3/ON.
38 reg_1p8v: regulator-1p8v {
39 compatible = "regulator-fixed";
40 regulator-name = "fixed-1.8V";
41 regulator-min-microvolt = <1800000>;
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H A Drzg2lc-smarc-som.dtsi1 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/interrupt-controller/irqc-rzg2l.h>
10 #include <dt-bindings/pinctrl/rzg2l-pinctrl.h>
27 reg_1p8v: regulator-1p8v {
28 compatible = "regulator-fixed";
29 regulator-name = "fixed-1.8V";
30 regulator-min-microvolt = <1800000>;
31 regulator-max-microvolt = <1800000>;
32 regulator-boot-on;
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H A Dr9a09g077m44-rzt2h-evk.dts1 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
8 /dts-v1/;
26 * P17_4 = SD1_CD; SW2[3] = ON
27 * P08_5 = SD1_PWEN; SW2[3] = ON
28 * P08_6 = SD1_IOVS; SW2[3] = ON; SW5[3] = OFF; SW5[4] = ON
35 * This board is equipped with three USB connectors: Type-A (CN80), Mini-B
36 * (CN79), and Micro-AB (CN33). The RZ/T2H SoC has a single USB channel, so
40 * By default, the Type-A (CN80) and Mini-B (CN79) connectors are enabled.
42 * - P00_0 - P00_2 (control signals for USB power supply): SW1[5] = ON
43 * - USB_VBUSIN (used for USB function): SW7[7] = OFF; SW7[8] = ON
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H A Drzg2l-smarc.dtsi1 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/pinctrl/rzg2l-pinctrl.h>
17 osc1: cec-clock {
18 compatible = "fixed-clock";
19 #clock-cells = <0>;
20 clock-frequency = <12000000>;
23 hdmi-out {
24 compatible = "hdmi-connector";
29 remote-endpoint = <&adv7535_out>;
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/linux/arch/riscv/boot/dts/renesas/
H A Dr9a07g043f01-smarc.dts1 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
8 /dts-v1/;
11 * DIP-Switch SW1 setting
13 * SW1-2 : SW_SD0_DEV_SEL (0: uSD; 1: eMMC)
14 * SW1-3 : SW_ET0_EN_N (0: ETHER0; 1: CAN0, CAN1, SSI1, RSPI1)
15 * Please change below macros according to SW1 setting on the SoM
21 #include "rzfive-smarc-som.dtsi"
22 #include "rzfive-smarc.dtsi"
26 compatible = "renesas,smarc-evk", "renesas,r9a07g043f01", "renesas,r9a07g043";
/linux/arch/arm/boot/dts/renesas/
H A Dr9a06g032-rzn1d400-db.dts1 // SPDX-License-Identifier: GPL-2.0
3 * Device Tree Source for the RZN1D-DB Board
9 /dts-v1/;
11 #include <dt-bindings/gpio/gpio.h>
12 #include <dt-bindings/input/input.h>
13 #include <dt-bindings/leds/common.h>
14 #include <dt-bindings/net/pcs-rzn1-miic.h>
15 #include <dt-bindings/pinctrl/rzn1-pinctrl.h>
20 model = "RZN1D-DB Board";
21 compatible = "renesas,rzn1d400-db", "renesas,r9a06g032";
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H A Dr8a7742-iwg21d-q7-dbcm-ca.dts1 // SPDX-License-Identifier: GPL-2.0
3 * Device Tree Source for the iWave-RZ/G1H Qseven board development
9 /dts-v1/;
11 #include <dt-bindings/media/video-interfaces.h>
13 #include "r8a7742-iwg21d-q7.dts"
16 model = "iWave Systems RZ/G1H Qseven development platform with camera add-on";
27 mclk_cam1: mclk-cam1 {
28 compatible = "fixed-clock";
29 #clock-cells = <0>;
30 clock-frequency = <26000000>;
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/linux/arch/mips/kernel/
H A Dbmips_vec.S8 * Reset/NMI/re-entry vectors for BMIPS processors
36 * triggered by the SW1 interrupt. If that is the case we try to move
50 /* re-enable IRQs to wait for SW1 */
58 mfc0 k1, $22, 3
66 /* wait here for SW1 interrupt from bmips_boot_secondary() */
101 li k1, (3 << 25)
178 /* set local CP0 CONFIG to make kseg0 cacheable, write-back */
190 /* initialize CPU1's local I-cache */
201 b 3f
208 bne k0, k1, 3f
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/linux/sound/soc/amd/ps/
H A Dacp63.h1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * AMD Common ACP header file for ACP6.3, ACP7.0 & ACP7.1 platforms
22 #define ACP63_PGFSM_STATUS_MASK 3
26 #define ACP63_POWER_OFF_IN_PROGRESS 3
36 #define ACP_WOV_GAIN_CONTROL GENMASK(4, 3)
94 * 3 (SDW0_AUDIO0_RX) 27
98 #define ACP63_SDW0_DMA_TX_IRQ_MASK(i) (ACP_AUDIO0_TX_THRESHOLD - (2 * (i)))
99 #define ACP63_SDW0_DMA_RX_IRQ_MASK(i) (ACP_AUDIO0_RX_THRESHOLD - (
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/linux/drivers/regulator/
H A Dmc13892-regulator.c1 // SPDX-License-Identifier: GPL-2.0
7 // Based on draft driver from Arnaud Patard <arnaud.patard@rtp-net.org>
23 #define MC13892_POWERCTL0_USEROFFSPI 3
80 #define MC13892_REGULATORSETTING0_VGEN1VSEL_M (3<<0)
81 #define MC13892_REGULATORSETTING0_VDIGVSEL_M (3<<4)
83 #define MC13892_REGULATORSETTING0_VPLLVSEL_M (3<<9)
84 #define MC13892_REGULATORSETTING0_VUSB2VSEL_M (3<<11)
86 #define MC13892_REGULATORSETTING0_VCAMVSEL_M (3<<16)
93 #define MC13892_REGULATORSETTING1_VVIDEOVSEL_M (3<<2)
94 #define MC13892_REGULATORSETTING1_VAUDIOVSEL_M (3<<4)
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H A Dltc3589.c1 // SPDX-License-Identifier: GPL-2.0
3 // Linear Technology LTC3589,LTC3589-1 regulator support
36 #define LTC3589_IRQSTAT_PGOOD_TIMEOUT BIT(3)
45 #define LTC3589_OVEN_BB_OUT BIT(3)
57 #define LTC3589_VRRCR_SW2_RAMP_MASK GENMASK(3, 2)
107 return regmap_update_bits(ltc3589->regmap, rdev->desc->vsel_reg + 1, in ltc3589_set_suspend_voltage()
108 rdev->desc->vsel_mask, sel); in ltc3589_set_suspend_voltage()
118 mask = rdev->desc->apply_bit << 1; in ltc3589_set_suspend_mode()
123 mask |= rdev->desc->apply_bit; in ltc3589_set_suspend_mode()
124 bit |= rdev->desc->apply_bit; in ltc3589_set_suspend_mode()
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H A Dltc3676.c1 // SPDX-License-Identifier: GPL-2.0-only
48 #define LTC3676_IRQSTAT_PGOOD_TIMEOUT BIT(3)
76 struct device *dev = ltc3676->dev; in ltc3676_set_suspend_voltage()
86 return regmap_update_bits(ltc3676->regmap, rdev->desc->vsel_reg + 1, in ltc3676_set_suspend_voltage()
87 rdev->desc->vsel_mask, sel); in ltc3676_set_suspend_voltage()
94 struct device *dev = ltc3676->dev; in ltc3676_set_suspend_mode()
109 dev_warn(&rdev->dev, "%s: regulator mode: 0x%x not supported\n", in ltc3676_set_suspend_mode()
110 rdev->desc->name, mode); in ltc3676_set_suspend_mode()
111 return -EINVAL; in ltc3676_set_suspend_mode()
114 return regmap_update_bits(ltc3676->regmap, rdev->desc->vsel_reg, in ltc3676_set_suspend_mode()
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H A Dpcap-regulator.c1 // SPDX-License-Identifier: GPL-2.0-or-later
15 #include <linux/mfd/ezx-pcap.h>
117 VREG_INFO(V7, PCAP_REG_VREG2, 3, 4, 15, 21),
125 VREG_INFO(VAUX3, PCAP_REG_AUXVREG, 7, 8, 2, 3),
131 VREG_INFO(SW1, PCAP_REG_SWCTRL, 1, 2, NA, NA),
148 if (rdev->desc->n_voltages == 1) in pcap_regulator_set_voltage_sel()
149 return -EINVAL; in pcap_regulator_set_voltage_sel()
151 return ezx_pcap_set_bits(pcap, vreg->reg, in pcap_regulator_set_voltage_sel()
152 (rdev->desc->n_voltages - 1) << vreg->index, in pcap_regulator_set_voltage_sel()
153 selector << vreg->index); in pcap_regulator_set_voltage_sel()
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H A Dcpcap-regulator.c1 // SPDX-License-Identifier: GPL-2.0-only
5 * Based on cpcap-regulator.c from Motorola Linux kernel tree
6 * Copyright (C) 2009-2011 Motorola, Inc.
20 #include <linux/mfd/motorola-cpcap.h>
27 /* CPCAP_REG_ASSIGN2 bits - Resource Assignment 2 */
38 /* CPCAP_REG_ASSIGN3 bits - Resource Assignment 3 */
51 #define CPCAP_BIT_VCSI_SEL BIT(3)
56 /* CPCAP_REG_ASSIGN4 bits - Resource Assignment 4 */
63 * enable register bits. No idea why BIT(3) is not defined.
170 if (rdev->desc->enable_val & CPCAP_REG_OFF_MODE_SEC) { in cpcap_regulator_enable()
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/linux/tools/testing/selftests/net/forwarding/
H A Dipip_lib.sh2 # SPDX-License-Identifier: GPL-2.0
4 # Handles creation and destruction of IP-in-IP or GRE tunnels over the given
9 # SW1 uses default VRF so tunnel has no bound dev.
10 # SW2 uses non-default VRF tunnel has a bound dev.
11 # +-------------------------+
15 # +-------------------|-----+
17 # +-------------------|-----+
18 # | SW1 | |
24 # | rem=192.0.2.66 --. |
26 # | .------------------' |
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H A Dip6gre_lib.sh1 # SPDX-License-Identifier: GPL-2.0
4 # Handles creation and destruction of IP-in-IP or GRE tunnels over the given
9 # SW1 uses default VRF so tunnel has no bound dev.
10 # SW2 uses non-default VRF tunnel has a bound dev.
11 # +--------------------------------+
16 # +-------------------------|------+
18 # +-------------------------|-------------------+
19 # | SW1 | |
25 # | loc=2001:db8:3::1 |
26 # | rem=2001:db8:3::2 --. |
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/linux/arch/arm/boot/dts/qcom/
H A Dqcom-ipq8064-rb3011.dts1 // SPDX-License-Identifier: GPL-2.0
2 #include "qcom-ipq8064.dtsi"
3 #include <dt-bindings/input/input.h>
4 #include <dt-bindings/leds/common.h>
7 model = "MikroTik RB3011UiAS-RM";
14 mdio-gpio0 = &mdio0;
15 mdio-gpio1 = &mdio1;
20 stdout-path = "serial0:115200n8";
23 gpio-keys {
24 compatible = "gpio-keys";
[all …]
/linux/Documentation/devicetree/bindings/mfd/
H A Dmaxim,max5970.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Patrick Rudolph <patrick.rudolph@9elements.com>
24 - maxim,max5970
25 - maxim,max5978
39 "#address-cells":
42 "#size-cells":
46 "^led@[0-3]$":
53 maximum: 3
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/linux/arch/mips/include/asm/sn/
H A Dintr.h6 * Copyright (C) 1992 - 1997 Silicon Graphics, Inc.
41 * Hard-coded interrupt levels:
45 * L0 = SW1
57 * INT_PEND0 hard-coded bits.
66 #define PG_MIG_INTR 3
80 * INT_PEND1 hard-coded bits:
/linux/arch/sh/boards/
H A Dboard-apsh4a3a.c1 // SPDX-License-Identifier: GPL-2.0
3 * ALPHAPROJECT AP-SH4A-3A Support.
54 .end = 0x01000000 - 1,
60 .name = "physmap-flash",
76 .name = "smsc911x-memory",
78 .end = 0xA4000000 + SZ_256 - 1,
82 .name = "smsc911x-irq",
98 .id = -1,
137 printk(KERN_INFO "Alpha Project AP-SH4A-3A support:\n"); in apsh4a3a_setup()
150 /* These are the factory default settings of SW1 and SW2. in apsh4a3a_mode_pins()
[all …]
H A Dboard-apsh4ad0a.c1 // SPDX-License-Identifier: GPL-2.0
3 * ALPHAPROJECT AP-SH4AD-0A Support.
28 .name = "smsc911x-memory",
30 .end = 0xA4000000 + SZ_256 - 1,
34 .name = "smsc911x-irq",
50 .id = -1,
75 /* These are the factory default settings of SW1 and SW2. in apsh4ad0a_mode_pins()
79 value |= MODE_PIN0; /* Clock Mode 3 */ in apsh4ad0a_mode_pins()
83 value &= ~MODE_PIN4; /* 16-bit Area0 bus width */ in apsh4ad0a_mode_pins()
89 value &= ~MODE_PIN10; /* 29-bit address mode */ in apsh4ad0a_mode_pins()
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