Lines Matching +full:sw1 +full:- +full:3
8 * Reset/NMI/re-entry vectors for BMIPS processors
36 * triggered by the SW1 interrupt. If that is the case we try to move
50 /* re-enable IRQs to wait for SW1 */
58 mfc0 k1, $22, 3
66 /* wait here for SW1 interrupt from bmips_boot_secondary() */
101 li k1, (3 << 25)
178 /* set local CP0 CONFIG to make kseg0 cacheable, write-back */
190 /* initialize CPU1's local I-cache */
201 b 3f
208 bne k0, k1, 3f
216 3:
286 addiu t1, t0, -PRID_REV_BMIPS4380_HI
288 addiu t0, -PRID_REV_BMIPS4380_LO
291 mfc0 t0, $22, 3
297 mtc0 t0, $22, 3