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/freebsd/sys/contrib/device-tree/Bindings/pci/
H A Dpci.txt3 PCI Bus Binding to: IEEE Std 1275-1994
4 https://www.devicetree.org/open-firmware/bindings/pci/pci2_1.pdf
9 https://www.devicetree.org/open-firmware/practice/imap/imap0_9d.pdf
14 - linux,pci-domain:
21 - max-link-speed:
27 - reset-gpios:
30 - supports-clkreq:
31 If present this property specifies that CLKREQ signal routing exists from
33 which depends on CLKREQ signal existence. For example, programming root port
34 not to advertise ASPM L1 Sub-States support if there is no CLKREQ signal.
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H A Dnvidia,tegra194-pcie.txt4 and thus inherits all the common properties defined in snps,dw-pcie.yaml and
5 snps,dw-pcie-ep.yaml.
10 - power-domains: A phandle to the node that controls power to the respective
20 "include/dt-bindings/power/tegra194-powergate.h" file.
21 - reg: A list of physical base address and length pairs for each set of
22 controller registers. Must contain an entry for each entry in the reg-names
24 - reg-names: Must include the following entries:
26 "config": As per the definition in snps,dw-pcie.yaml
32 - interrupts: A list of interrupt outputs of the controller. Must contain an
33 entry for each entry in the interrupt-names property.
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H A Dnvidia,tegra194-pcie.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pci/nvidia,tegra194-pcie.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Jon Hunter <jonathanh@nvidia.com>
12 - Vidya Sagar <vidyas@nvidia.com>
16 inherits all the common properties defined in snps,dw-pcie.yaml. Some of
20 See nvidia,tegra194-pcie-ep.yaml for details on the Endpoint mode device
26 - nvidia,tegra194-pcie
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/freebsd/sys/contrib/device-tree/Bindings/pinctrl/
H A Dnuvoton,npcm7xx-pinctrl.txt3 The Nuvoton BMC NPCM7XX Pin Controller multi-function routed through
4 the multiplexing block, Each pin supports GPIO functionality (GPIOx)
9 - #address-cells : should be 1.
10 - #size-cells : should be 1.
11 - compatible : "nuvoton,npcm750-pinctrl" for Poleg NPCM7XX.
12 - ranges : defines mapping ranges between pin controller node (parent)
17 The NPCM7XX has 8 GPIO Banks each GPIO bank supports 32 GPIO.
19 Required GPIO Bank subnode-properties:
20 - reg : specifies physical base address and size of the GPIO
22 - gpio-controller : Marks the device node as a GPIO controller.
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H A Dmarvell,kirkwood-pinctrl.txt3 Please refer to marvell,mvebu-pinctrl.txt in this directory for common binding
7 - compatible: "marvell,88f6180-pinctrl",
8 "marvell,88f6190-pinctrl", "marvell,88f6192-pinctrl",
9 "marvell,88f6281-pinctrl", "marvell,88f6282-pinctrl",
10 "marvell,98dx4122-pinctrl", "marvell,98dx1135-pinctrl"
11 - reg: register specifier of MPP registers
13 This driver supports all kirkwood variants, i.e. 88f6180, 88f619x, and 88f628x.
14 It also support the 88f6281-based variant in the 98dx412x Bobcat SoCs.
37 mpp11 11 gpio, spi(miso), uart0(rxd), ptp(clk), ptp-1(evreq),
38 ptp-2(trig)
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/freebsd/sys/contrib/device-tree/src/arm/marvell/
H A Darmada-388-clearfog.dtsi1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
8 #include "armada-388.dtsi"
9 #include "armada-38x-solidrun-microsom.dtsi"
13 /* So that mvebu u-boot can update the MAC addresses */
20 stdout-path = "serial0:115200n8";
23 reg_3p3v: regulator-3p3v {
24 compatible = "regulator-fixed";
25 regulator-name = "3P3V";
26 regulator-min-microvolt = <3300000>;
27 regulator-max-microvolt = <3300000>;
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/freebsd/sys/contrib/dev/rtw88/
H A Dpci.c1 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
2 /* Copyright(c) 2018-2019 Realtek Corporation
54 return skb->priority; in rtw_pci_get_tx_qsel()
60 struct rtw_pci *rtwpci = (struct rtw_pci *)rtwdev->priv; in rtw_pci_read8()
63 return readb(rtwpci->mmap + addr); in rtw_pci_read8()
67 val = bus_read_1((struct resource *)rtwpci->mma in rtw_pci_read8()
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/freebsd/sys/dev/bhnd/
H A Dbhnd_ids.h1 /*-
2 * SPDX-License-Identifier: ISC
4 * Copyright (c) 2015-2016 Landon Fuller <landon@landonf.org>
5 * Copyright (c) 1999-2015, Broadcom Corporation
9 * with the dd-wrt project, and the hndsoc.h header distributed with Broadcom's
30 * JEDEC JEP-106 Core Vendor IDs
32 * These are the JEDEC JEP-106 manufacturer ID representions (with ARM's
33 * non-standard 4-bit continutation code), as used in ARM's PrimeCell
38 * will need to convert bus-specific vendor IDs to their BHND_MFGID
39 * JEP-106 equivalents.
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/freebsd/sys/contrib/dev/rtw89/
H A Dpci.c1 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
25 MODULE_PARM_DESC(disable_clkreq, "Set Y to disable PCI clkreq support");
32 struct rtw89_pci *rtwpci = (struct rtw89_pci *)rtwdev->priv; in rtw89_pci_rst_bdram_pcie()
33 struct pci_dev *pdev = rtwpci->pdev; in rtw89_pci_rst_bdram_pcie()
48 return -EFAULT; in rtw89_pci_dma_recalc()
72 const struct rtw89_pci_info *info = rtwdev->pci_inf in rtw89_pci_txbd_recalc()
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/freebsd/sys/contrib/device-tree/src/arm64/mediatek/
H A Dmt8192-asurada.dtsi1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
6 /dts-v1/;
9 #include <dt-bindings/gpio/gpio.h>
10 #include <dt-bindings/spmi/spmi.h>
25 stdout-path = "serial0:115200n8";
33 backlight_lcd0: backlight-lcd0 {
34 compatible = "pwm-backlight";
36 power-suppl
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/freebsd/sys/dev/ath/ath_hal/ar5212/
H A Dar5212_attach.c1 /*-
2 * SPDX-License-Identifier: ISC
4 * Copyright (c) 2002-2009 Sam Leffler, Errno Consulting
5 * Copyright (c) 2002-2008 Atheros Communications, Inc.
202 .totalSizeDesired = { -55, -55, -55, -55, -62 }, in ar5212AniSetup()
203 .coarseHigh = { -14, -14, -14, -14, -12 }, in ar5212AniSetup()
204 .coarseLow = { -64, -64, -64, -64, -70 }, in ar5212AniSetup()
205 .firpwr = { -78, -78, -78, -78, -80 }, in ar5212AniSetup()
218 if (AH_PRIVATE(ah)->ah_macVersion < AR_SREV_VERSION_GRIFFIN) { in ar5212AniSetup()
227 AH5212(ah)->ah_aniControl = ar5212AniControl; in ar5212AniSetup()
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/freebsd/sys/contrib/device-tree/src/arm64/nvidia/
H A Dtegra194.dtsi1 // SPDX-License-Identifier: GPL-2.0
2 #include <dt-bindings/clock/tegra194-clock.h>
3 #include <dt-bindings/gpio/tegra194-gpio.h>
4 #include <dt-bindings/interrupt-controller/arm-gi
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/freebsd/sys/contrib/dev/ath/ath_hal/ar9300/
H A Dar9300_attach.c145 p_counters->uc_receiver_errors = MS(val, RCVD_ERR_MASK); in ar9300_read_pcie_error_monitor()
146 p_counters->uc_bad_tlp_errors = MS(val, BAD_TLP_ERR_MASK); in ar9300_read_pcie_error_monitor()
147 p_counters->uc_bad_dllp_errors = MS(val, BAD_DLLP_ERR_MASK); in ar9300_read_pcie_error_monitor()
151 p_counters->uc_replay_timeout_errors = MS(val, RPLY_TO_ERR_MASK); in ar9300_read_pcie_error_monitor()
152 p_counters->uc_replay_number_rollover_errors= MS(val, RPLY_NUM_RO_ERR_MASK); in ar9300_read_pcie_error_monitor()
566 if (AH_PRIVATE(ah)->ah_devid == AR9300_DEVID_AR9340) { in ar9300_read_revisions()
568 AH_PRIVATE(ah)->ah_macVersion = AR_SREV_VERSION_WASP; in ar9300_read_revisions()
569 } else if(AH_PRIVATE(ah)->ah_devid == AR9300_DEVID_QCA955X) { in ar9300_read_revisions()
571 AH_PRIVATE(ah)->ah_macVersion = AR_SREV_VERSION_SCORPION; in ar9300_read_revisions()
572 } else if(AH_PRIVATE(ah)->ah_devid == AR9300_DEVID_QCA953X) { in ar9300_read_revisions()
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/freebsd/sys/dev/rtsx/
H A Drtsx.c1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
12 * - Lutz Bichler <Lutz.Bichler@gmail.com>
73 /* The softc holds our per-instance data. */
136 uint8_t rtsx_cam_status; /* CAM status - 1 if card in use */
143 bool rtsx_vpclk; /* voltage at Pulse-width Modulation(PWM) clock? */
292 #define RTSX_LOCK_INIT(_sc) mtx_init(&(_sc)->rtsx_mtx, \
293 device_get_nameunit(sc->rtsx_dev), "rtsx", MTX_DEF)
294 #define RTSX_LOCK(_sc) mtx_lock(&(_sc)->rtsx_mtx)
295 #define RTSX_UNLOCK(_sc) mtx_unlock(&(_sc)->rtsx_mtx)
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/freebsd/sys/dev/re/
H A Dif_re.c1 /*-
2 * SPDX-License-Identifier: BSD-4-Clause
4 * Copyright (c) 1997, 1998-2003
18 * 4. Neither the name of the author nor the names of any co-contributors
51 * with the older 8139 family, however it also supports a special
59 * o 64-bit DMA
69 * Like the 8139, the 8139C+ also has a built-in 10/100 PHY. The C+
74 * The 8169 is a 64-bit 10/100/1000 gigabit ethernet MAC. It has almost the
93 * have a built-in PHY. Most reference boards use a Marvell 88E1000 'Alaska'
96 * The 8169S/8110S 10/100/1000 devices have built-in copper gigE PHYs
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/freebsd/sys/contrib/device-tree/src/arm64/qcom/
H A Dsc7280.dtsi1 // SPDX-License-Identifier: BSD-3-Clause
5 * Copyright (c) 2020-2021, The Linux Foundation. All rights reserved.
7 #include <dt-bindings/clock/qcom,camcc-sc7280.h>
8 #include <dt-bindings/clock/qcom,dispcc-sc7280.h>
9 #include <dt-binding
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/freebsd/sys/dev/qlnx/qlnxe/
H A Dreg_addr.h2 * Copyright (c) 2017-2018 Cavium, Inc.
78 …- For ending "endless completion". 0 - When receiving a completion timeout while receiving a compl…
79 … DataWidth:0x4 // 0 - TXCPL sync fifo pop underflow 1 - TXR sync fifo pop underflow 2 - TXW hea…
80 …s:R DataWidth:0x6 // 0 - RX target read and config sync fifo push overflow 1 - RX header syn…
81 …ataWidth:0x14 // 4:0 - TXCPL sync fifo pop status 9:5 - TXR sync fifo pop status 14:10 - TXW hea…
88 …ffff<<0) // Vendor ID. PCI-SIG assigned Manufacturer Identifier. Note: The access attributes of …
90 …ce Identifier. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
116 … (0x1<<9) // Fast back-to-back transaction ena…
128 … (0x1<<23) // Fast back-to-back capable. Not ap…
145 …l has_io_bar=0. Note: The access attributes of this field are as follows: - Dbi: if (DBI_RO_WR_E…
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