| /linux/Documentation/ABI/testing/ |
| H A D | sysfs-bus-mei | 6 Description: Stores the same MODALIAS value emitted by uevent
13 Description: Stores mei client device name
20 Description: Stores mei client device uuid
27 Description: Stores mei client protocol version
34 Description: Stores mei client maximum number of connections
41 Description: Stores mei client fixed address, if any
48 Description: Stores mei client vtag support status
55 Description: Stores mei client maximum message length
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| H A D | sysfs-devices-platform-sh_mobile_lcdc_fb | 8 Stores the alpha blending value for the overlay. Values range
32 Stores the x,y overlay position on the display in pixels. The
42 Stores the raster operation (ROP3) for the overlay. Values
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| /linux/tools/memory-model/Documentation/ |
| H A D | control-dependencies.txt | 11 One such challenge is that control dependencies order only later stores.
31 However, stores are not speculated. This means that ordering is
43 the compiler might fuse the store to "b" with other stores. Worse yet,
60 identical stores on both branches of the "if" statement as follows:
104 guaranteed only when the stores differ, for example:
212 only to the stores in the then-clause and else-clause of the "if" statement
219 (*) Control dependencies can order prior loads against later stores.
221 Not prior loads against later loads, nor prior stores against
224 stores and later loads, smp_mb().
226 (*) If both legs of the "if" statement contain identical stores to
[all …]
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| H A D | explanation.txt | 103 device, stores it in a buffer, and sets a flag to indicate the buffer
135 Thus, P0 stores the data in buf and then sets flag. Meanwhile, P1
141 This pattern of memory accesses, where one CPU stores values to two
198 it, as loads can obtain values only from earlier stores.
203 P1 must load 0 from buf before P0 stores 1 to it; otherwise r2
207 P0 stores 1 to buf before storing 1 to flag, since it executes
223 each CPU stores to its own shared location and then loads from the
271 W: P0 stores 1 to flag executes before
274 Z: P0 stores 1 to buf executes before
275 W: P0 stores 1 to flag.
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| /linux/tools/perf/pmu-events/arch/x86/knightslanding/ |
| H A D | uncore-memory.json | 3 …"BriefDescription": "Counts the number of read requests and streaming stores that hit in MCDRAM ca…
12 …"BriefDescription": "Counts the number of read requests and streaming stores that hit in MCDRAM ca…
21 …"BriefDescription": "Counts the number of read requests and streaming stores that miss in MCDRAM c…
30 …"BriefDescription": "Counts the number of read requests and streaming stores that miss in MCDRAM c…
55 …id memory mode, this event counts all read requests as well as streaming stores that hit or miss i…
71 …hybrid. In cache and hybrid memory mode, this event counts all streaming stores, writebacks and, r…
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| /linux/arch/mips/include/asm/octeon/ |
| H A D | octeon.h | 211 * stores; if clear, SYNCWS and SYNCS only order
212 * unmarked stores. SYNCWSMARKED has no effect when
222 * loads/stores can use XKPHYS addresses with
225 /* R/W If set (and UX set), user-level loads/stores
229 * loads/stores can use XKPHYS addresses with
232 /* R/W If set (and UX set), user-level loads/stores
235 /* R/W If set, all stores act as SYNCW (NOMERGE must
238 /* R/W If set, no stores merge, and all stores reach
265 /* R/W If set, CVMSEG is available for loads/stores in
268 /* R/W If set, CVMSEG is available for loads/stores in
[all …]
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| /linux/arch/powerpc/include/asm/ |
| H A D | barrier.h | 19 * providing an ordering (separately) for (a) cacheable stores and (b)
20 * loads and stores to non-cacheable memory (e.g. I/O devices).
22 * mb() prevents loads and stores being reordered across this point.
24 * wmb() prevents stores being reordered across this point.
32 * doesn't order loads with respect to previous stores. Lwsync can be
109 * pmem_wmb() ensures that all stores for which the modification
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| /linux/tools/arch/powerpc/include/asm/ |
| H A D | barrier.h | 15 * providing an ordering (separately) for (a) cacheable stores and (b)
16 * loads and stores to non-cacheable memory (e.g. I/O devices).
18 * mb() prevents loads and stores being reordered across this point.
20 * wmb() prevents stores being reordered across this point.
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| /linux/arch/sparc/kernel/ |
| H A D | dtlb_prot.S | 12 * [TL == 0] 1) User stores to readonly pages.
13 * [TL == 0] 2) Nucleus stores to user readonly pages.
14 * [TL > 0] 3) Nucleus stores to user readonly stack frame.
20 membar #Sync ! Synchronize stores
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| /linux/arch/sparc/lib/ |
| H A D | M7memset.S | 32 * For small 6 or fewer bytes stores, bytes will be stored.
34 * For less than 32 bytes stores, align the address on 4 byte boundary.
41 * Using BIS stores, set the first long word of each
46 * Using BIS stores, set the first long word of each of
66 * similar to prefetching for normal stores.
71 * BIS stores must be followed by a membar #StoreStore. The benefit of
79 * store and the final stores.
167 ! Use long word stores.
179 and %o2, 63, %o3 ! %o3 = bytes left after blk stores.
187 ! initial cache-clearing stores
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| /linux/tools/perf/arch/powerpc/util/ |
| H A D | mem-events.c | 10 E("ldlat-stores", "%s/mem-stores/", "mem-stores", false, 0),
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| /linux/tools/perf/pmu-events/arch/powerpc/power10/ |
| H A D | translation.json | 10 …efDescription": "Stores completed from S2Q (2nd-level store queue). This event includes regular st…
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| /linux/include/uapi/sound/ |
| H A D | snd_sst_tokens.h | 34 * %SKL_TKN_U8_CORE_ID: Stores module affinity value.Can take
65 * %SKL_TKN_U16_PIN_INST_ID: Stores the pin instance id
67 * %SKL_TKN_U16_MOD_INST_ID: Stores the mdule instance id
73 * %SKL_TKN_U32_OBS: Stores Output Buffer size
75 * %SKL_TKN_U32_IBS: Stores input buffer size
84 * %SKL_TKN_U32_PIPE_ID: Stores the pipe id
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| /linux/arch/mips/include/asm/ |
| H A D | sync.h | 33 * loads or stores. By way of example, if we only care that stores older
34 * than a barrier are observed prior to stores that are younger than a
36 * ordering barrier can be used. Limiting the barrier's effects to stores
38 * make progress faster than if younger loads had to wait for older stores
79 * stores, but instead causes synchronization of an icache or TLB global
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| /linux/drivers/net/wwan/iosm/ |
| H A D | iosm_ipc_pm.c | 76 /* Complete all memory stores before setting bit */ in ipc_pm_wait_for_device_active()
84 /* Complete all memory stores after setting bit */ in ipc_pm_wait_for_device_active()
99 /* Complete all memory stores before clearing bit */ in ipc_pm_wait_for_device_active()
107 /* Complete all memory stores after clearing bit */ in ipc_pm_wait_for_device_active()
319 /* Complete all memory stores before clearing bit */ in ipc_pm_init()
324 /* Complete all memory stores after clearing bit */ in ipc_pm_init()
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| /linux/fs/romfs/ |
| H A D | Kconfig | 20 # Select the backing stores to be supported
23 prompt "RomFS backing stores"
27 Select the backing stores to be supported.
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| /linux/tools/perf/pmu-events/arch/x86/icelakex/ |
| H A D | virtual-memory.json | 67 "BriefDescription": "Stores that miss the DTLB and hit the STLB.",
71 …"PublicDescription": "Counts stores that miss the DTLB (Data TLB) and hit the STLB (2nd Level TLB)…
90 …n": "Counts completed page walks (all page sizes) caused by demand data stores. This implies it m…
99 …"PublicDescription": "Counts completed page walks (1G sizes) caused by demand data stores. This i…
108 …tion": "Counts completed page walks (2M/4M sizes) caused by demand data stores. This implies addr…
117 …"PublicDescription": "Counts completed page walks (4K sizes) caused by demand data stores. This i…
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| /linux/tools/perf/pmu-events/arch/x86/skylake/ |
| H A D | virtual-memory.json | 80 …"PublicDescription": "Counts demand data stores that caused a page walk of any page size (4K/2M/4M…
85 "BriefDescription": "Stores that miss the DTLB and hit the STLB.",
89 … "PublicDescription": "Stores that miss the DTLB (Data TLB) and hit the STLB (2nd Level TLB).",
108 …n": "Counts completed page walks (all page sizes) caused by demand data stores. This implies it m…
117 …"PublicDescription": "Counts completed page walks (1G sizes) caused by demand data stores. This i…
126 …tion": "Counts completed page walks (2M/4M sizes) caused by demand data stores. This implies addr…
135 …"PublicDescription": "Counts completed page walks (4K sizes) caused by demand data stores. This i…
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| /linux/tools/perf/pmu-events/arch/x86/skylakex/ |
| H A D | virtual-memory.json | 80 …"PublicDescription": "Counts demand data stores that caused a page walk of any page size (4K/2M/4M…
85 "BriefDescription": "Stores that miss the DTLB and hit the STLB.",
89 … "PublicDescription": "Stores that miss the DTLB (Data TLB) and hit the STLB (2nd Level TLB).",
108 …n": "Counts completed page walks (all page sizes) caused by demand data stores. This implies it m…
117 …"PublicDescription": "Counts completed page walks (1G sizes) caused by demand data stores. This i…
126 …tion": "Counts completed page walks (2M/4M sizes) caused by demand data stores. This implies addr…
135 …"PublicDescription": "Counts completed page walks (4K sizes) caused by demand data stores. This i…
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| /linux/tools/perf/pmu-events/arch/x86/cascadelakex/ |
| H A D | virtual-memory.json | 80 …"PublicDescription": "Counts demand data stores that caused a page walk of any page size (4K/2M/4M…
85 "BriefDescription": "Stores that miss the DTLB and hit the STLB.",
89 … "PublicDescription": "Stores that miss the DTLB (Data TLB) and hit the STLB (2nd Level TLB).",
108 …n": "Counts completed page walks (all page sizes) caused by demand data stores. This implies it m…
117 …"PublicDescription": "Counts completed page walks (1G sizes) caused by demand data stores. This i…
126 …tion": "Counts completed page walks (2M/4M sizes) caused by demand data stores. This implies addr…
135 …"PublicDescription": "Counts completed page walks (4K sizes) caused by demand data stores. This i…
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| /linux/tools/perf/pmu-events/arch/x86/amdzen1/ |
| H A D | memory.json | 11 …n": "Counts the number of operations dispatched to the LS unit. Unit Masks ADDed. Load-op-Stores.",
17 "BriefDescription": "Counts the number of stores dispatched to the LS unit. Unit Masks ADDed.",
43 "EventName": "ls_mab_alloc.stores",
45 "BriefDescription": "LS MAB allocates by type - stores.",
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| /linux/tools/perf/pmu-events/arch/x86/amdzen2/ |
| H A D | memory.json | 6 …stores when accessing the same data. Vector/SIMD code is particularly susceptible to this problem;…
52 …"BriefDescription": "Number of stores dispatched. Counts the number of operations dispatched to th…
99 "EventName": "ls_mab_alloc.stores",
101 "BriefDescription": "LS MAB Allocates by Type. Stores.",
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| /linux/tools/perf/pmu-events/arch/x86/grandridge/ |
| H A D | virtual-memory.json | 46 …Counts the number of first level TLB misses but second level hits due to stores that did not start…
66 …"PublicDescription": "Counts the number of page walks completed due to stores whose address transl…
75 …"PublicDescription": "Counts the number of page walks completed due to stores whose address transl…
80 …ounts the number of page walks outstanding in the page miss handler (PMH) for stores every cycle.",
84 … the number of page walks outstanding in the page miss handler (PMH) for stores every cycle. A PMH…
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| /linux/tools/perf/pmu-events/arch/x86/sierraforest/ |
| H A D | virtual-memory.json | 46 …Counts the number of first level TLB misses but second level hits due to stores that did not start…
66 …"PublicDescription": "Counts the number of page walks completed due to stores whose address transl…
75 …"PublicDescription": "Counts the number of page walks completed due to stores whose address transl…
80 …ounts the number of page walks outstanding in the page miss handler (PMH) for stores every cycle.",
84 … the number of page walks outstanding in the page miss handler (PMH) for stores every cycle. A PMH…
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| /linux/tools/perf/pmu-events/arch/x86/rocketlake/ |
| H A D | virtual-memory.json | 67 "BriefDescription": "Stores that miss the DTLB and hit the STLB.",
71 "PublicDescription": "Counts stores that miss the DTLB (Data TLB) and hit the STLB (2nd Level TLB).",
90 "PublicDescription": "Counts completed page walks (all page sizes) caused by demand data stores. This implies it missed in the DTLB and further levels of TLB. The page walk can end with or without a fault.",
99 "PublicDescription": "Counts completed page walks (1G sizes) caused by demand data stores. This implies address translations missed in the DTLB and further levels of TLB. The page walk can end with or without a fault.",
108 "PublicDescription": "Counts completed page walks (2M/4M sizes) caused by demand data stores. This implies address translations missed in the DTLB and further levels of TLB. The page walk can end with or without a fault.",
117 "PublicDescription": "Counts completed page walks (4K sizes) caused by demand data stores. This implies address translations missed in the DTLB and further levels of TLB. The page walk can end with or without a fault.",
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