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Searched +full:stmmac +full:- +full:axi +full:- +full:config (Results 1 – 25 of 31) sorted by relevance

12

/linux/arch/arm64/boot/dts/intel/
H A Dsocfpga_agilex5.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
6 /dts-v1/;
7 #include <dt-bindings/reset/altr,rst-mgr-s10.h>
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 #include <dt-bindings/interrupt-controller/irq.h>
11 #include <dt-bindings/clock/intel,agilex5-clkmgr.h>
14 compatible = "intel,socfpga-agilex5";
15 #address-cells = <2>;
16 #size-cells = <2>;
[all …]
/linux/Documentation/devicetree/bindings/net/
H A Dsophgo,cv1800b-dwmac.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/net/sophgo,cv1800b-dwmac.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Inochi Amaoto <inochiama@gmail.com>
17 - sophgo,cv1800b-dwmac
19 - compatible
24 - const: sophgo,cv1800b-dwmac
25 - const: snps,dwmac-3.70a
32 - description: GMAC main clock
[all …]
H A Dintel,dwmac-plat.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/net/intel,dwmac-plat.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Vineetha G. Jaya Kumaran <vineetha.g.jaya.kumaran@intel.com>
17 - intel,keembay-dwmac
19 - compatible
22 - $ref: snps,dwmac.yaml#
27 - items:
28 - enum:
[all …]
H A Dstarfive,jh7110-dwmac.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/net/starfive,jh7110-dwmac.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - Emil Renner Berthing <kernel@esmil.dk>
12 - Samin Guo <samin.guo@starfivetech.com>
19 - starfive,jh7100-dwmac
20 - starfive,jh7110-dwmac
22 - compatible
27 - items:
[all …]
H A Dstm32-dwmac.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/net/stm32-dwmac.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - Alexandre Torgue <alexandre.torgue@foss.st.com>
12 - Christophe Roullier <christophe.roullier@foss.st.com>
15 This file documents platform glue layer for stmmac.
23 - st,stm32-dwmac
24 - st,stm32mp1-dwmac
25 - st,stm32mp13-dwmac
[all …]
/linux/arch/arm64/boot/dts/st/
H A Dstm32mp253.dtsi1 // SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-3-Clause)
3 * Copyright (C) STMicroelectronics 2023 - All Rights Reserved
11 compatible = "arm,cortex-a35";
14 enable-method = "psci";
15 power-domains = <&CPU_PD1>;
16 power-domain-names = "psci";
20 arm-pmu {
23 interrupt-affinity = <&cpu0>, <&cpu1>;
27 CPU_PD1: power-domain-cpu1 {
28 #power-domain-cells = <0>;
[all …]
H A Dstm32mp233.dtsi1 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause)
3 * Copyright (C) STMicroelectronics 2025 - All Rights Reserved
11 compatible = "arm,cortex-a35";
14 enable-method = "psci";
15 power-domains = <&cpu1_pd>;
16 power-domain-names = "psci";
20 arm-pmu {
23 interrupt-affinity = <&cpu0>, <&cpu1>;
27 cpu1_pd: power-domain-cpu1 {
28 #power-domain-cells = <0>;
[all …]
/linux/arch/arm/boot/dts/axis/
H A Dartpec6.dtsi2 * Device Tree Source for the Axis ARTPEC-6 SoC
4 * This file is dual-licensed: you can use it either under the terms
43 #include <dt-bindings/interrupt-controller/arm-gic.h>
44 #include <dt-bindings/dma/nbpfaxi.h>
45 #include <dt-bindings/clock/axis,artpec6-clkctrl.h>
48 #address-cells = <1>;
49 #size-cells = <1>;
51 interrupt-parent = <&intc>;
54 #address-cells = <1>;
55 #size-cells = <0>;
[all …]
/linux/arch/riscv/boot/dts/sophgo/
H A Dcv180x.dtsi1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
7 #include <dt-bindings/clock/sophgo,cv1800.h>
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/interrupt-controller/irq.h>
10 #include "cv18xx-reset.h"
13 #address-cells = <1>;
14 #size-cells = <1>;
17 compatible = "fixed-clock";
18 clock-output-names = "osc_25m";
19 #clock-cells = <0>;
[all …]
H A Dsg2044.dtsi1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
6 #include <dt-bindings/clock/sophgo,sg2044-pll.h>
7 #include <dt-bindings/clock/sophgo,sg2044-clk.h>
8 #include <dt-bindings/interrupt-controller/irq.h>
9 #include <dt-bindings/gpio/gpio.h>
10 #include <dt-bindings/pinctrl/pinctrl-sg2044.h>
12 #include "sg2044-cpus.dtsi"
13 #include "sg2044-reset.h"
24 compatible = "fixed-clock";
25 clock-output-names = "osc";
[all …]
H A Dsg2042.dtsi1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
6 /dts-v1/;
7 #include <dt-bindings/clock/sophgo,sg2042-clkgen.h>
8 #include <dt-bindings/clock/sophgo,sg2042-pll.h>
9 #include <dt-bindings/clock/sophgo,sg2042-rpgate.h>
10 #include <dt-bindings/interrupt-controller/irq.h>
11 #include <dt-bindings/pinctrl/pinctrl-sg2042.h>
12 #include <dt-bindings/reset/sophgo,sg2042-reset.h>
14 #include "sg2042-cpus.dtsi"
18 #address-cells = <2>;
[all …]
/linux/arch/arm64/boot/dts/rockchip/
H A Drk3568.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 #include "rk356x-base.dtsi"
11 cpu0_opp_table: opp-table-0 {
12 compatible = "operating-points-v2";
13 opp-shared;
15 opp-408000000 {
16 opp-hz = /bits/ 64 <408000000>;
17 opp-microvolt = <850000 850000 1150000>;
18 clock-latency-ns = <40000>;
21 opp-600000000 {
[all …]
H A Drk3528.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
7 #include <dt-bindings/gpio/gpio.h>
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
9 #include <dt-bindings/interrupt-controller/irq.h>
10 #include <dt-bindings/phy/phy.h>
11 #include <dt-bindings/pinctrl/rockchip.h>
12 #include <dt-bindings/clock/rockchip,rk3528-cru.h>
13 #include <dt-bindings/power/rockchip,rk3528-power.h>
14 #include <dt-bindings/reset/rockchip,rk3528-cru.h>
19 interrupt-parent = <&gic>;
[all …]
H A Drk3576.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 #include <dt-bindings/clock/rockchip,rk3576-cru.h>
7 #include <dt-bindings/interrupt-controller/arm-gic.h>
8 #include <dt-bindings/interrupt-controller/irq.h>
9 #include <dt-bindings/phy/phy.h>
10 #include <dt-bindings/pinctrl/rockchip.h>
11 #include <dt-bindings/power/rockchip,rk3576-power.h>
12 #include <dt-bindings/reset/rockchip,rk3576-cru.h>
13 #include <dt-bindings/soc/rockchip,boot-mode.h>
14 #include <dt-bindings/thermal/thermal.h>
[all …]
H A Drk356x-base.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 #include <dt-bindings/clock/rk3568-cru.h>
7 #include <dt-bindings/interrupt-controller/arm-gic.h>
8 #include <dt-bindings/interrupt-controller/irq.h>
9 #include <dt-bindings/phy/phy.h>
10 #include <dt-bindings/pinctrl/rockchip.h>
11 #include <dt-bindings/power/rk3568-power.h>
12 #include <dt-bindings/soc/rockchip,boot-mode.h>
13 #include <dt-bindings/thermal/thermal.h>
16 interrupt-parent = <&gic>;
[all …]
/linux/arch/arm/boot/dts/intel/socfpga/
H A Dsocfpga.dtsi1 // SPDX-License-Identifier: GPL-2.0+
6 #include <dt-bindings/reset/altr,rst-mgr.h>
9 #address-cells = <1>;
10 #size-cells = <1>;
22 #address-cells = <1>;
23 #size-cells = <0>;
24 enable-method = "altr,socfpga-smp";
27 compatible = "arm,cortex-a9";
30 next-level-cache = <&L2>;
33 compatible = "arm,cortex-a9";
[all …]
/linux/arch/arm64/boot/dts/renesas/
H A Dr9a09g087.dtsi1 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
8 #include <dt-bindings/clock/renesas,r9a09g087-cpg-mssr.h>
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
13 #address-cells = <2>;
14 #size-cells = <2>;
15 interrupt-parent = <&gic>;
18 #address-cells = <1>;
19 #size-cells = <0>;
22 compatible = "arm,cortex-a55";
25 next-level-cache = <&L3_CA55>;
[all …]
H A Dr9a09g077.dtsi1 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
8 #include <dt-bindings/clock/renesas,r9a09g077-cpg-mssr.h>
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
13 #address-cells = <2>;
14 #size-cells = <2>;
15 interrupt-parent = <&gic>;
18 #address-cells = <1>;
19 #size-cells = <0>;
22 compatible = "arm,cortex-a55";
25 next-level-cache = <&L3_CA55>;
[all …]
H A Dr9a09g056.dtsi1 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
8 #include <dt-bindings/clock/renesas,r9a09g056-cpg.h>
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 #include <dt-bindings/pinctrl/rzg2l-pinctrl.h>
12 /* RZV2N_Px = Offset address of PFC_P_mn - 0x20 */
31 #address-cells = <2>;
32 #size-cells = <2>;
33 interrupt-parent = <&gic>;
35 audio_extal_clk: audio-clk {
36 compatible = "fixed-clock";
[all …]
H A Dr9a09g047.dtsi1 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
8 #include <dt-bindings/clock/renesas,r9a09g047-cpg.h>
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
13 #address-cells = <2>;
14 #size-cells = <2>;
15 interrupt-parent = <&gic>;
17 audio_extal_clk: audio-clk {
18 compatible = "fixed-clock";
19 #clock-cells = <0>;
21 clock-frequency = <0>;
[all …]
H A Dr9a09g057.dtsi1 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
8 #include <dt-bindings/clock/renesas,r9a09g057-cpg.h>
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
13 #address-cells = <2>;
14 #size-cells = <2>;
15 interrupt-parent = <&gic>;
17 audio_extal_clk: audio-clk {
18 compatible = "fixed-clock";
19 #clock-cells = <0>;
21 clock-frequency = <0>;
[all …]
/linux/arch/arm/boot/dts/rockchip/
H A Drv1126.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 #include <dt-bindings/clock/rockchip,rv1126-cru.h>
7 #include <dt-bindings/gpio/gpio.h>
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
9 #include <dt-bindings/interrupt-controller/irq.h>
10 #include <dt-bindings/pinctrl/rockchip.h>
11 #include <dt-bindings/power/rockchip,rv1126-power.h>
12 #include <dt-bindings/soc/rockchip,boot-mode.h>
15 #address-cells = <1>;
16 #size-cells = <1>;
[all …]
/linux/arch/riscv/boot/dts/thead/
H A Dth1520.dtsi1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
7 #include <dt-bindings/interrupt-controller/irq.h>
8 #include <dt-bindings/clock/thead,th1520-clk-ap.h>
9 #include <dt-bindings/power/thead,th1520-power.h>
10 #include <dt-bindings/reset/thead,th1520-reset.h>
14 #address-cells = <2>;
15 #size-cells = <2>;
18 #address-cells = <1>;
19 #size-cells = <0>;
20 timebase-frequency = <3000000>;
[all …]
/linux/arch/arm64/boot/dts/mediatek/
H A Dmt2712e.dtsi5 * SPDX-License-Identifier: (GPL-2.0 OR MIT)
8 #include <dt-bindings/clock/mt2712-clk.h>
9 #include <dt-bindings/interrupt-controller/irq.h>
10 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 #include <dt-bindings/memory/mt2712-larb-port.h>
12 #include <dt-bindings/phy/phy.h>
13 #include <dt-bindings/power/mt2712-power.h>
14 #include "mt2712-pinfunc.h"
18 interrupt-parent = <&sysirq>;
19 #address-cells = <2>;
[all …]
/linux/arch/arm64/boot/dts/allwinner/
H A Dsun55i-a523.dtsi1 // SPDX-License-Identifier: (GPL-2.0-only OR MIT)
2 // Copyright (C) 2023-2024 Arm Ltd.
4 #include <dt-bindings/interrupt-controller/arm-gic.h>
5 #include <dt-bindings/clock/sun6i-rtc.h>
6 #include <dt-bindings/clock/sun55i-a523-ccu.h>
7 #include <dt-bindings/clock/sun55i-a523-mcu-ccu.h>
8 #include <dt-bindings/clock/sun55i-a523-r-ccu.h>
9 #include <dt-bindings/reset/sun55i-a523-ccu.h>
10 #include <dt-bindings/reset/sun55i-a523-mcu-ccu.h>
11 #include <dt-bindings/reset/sun55i-a523-r-ccu.h>
[all …]

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