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/linux/arch/arm/boot/dts/st/
H A Dstm32f429.dtsi2 * Copyright 2015 - Maxime Coquelin <mcoquelin.stm32@gmail.com>
4 * This file is dual-licensed: you can use it either under the terms
22 * MA 02110-1301 USA
48 #include "../armv7-m.dtsi"
49 #include <dt-bindings/clock/stm32fx-clock.h>
50 #include <dt-bindings/mfd/stm32f4-rcc.h>
53 #address-cells = <1>;
54 #size-cells = <1>;
57 clk_hse: clk-hse {
58 #clock-cells = <0>;
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H A Dstm32f746.dtsi2 * Copyright 2015 - Maxime Coquelin <mcoquelin.stm32@gmail.com>
4 * This file is dual-licensed: you can use it either under the terms
43 #include "../armv7-m.dtsi"
44 #include <dt-bindings/clock/stm32fx-clock.h>
45 #include <dt-bindings/mfd/stm32f7-rcc.h>
48 #address-cells = <1>;
49 #size-cells = <1>;
52 clk_hse: clk-hse {
53 #clock-cells = <0>;
54 compatible = "fixed-clock";
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H A Dstm32mp131.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
3 * Copyright (C) STMicroelectronics 2021 - All Rights Reserved
6 #include <dt-bindings/interrupt-controller/arm-gic.h>
7 #include <dt-bindings/clock/stm32mp13-clks.h>
8 #include <dt-bindings/reset/stm32mp13-resets.h>
11 #address-cells = <1>;
12 #size-cells = <1>;
15 #address-cells = <1>;
16 #size-cells = <0>;
19 compatible = "arm,cortex-a7";
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H A Dstm32mp151.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
3 * Copyright (C) STMicroelectronics 2017 - All Rights Reserved
6 #include <dt-bindings/interrupt-controller/arm-gic.h>
7 #include <dt-bindings/clock/stm32mp1-clks.h>
8 #include <dt-bindings/reset/stm32mp1-resets.h>
11 #address-cells = <1>;
12 #size-cells = <1>;
15 #address-cells = <1>;
16 #size-cells = <0>;
19 compatible = "arm,cortex-a7";
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/linux/Documentation/devicetree/bindings/mfd/
H A Dst,stm32-timers.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/mfd/st,stm32-timers.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: STMicroelectronics STM32 Timers
11 - advanced-control timers consist of a 16-bit auto-reload counter driven
14 - general-purpose timers consist of a 16-bit or 32-bit auto-reload counter
16 - basic timers consist of a 16-bit auto-reload counter driven by a
20 - Fabrice Gasnier <fabrice.gasnier@foss.st.com>
24 const: st,stm32-timers
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H A Dst,stm32-lptimer.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/mfd/st,stm32-lptimer.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: STMicroelectronics STM32 Low-Power Timers
10 The STM32 Low-Power Timer (LPTIM) is a 16-bit timer that provides several
12 - PWM output (with programmable prescaler, configurable polarity)
13 - Trigger source for STM32 ADC/DAC (LPTIM_OUT)
14 - Several counter modes:
15 - quadrature encoder to detect angular position and direction of rotary
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/linux/drivers/mfd/
H A Dstm32-timers.c1 // SPDX-License-Identifier: GPL-2.0
8 #include <linux/mfd/stm32-timers.h>
33 status = dmaengine_tx_status(dma->chan, dma->chan->cookie, &state); in stm32_timers_dma_done()
35 complete(&dma->completion); in stm32_timers_dma_done()
39 * stm32_timers_dma_burst_read - Read from timers registers using DMA.
41 * Read from STM32 timers registers using DMA on a single event.
57 struct regmap *regmap = ddata->regmap; in stm32_timers_dma_burst_read()
58 struct stm32_timers_dma *dma = &ddata->dma; in stm32_timers_dma_burst_read()
70 return -EINVAL; in stm32_timers_dma_burst_read()
74 return -EINVAL; in stm32_timers_dma_burst_read()
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H A Dstm32-lptimer.c1 // SPDX-License-Identifier: GPL-2.0
3 * STM32 Low-Power Timer parent driver.
6 * Inspired by Benjamin Gaignard's stm32-timers driver
9 #include <linux/mfd/stm32-lptimer.h>
31 * Low-Power Timer supports it. in stm32_lptimer_detect_encoder()
33 ret = regmap_update_bits(ddata->regmap, STM32_LPTIM_CFGR, in stm32_lptimer_detect_encoder()
38 ret = regmap_read(ddata->regmap, STM32_LPTIM_CFGR, &val); in stm32_lptimer_detect_encoder()
42 ret = regmap_update_bits(ddata->regmap, STM32_LPTIM_CFGR, in stm32_lptimer_detect_encoder()
47 ddata->has_encoder = !!(val & STM32_LPTIM_ENC); in stm32_lptimer_detect_encoder()
54 struct device *dev = &pdev->dev; in stm32_lptimer_probe()
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H A DMakefile1 # SPDX-License-Identifier: GPL-2.0
6 88pm860x-objs := 88pm860x-core.o 88pm860x-i2c.o
7 obj-$(CONFIG_MFD_88PM860X) += 88pm860x.o
8 obj-$(CONFIG_MFD_88PM800) += 88pm800.o 88pm80x.o
9 obj-$(CONFIG_MFD_88PM805) += 88pm805.o 88pm80x.o
10 obj-$(CONFIG_MFD_88PM886_PMIC) += 88pm886.o
11 obj-$(CONFIG_MFD_ACT8945A) += act8945a.o
12 obj-$(CONFIG_MFD_SM501) += sm501.o
13 obj-$(CONFIG_ARCH_BCM2835) += bcm2835-pm.o
14 obj-$(CONFIG_MFD_BCM590XX) += bcm590xx.o
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H A DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
57 tristate "Active-semi ACT8945A"
62 Support for the ACT8945A PMIC from Active-semi. This device
63 features three step-down DC/DC converters and four low-dropout
79 sun4i-gpadc-iio and the hwmon driver iio_hwmon.
82 called sun4i-gpadc.
113 tablets etc. It has 4 DC/DC step-down regulators, 3 DC/DC step-down
144 over at91-usart-serial driver and usart-spi-driver. Only one function
160 tristate "Atmel HLCDC (High-end LCD Controller)"
197 tristate "X-Powers AC100"
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/linux/drivers/iio/trigger/
H A DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
7 menu "Triggers - standalone"
14 timers as interrupt source.
17 module will be called iio-trig-hrtimer.
26 module will be called iio-trig-interrupt.
29 tristate "STM32 Low-Power Timer Trigger"
32 Select this option to enable STM32 Low-Power Timer Trigger.
33 This can be used as trigger source for STM32 internal ADC
37 module will be called stm32-lptimer-trigger.
40 tristate "STM32 Timer Trigger"
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H A Dstm32-timer-trigger.c1 // SPDX-License-Identifier: GPL-2.0
11 #include <linux/iio/timer/stm32-timer-trigger.h>
13 #include <linux/mfd/stm32-timers.h>
126 div = (unsigned long long)clk_get_rate(priv->clk); in stm32_timer_start()
136 while (div > priv->max_arr) { in stm32_timer_start()
144 dev_err(priv->dev, "prescaler exceeds the maximum value\n"); in stm32_timer_start()
145 return -EINVAL; in stm32_timer_start()
149 regmap_read(priv->regmap, TIM_CCER, &ccer); in stm32_timer_start()
151 return -EBUSY; in stm32_timer_start()
153 mutex_lock(&priv->lock); in stm32_timer_start()
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/linux/Documentation/devicetree/bindings/timer/
H A Dst,stm32-timer.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/timer/st,stm32-timer.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: STMicroelectronics STM32 general-purpose 16 and 32 bits timers
10 - Fabrice Gasnier <fabrice.gasnier@foss.st.com>
11 - Patrice Chotard <patrice.chotard@foss.st.com>
15 const: st,stm32-timer
30 - compatible
31 - reg
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/linux/drivers/clocksource/
H A Dtimer-stm32.c1 // SPDX-License-Identifier: GPL-2.0-only
4 * Author: Maxime Coquelin <mcoquelin.stm32@gmail.com>
6 * Inspired by time-efm32.c from Uwe Kleine-Koenig
23 #include "timer-of.h"
54 * stm32_timer_of_bits_set - set accessor helper
58 * Accessor helper to set the number of bits in the timer-of private
64 struct stm32_timer_private *pd = to->private_data; in stm32_timer_of_bits_set()
66 pd->bits = bits; in stm32_timer_of_bits_set()
70 * stm32_timer_of_bits_get - get accessor helper
73 * Accessor helper to get the number of bits in the timer-of private
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H A DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
60 bool "OMAP dual-mode timer driver" if ARCH_K3 || COMPILE_TEST
64 Enables the support for the TI dual-mode timer driver.
141 This driver adds support for the timers found in the Realtek RTL83xx
175 Enables support for the timers and watchdogs found on NVIDIA
190 Enable 24-bit TIMER0 and TIMER1 counters in the NPCM7xx architecture,
213 32-bit free running decrementing counters.
248 bool "Integrator-AP timer driver" if COMPILE_TEST
251 Enables support for the Integrator-AP timer.
276 available on many OMAP-like platforms.
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/linux/include/linux/mfd/
H A Dstm32-lptimer.h1 /* SPDX-License-Identifier: GPL-2.0 */
3 * STM32 Low-Power Timer parent driver.
6 * Inspired by Benjamin Gaignard's stm32-timers driver
24 /* STM32_LPTIM_ISR - bit fields */
29 /* STM32_LPTIM_ICR - bit fields */
33 /* STM32_LPTIM_IER - bit flieds */
36 /* STM32_LPTIM_CR - bit fields */
41 /* STM32_LPTIM_CFGR - bit fields */
57 * struct stm32_lptimer - STM32 Low-Power Timer data assigned by parent device
60 * @has_encoder: indicates this Low-Power Timer supports encoder mode
/linux/Documentation/arch/arm/stm32/
H A Dstm32f769-overview.rst6 ------------
8 The STM32F769 is a Cortex-M7 MCU aimed at various applications.
11 - Cortex-M7 core running up to @216MHz
12 - 2MB internal flash, 512KBytes internal RAM (+4KB of backup SRAM)
13 - FMC controller to connect SDRAM, NOR and NAND memories
14 - Dual mode QSPI
15 - SD/MMC/SDIO support*2
16 - Ethernet controller
17 - USB OTFG FS & HS controllers
18 - I2C*4, SPI*6, CAN*3 busses support
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H A Dstm32mp13-overview.rst6 ------------
8 The STM32MP131/STM32MP133/STM32MP135 are Cortex-A MPU aimed at various applications.
11 - One Cortex-A7 application core
12 - Standard memories interface support
13 - Standard connectivity, widely inherited from the STM32 MCU family
14 - Comprehensive security support
18 - Cortex-A7 core running up to @900MHz
19 - FMC controller to connect SDRAM, NOR and NAND memories
20 - QSPI
21 - SD/MMC/SDIO support
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H A Dstm32mp151-overview.rst6 ------------
8 The STM32MP151 is a Cortex-A MPU aimed at various applications.
11 - Single Cortex-A7 application core
12 - Standard memories interface support
13 - Standard connectivity, widely inherited from the STM32 MCU family
14 - Comprehensive security support
18 - Cortex-A7 core running up to @800MHz
19 - FMC controller to connect SDRAM, NOR and NAND memories
20 - QSPI
21 - SD/MMC/SDIO support
[all …]
H A Dstm32f746-overview.rst6 ------------
8 The STM32F746 is a Cortex-M7 MCU aimed at various applications.
11 - Cortex-M7 core running up to @216MHz
12 - 1MB internal flash, 320KBytes internal RAM (+4KB of backup SRAM)
13 - FMC controller to connect SDRAM, NOR and NAND memories
14 - Dual mode QSPI
15 - SD/MMC/SDIO support
16 - Ethernet controller
17 - USB OTFG FS & HS controllers
18 - I2C, SPI, CAN busses support
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/linux/Documentation/ABI/testing/
H A Dsysfs-bus-iio-adc-stm325 The STM32 ADC can be configured to use external trigger sources
6 (e.g. timers, pwm or exti gpio). Then, it can be tuned to start
9 - "rising-edge"
10 - "falling-edge"
11 - "both-edges".
/linux/drivers/pwm/
H A DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
3 bool "Pulse-Width Modulation (PWM) Support"
5 Generic Pulse-Width Modulation (PWM) support.
7 In Pulse-Width Modulation, a variation of the width of pulses
48 will be called pwm-ab8500.
67 will be called pwm-apple.
77 will be called pwm-atmel.
85 (Atmel High-end LCD Controller). This PWM output is mainly used
89 will be called pwm-atmel-hlcdc.
102 will be called pwm-atmel-tcb.
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H A Dpwm-stm32.c1 // SPDX-License-Identifier: GPL-2.0
7 * Inspired by timer-stm32.c from Maxime Coquelin
8 * pwm-atmel.c from Bo Shen
12 #include <linux/mfd/stm32-timers.h>
49 regmap_read(dev->regmap, TIM_CCER, &ccer); in active_channels()
82 * 0: IC1/3 snapchot on rising edge: counter value -> CCR1/CCR3
84 * 1: IC2/4 snapchot on falling edge: counter value -> CCR2/CCR4
85 * 2: IC1/3 snapchot on rising edge: counter value -> CCR1/CCR3
89 * - Period = t2 - t0
90 * - Duty cycle = t1 - t0
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/linux/drivers/counter/
H A Dstm32-timer-cnt.c1 // SPDX-License-Identifier: GPL-2.0
3 * STM32 Timer Encoder and Counter driver
12 #include <linux/mfd/stm32-timers.h>
65 regmap_read(priv->regmap, TIM_CNT, &cnt); in stm32_count_read()
77 regmap_read(priv->regmap, TIM_ARR, &ceiling); in stm32_count_write()
79 return -EINVAL; in stm32_count_write()
81 return regmap_write(priv->regmap, TIM_CNT, val); in stm32_count_write()
91 regmap_read(priv->regmap, TIM_SMCR, &smcr); in stm32_count_function_read()
107 return -EINVAL; in stm32_count_function_read()
123 if (!priv->has_encoder) in stm32_count_function_write()
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/linux/Documentation/admin-guide/media/
H A Dcec.rst1 .. SPDX-License-Identifier: GPL-2.0
12 - Exynos4
13 - Exynos5
14 - STIH4xx HDMI CEC
15 - V4L2 adv7511 (same HW, but a different driver from the drm adv7511)
16 - stm32
17 - Allwinner A10 (sun4i)
18 - Raspberry Pi
19 - dw-hdmi (Synopsis IP)
20 - amlogic (meson ao-cec and ao-cec-g12a)
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