/linux/Documentation/devicetree/bindings/mfd/ |
H A D | st,stm32-lptimer.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 3 --- 4 $id: http://devicetree.org/schemas/mfd/st,stm32-lptimer.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 7 title: STMicroelectronics STM32 Low-Power Timers 10 The STM32 Low-Power Timer (LPTIM) is a 16-bit timer that provides several 12 - PWM output (with programmable prescaler, configurable polarity) 13 - Trigger source for STM32 ADC/DAC (LPTIM_OUT) 14 - Several counter modes: 15 - quadrature encoder to detect angular position and direction of rotary [all …]
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H A D | st,stm32-timers.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 3 --- 4 $id: http://devicetree.org/schemas/mfd/st,stm32-timers.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 7 title: STMicroelectronics STM32 Timers 10 This hardware block provides 3 types of timer along with PWM functionality: 11 - advanced-control timers consist of a 16-bit auto-reload counter driven 14 - general-purpose timers consist of a 16-bit or 32-bit auto-reload counter 16 - basic timers consist of a 16-bit auto-reload counter driven by a 20 - Fabrice Gasnier <fabrice.gasnier@foss.st.com> [all …]
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/linux/drivers/counter/ |
H A D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0-only 3 # Counter devices 8 select COUNTER 14 Interval Timer (PIT). The Intel 825x family of chips was first 21 menuconfig COUNTER config 22 tristate "Counter support" 24 This enables counter device support through the Generic Counter 26 one or more of the counter device drivers below. 28 if COUNTER 31 tristate "ACCES 104-QUAD-8 driver" [all …]
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H A D | stm32-lptimer-cnt.c | 1 // SPDX-License-Identifier: GPL-2.0 3 * STM32 Low-Power Timer Encoder and Counter driver 9 * Inspired by 104-quad-8 and stm32-timer-trigger drivers. 14 #include <linux/counter.h> 15 #include <linux/mfd/stm32-lptimer.h> 37 ret = regmap_read(priv->regmap, STM32_LPTIM_CR, &val); in stm32_lptim_is_enabled() 51 ret = regmap_write(priv->regmap, STM32_LPTIM_CR, val); in stm32_lptim_set_enable_state() 56 clk_disable(priv->clk); in stm32_lptim_set_enable_state() 57 priv->enabled = false; in stm32_lptim_set_enable_state() 61 /* LP timer must be enabled before writing CMP & ARR */ in stm32_lptim_set_enable_state() [all …]
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H A D | stm32-timer-cnt.c | 1 // SPDX-License-Identifier: GPL-2.0 3 * STM32 Timer Encoder and Counter driver 10 #include <linux/counter.h> 12 #include <linux/mfd/stm32-timers.h> 59 static int stm32_count_read(struct counter_device *counter, in stm32_count_read() argument 62 struct stm32_timer_cnt *const priv = counter_priv(counter); in stm32_count_read() 65 regmap_read(priv->regmap, TIM_CNT, &cnt); in stm32_count_read() 71 static int stm32_count_write(struct counter_device *counter, in stm32_count_write() argument 74 struct stm32_timer_cnt *const priv = counter_priv(counter); in stm32_count_write() 77 regmap_read(priv->regmap, TIM_ARR, &ceiling); in stm32_count_write() [all …]
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H A D | Makefile | 1 # SPDX-License-Identifier: GPL-2.0-only 3 # Makefile for Counter devices 6 obj-$(CONFIG_COUNTER) += counter.o 7 counter-y := counter-core.o counter-sysfs.o counter-chrdev.o 9 obj-$(CONFIG_I8254) += i8254.o 10 obj-$(CONFIG_104_QUAD_8) += 104-quad-8.o 11 obj-$(CONFIG_INTERRUPT_CNT) += interrupt-cnt.o 12 obj-$(CONFIG_RZ_MTU3_CNT) += rz-mtu3-cnt.o 13 obj-$(CONFIG_STM32_TIMER_CNT) += stm32-timer-cnt.o 14 obj-$(CONFIG_STM32_LPTIMER_CNT) += stm32-lptimer-cnt.o [all …]
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/linux/arch/arm/boot/dts/st/ |
H A D | stm32mp131.dtsi | 1 // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) 3 * Copyright (C) STMicroelectronics 2021 - All Rights Reserved 6 #include <dt-bindings/interrupt-controller/arm-gic.h> 7 #include <dt-bindings/clock/stm32mp13-clks.h> 8 #include <dt-bindings/reset/stm32mp13-resets.h> 11 #address-cells = <1>; 12 #size-cells = <1>; 15 #address-cells = <1>; 16 #size-cells = <0>; 19 compatible = "arm,cortex-a7"; [all …]
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H A D | stm32mp151.dtsi | 1 // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) 3 * Copyright (C) STMicroelectronics 2017 - All Rights Reserved 6 #include <dt-bindings/interrupt-controller/arm-gic.h> 7 #include <dt-bindings/clock/stm32mp1-clks.h> 8 #include <dt-bindings/reset/stm32mp1-resets.h> 11 #address-cells = <1>; 12 #size-cells = <1>; 15 #address-cells = <1>; 16 #size-cells = <0>; 19 compatible = "arm,cortex-a7"; [all …]
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H A D | stm32h743.dtsi | 2 * Copyright 2017 - Alexandre Torgue <alexandre.torgue@st.com> 4 * This file is dual-licensed: you can use it either under the terms 43 #include "../armv7-m.dtsi" 44 #include <dt-bindings/clock/stm32h7-clks.h> 45 #include <dt-bindings/mfd/stm32h7-rcc.h> 46 #include <dt-bindings/interrupt-controller/irq.h> 49 #address-cells = <1>; 50 #size-cells = <1>; 53 clk_hse: clk-hse { 54 #clock-cells = <0>; [all …]
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/linux/drivers/clocksource/ |
H A D | timer-stm32.c | 1 // SPDX-License-Identifier: GPL-2.0-only 4 * Author: Maxime Coquelin <mcoquelin.stm32@gmail.com> 6 * Inspired by time-efm32.c from Uwe Kleine-Koenig 23 #include "timer-of.h" 54 * stm32_timer_of_bits_set - set accessor helper 58 * Accessor helper to set the number of bits in the timer-of private 64 struct stm32_timer_private *pd = to->private_data; in stm32_timer_of_bits_set() 66 pd->bits = bits; in stm32_timer_of_bits_set() 70 * stm32_timer_of_bits_get - get accessor helper 73 * Accessor helper to get the number of bits in the timer-of private [all …]
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H A D | timer-stm32-lp.c | 1 // SPDX-License-Identifier: GPL-2.0 3 * Copyright (C) STMicroelectronics 2019 - All Rights Reserved 11 #include <linux/mfd/stm32-lptimer.h> 40 regmap_write(priv->reg, STM32_LPTIM_CR, 0); in stm32_clkevent_lp_shutdown() 41 regmap_write(priv->reg, STM32_LPTIM_IER, 0); in stm32_clkevent_lp_shutdown() 43 regmap_write(priv->reg, STM32_LPTIM_ICR, STM32_LPTIM_ARRMCF); in stm32_clkevent_lp_shutdown() 55 regmap_write(priv->reg, STM32_LPTIM_CR, 0); in stm32_clkevent_lp_set_timer() 57 regmap_write(priv->reg, STM32_LPTIM_IER, STM32_LPTIM_ARRMIE); in stm32_clkevent_lp_set_timer() 59 regmap_write(priv->reg, STM32_LPTIM_CR, STM32_LPTIM_ENABLE); in stm32_clkevent_lp_set_timer() 60 /* set next event counter */ in stm32_clkevent_lp_set_timer() [all …]
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H A D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0-only 36 bool "BCM2835 timer driver" if COMPILE_TEST 39 Enables the support for the BCM2835 timer driver. 42 bool "BCM mobile timer driver" if COMPILE_TEST 45 Enables the support for the BCM Kona mobile timer driver. 48 bool "Texas Instruments DaVinci timer driver" if COMPILE_TEST 50 Enables the support for the TI DaVinci timer driver. 53 bool "Digicolor timer driver" if COMPILE_TEST 57 Enables the support for the digicolor timer driver. 60 bool "OMAP dual-mode timer driver" if ARCH_K3 || COMPILE_TEST [all …]
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/linux/drivers/pwm/ |
H A D | pwm-stm32-lp.c | 1 // SPDX-License-Identifier: GPL-2.0 3 * STM32 Low-Power Timer PWM driver 9 * Inspired by Gerald Baeza's pwm-stm32 driver 13 #include <linux/mfd/stm32-lptimer.h> 30 /* STM32 Low-Power Timer is preceded by a configurable power-of-2 prescaler */ 46 if (!state->enabled) { in stm32_pwm_lp_apply() 48 /* Disable LP timer */ in stm32_pwm_lp_apply() 49 ret = regmap_write(priv->regmap, STM32_LPTIM_CR, 0); in stm32_pwm_lp_apply() 52 /* disable clock to PWM counter */ in stm32_pwm_lp_apply() 53 clk_disable(priv->clk); in stm32_pwm_lp_apply() [all …]
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H A D | pwm-stm32.c | 1 // SPDX-License-Identifier: GPL-2.0 7 * Inspired by timer-stm32.c from Maxime Coquelin 8 * pwm-atmel.c from Bo Shen 12 #include <linux/mfd/stm32-timers.h> 49 regmap_read(dev->regmap, TIM_CCER, &ccer); in active_channels() 69 * COUNTER: ______XXXXX . . . |_XXX 82 * 0: IC1/3 snapchot on rising edge: counter value -> CCR1/CCR3 84 * 1: IC2/4 snapchot on falling edge: counter value -> CCR2/CCR4 85 * 2: IC1/3 snapchot on rising edge: counter value -> CCR1/CCR3 89 * - Period = t2 - t0 [all …]
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/linux/include/linux/mfd/ |
H A D | stm32-lptimer.h | 1 /* SPDX-License-Identifier: GPL-2.0 */ 3 * STM32 Low-Power Timer parent driver. 6 * Inspired by Benjamin Gaignard's stm32-timers driver 22 #define STM32_LPTIM_CNT 0x1C /* Counter Reg */ 24 /* STM32_LPTIM_ISR - bit fields */ 29 /* STM32_LPTIM_ICR - bit fields */ 33 /* STM32_LPTIM_IER - bit flieds */ 36 /* STM32_LPTIM_CR - bit fields */ 41 /* STM32_LPTIM_CFGR - bit fields */ 57 * struct stm32_lptimer - STM32 Low-Power Timer data assigned by parent device [all …]
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H A D | stm32-timers.h | 1 /* SPDX-License-Identifier: GPL-2.0 */ 12 #include <linux/dma-mapping.h> 24 #define TIM_CNT 0x24 /* Counter */ 26 #define TIM_ARR 0x2c /* Auto-Reload Register */ 27 #define TIM_CCRx(x) (0x34 + 4 * ((x) - 1)) /* Capt/Comp Register x (x ∈ {1, .. 4}) */ 32 #define TIM_BDTR 0x44 /* Break and Dead-Time Reg */ 37 #define TIM_CR1_CEN BIT(0) /* Counter Enable */ 38 #define TIM_CR1_DIR BIT(4) /* Counter Direction */ 39 #define TIM_CR1_ARPE BIT(7) /* Auto-reload Preload Ena */ 45 #define TIM_DIER_CCxIE(x) BIT(1 + ((x) - 1)) /* CCx Interrupt Enable (x ∈ {1, .. 4}) */ [all …]
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/linux/drivers/watchdog/ |
H A D | stm32_iwdg.c | 1 // SPDX-License-Identifier: GPL-2.0 3 * Driver for STM32 Independent Watchdog 33 #define KR_KEY_RELOAD 0xAAAA /* reload counter enable */ 48 #define SR_RVU BIT(1) /* Watchdog counter reload value update */ 94 dev_dbg(wdd->parent, "%s\n", __func__); in stm32_iwdg_start() 96 tout = clamp_t(unsigned int, wdd->timeout, in stm32_iwdg_start() 97 wdd->min_timeout, wdd->max_hw_heartbeat_ms / 1000); in stm32_iwdg_start() 99 presc = DIV_ROUND_UP(tout * wdt->rate, RLR_MAX + 1); in stm32_iwdg_start() 103 iwdg_pr = presc <= 1 << PR_SHIFT ? 0 : ilog2(presc) - PR_SHIFT; in stm32_iwdg_start() 104 iwdg_rlr = ((tout * wdt->rate) / presc) - 1; in stm32_iwdg_start() [all …]
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/linux/drivers/iio/trigger/ |
H A D | stm32-timer-trigger.c | 1 // SPDX-License-Identifier: GPL-2.0 11 #include <linux/iio/timer/stm32-timer-trigger.h> 13 #include <linux/mfd/stm32-timers.h> 22 /* List the triggers created by each timer */ 43 /* List the triggers accepted by each timer */ 50 { }, /* timer 6 */ 51 { }, /* timer 7 */ 54 { }, /* timer 10 */ 55 { }, /* timer 11 */ 65 { }, /* timer 6 */ [all …]
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/linux/drivers/rtc/ |
H A D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0-only 44 This clock should be battery-backed, so that it reads the correct 45 time when the system boots from a power-off state. Otherwise, your 141 once-per-second update interrupts, used for synchronization. 159 will be called rtc-test. 173 will be called rtc-88pm860x. 183 will be called rtc-88pm80x. 187 tristate "Abracon AB-RTCMC-32.768kHz-B5ZE-S3" 190 AB-RTCMC-32.768kHz-B5ZE-S3 I2C RTC chip. 193 will be called rtc-ab-b5ze-s3. [all …]
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/linux/ |
H A D | MAINTAINERS | 5 --------------------------------------------------- 21 W: *Web-page* with status/info 23 B: URI for where to file *bugs*. A web-page with detailed bug 28 patches to the given subsystem. This is either an in-tree file, 29 or a URI. See Documentation/maintainer/maintainer-entry-profile.rst 46 N: [^a-z]tegra all files whose path contains tegra 64 ---------------- 83 3WARE SAS/SATA-RAID SCSI DRIVERS (3W-XXXX, 3W-9XXX, 3W-SAS) 85 L: linux-scsi@vger.kernel.org 88 F: drivers/scsi/3w-* [all …]
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