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/linux/Documentation/devicetree/bindings/input/
H A Drotary-encoder.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/input/rotary-encoder.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Frank Li <Frank.Li@nxp.com>
13 See Documentation/input/devices/rotary-encoder.rst for more information.
17 const: rotary-encoder
28 rotary-encoder,steps:
32 Number of steps in a full turnaround of the
36 rotary-encoder,relative-axis:
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/linux/drivers/input/misc/
H A Drotary_encoder.c1 // SPDX-License-Identifier: GPL-2.0-only
11 * See file:Documentation/input/devices/rotary-encoder.rst for more information
26 #define DRV_NAME "rotary-encoder"
38 u32 steps; member
51 signed char dir; /* 1 - clockwise, -1 - CCW */
61 for (i = 0; i < encoder->gpios->ndescs; ++i) { in rotary_encoder_get_state()
62 int val = gpiod_get_value_cansleep(encoder->gpios->desc[i]); in rotary_encoder_get_state()
65 if (encoder->encoding == ROTENC_GRAY && ret & 1) in rotary_encoder_get_state()
76 if (encoder->relative_axis) { in rotary_encoder_report_event()
77 input_report_rel(encoder->input, in rotary_encoder_report_event()
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/linux/Documentation/input/devices/
H A Drotary-encoder.rst2 rotary-encoder - a generic driver for GPIO connected devices
8 --------
11 peripherals with two wires. The outputs are phase-shifted by 90 degrees
16 a stable state with both outputs high (half-period mode) and some have
17 a stable state in all steps (quarter-period mode).
33 |<-------->|
36 |<-->|
37 one step (half-period mode)
40 one step (quarter-period mode)
47 ----------------------
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/linux/Documentation/trace/coresight/
H A Dcoresight-config.rst1 .. SPDX-License-Identifier: GPL-2.0
14 programming of the CoreSight system with pre-defined configurations that
17 Many CoreSight components can be programmed in complex ways - especially ETMs.
30 --------
41 accesses in the driver - the resource usage and parameter descriptions
67 system - which is described below.
74 --------------
82 enabled on a class of devices - i.e. any ETMv4, or specific devices, e.g. a
110 The following steps take place in the operation of a configuration.
118 perf record -e cs_etm/autofdo/ myapp
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/linux/tools/memory-model/Documentation/
H A Dsimple.txt2 memory-ordering lives simple, as is necessary for those whose domain
3 is complex. After all, there are bugs other than memory-ordering bugs,
4 and the time spent gaining memory-ordering knowledge is not available
5 for gaining domain knowledge. Furthermore Linux-kernel memory model
15 of MMIO-based device drivers will often need to use mb(), rmb(), and
22 Single-threaded code
25 In single-threaded code, there is no reordering, at least assuming
32 In the general case, you will need to take explicit steps to ensure that
38 this lock at a given time, your code will be executed single-threaded.
56 surprisingly hard to correctly code production-quality lock acquisition
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/linux/drivers/mtd/nand/raw/
H A Dtegra_nand.c1 // SPDX-License-Identifier: GPL-2.0
4 * Copyright (C) 2014-2015 Lucas Stach <dev@lynxeye.de>
10 #include <linux/dma-mapping.h>
34 #define COMMAND_TRANS_SIZE(size) ((((size) - 1) & 0xf) << 20)
40 #define COMMAND_CLE_SIZE(size) ((((size) - 1) & 0x3) << 4)
41 #define COMMAND_ALE_SIZE(size) ((((size) - 1) & 0xf) << 0)
156 #define OFFSET(val, off) ((val) < (off) ? 0 : (val) - (off))
207 int bytes_per_step = DIV_ROUND_UP(BITS_PER_STEP_RS * chip->ecc.strength, in tegra_nand_ooblayout_rs_ecc()
211 return -ERANGE; in tegra_nand_ooblayout_rs_ecc()
213 oobregion->offset = SKIP_SPARE_BYTES; in tegra_nand_ooblayout_rs_ecc()
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H A Ddenali.c1 // SPDX-License-Identifier: GPL-2.0
4 * Copyright © 2009-2010, Intel Corporation and its suppliers.
6 * Copyright (c) 2017-2019 Socionext Inc.
12 #include <linux/dma-mapping.h>
23 #define DENALI_NAND_NAME "denali-nand"
31 #define DENALI_MAP10 (2 << 26) /* high-level control plane */
39 #define DENALI_BANK(denali) ((denali)->active_bank << 24)
41 #define DENALI_INVALID_BANK -1
50 return container_of(chip->controller, struct denali_controller, in to_denali_controller()
55 * Direct Addressing - the slave address forms the control information (command
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/linux/Documentation/hwmon/
H A Dlm93.rst10 Addresses scanned: I2C 0x2c-0x2e
18 Addresses scanned: I2C 0x2c-0x2e
24 - Mark M. Hoffman <mhoffman@lightlink.com>
25 - Ported to 2.6 by Eric J. Bowersox <ericb@aspsys.com>
26 - Adapted to 2.6.20 by Carsten Emde <ce@osadl.org>
27 - Modified for mainline integration by Hans J. Koch <hjk@hansjkoch.de>
30 -----------------
33 Set to non-zero to force some initializations (default is 0).
38 Configures in7 and in8 limit type, where 0 means absolute and non-zero
54 --------------------
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/linux/drivers/memory/tegra/
H A Dtegra210-emc-cc-r21021.c1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (c) 2014-2020, NVIDIA CORPORATION. All rights reserved.
14 #include "tegra210-emc.h"
15 #include "tegra210-mc.h"
21 #define STEPS (1 << 1) macro
36 #define emc_dbg(emc, flags, ...) dev_dbg(emc->dev, __VA_ARGS__)
53 * PTFV defines - basically just indexes into the per table PTFV array.
78 ({ next->ptfv_list[(dev)] = \
79 next->ptfv_list[(dev)] / \
80 next->ptfv_list[PTFV_DVFS_SAMPLES_INDEX]; })
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/linux/sound/soc/meson/
H A Daxg-pdm.c1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
12 #include <sound/soc-dai.h>
53 #define PDM_CHAN_CTRL_POINTER_MAX ((1 << PDM_CHAN_CTRL_POINTER_WIDTH) - 1)
71 unsigned int steps; member
77 unsigned int steps; member
134 axg_pdm_enable(priv->map); in axg_pdm_trigger()
140 axg_pdm_disable(priv->map); in axg_pdm_trigger()
144 return -EINVAL; in axg_pdm_trigger()
150 const struct axg_pdm_filters *filters = priv->cfg->filters; in axg_pdm_get_os()
151 unsigned int os = filters->hcic.ds; in axg_pdm_get_os()
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/linux/drivers/scsi/arm/
H A Dfas216.h1 /* SPDX-License-Identifier: GPL-2.0-only */
5 * Copyright (C) 1997-2000 Russell King
101 /* Transfer period step (write) */
123 #define CLKF_F37MHZ 0x00 /* 35.01 - 40 MHz */
125 #define CLKF_F12MHZ 0x03 /* 10.01 - 15 MHz */
126 #define CLKF_F17MHZ 0x04 /* 15.01 - 20 MHz */
127 #define CLKF_F22MHZ 0x05 /* 20.01 - 25 MHz */
128 #define CLKF_F27MHZ 0x06 /* 25.01 - 30 MHz */
129 #define CLKF_F32MHZ 0x07 /* 30.01 - 35 MHz */
172 PHASE_SELSTEPS, /* selection with command steps */
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/linux/kernel/sched/
H A Dpelt.c1 // SPDX-License-Identifier: GPL-2.0
3 * Per Entity Load Tracking (PELT)
30 * val * y^n, where y^32 ~= 0.5 (~1 scheduling period)
39 /* after bounds checking we can collapse to 32-bit */ in decay_load()
43 * As y^PERIOD = 1/2, we can combine in decay_load()
44 * y^n = 1/2^(n/PERIOD) * y^(n%PERIOD) in decay_load()
45 * With a look-up table which covers y^n (n<PERIOD) in decay_load()
68 * p-1 in __accumulate_pelt_segments()
73 * = 1024 ( \Sum y^n - \Sum y^n - y^0 ) in __accumulate_pelt_segments()
76 c2 = LOAD_AVG_MAX - decay_load(LOAD_AVG_MAX, periods) - 1024; in __accumulate_pelt_segments()
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/linux/drivers/comedi/drivers/
H A Drtd520.c1 // SPDX-License-Identifier: GPL-2.0+
6 * COMEDI - Linux Control and Measurement Device Interface
13 * Devices: [Real Time Devices] DM7520HR-1 (DM7520), DM7520HR-8,
14 * PCI4520 (PCI4520), PCI4520-8
16 * Status: Works. Only tested on DM7520-8. Not SMP safe.
24 * The PCI4520 is a PCI card. The DM7520 is a PC/104-plus card.
38 * The DM7520 has slightly fewer features (fewer gain steps).
40 * These boards can support external multiplexors and multi-board
71 * Analog-In supports instruction and command mode.
73 * With DMA, you can sample at 1.15Mhz with 70% idle on a 400Mhz K6-2
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/linux/drivers/leds/
H A Dleds-mt6323.c1 // SPDX-License-Identifier: GPL-2.0-or-later
47 /* ISINK_CON1: Register to setup the period of the blink. */
69 * struct mt6323_led - state container for the LED device
83 * struct mt6323_regs - register spec for the LED device
107 * struct mt6323_hwspec - hardware specific parameters
108 * @max_period: Maximum period for all LEDs
112 * @unit_duty: Steps of duty per period
123 * struct mt6323_data - device specific data
133 * struct mt6323_leds - state container for holding LED controller
156 struct mt6323_leds *leds = led->parent; in mt6323_led_hw_brightness()
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/linux/arch/arm/boot/dts/nxp/imx/
H A Dimx6dl-b1x5pv2.dtsi1 // SPDX-License-Identifier: GPL-2.0 OR MIT
6 // Copyright 2018-2021 General Electric Company
7 // Copyright 2018-2021 Collabora
9 #include <dt-bindings/input/input.h>
10 #include "imx6dl-qmx6.dtsi"
14 stdout-path = &uart3;
20 operating-points = <
25 fsl,soc-operating-points = <
26 /* ARM kHz SOC-PU uV */
33 operating-points = <
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H A Dimx6dl-victgo.dts1 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
7 /dts-v1/;
9 #include "imx6qdl-vicut1.dtsi"
15 gpio-keys {
16 compatible = "gpio-keys";
17 pinctrl-names = "default";
18 pinctrl-0 = <&pinctrl_gpiokeys>;
21 key-power {
25 wakeup-source;
28 key-enter {
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/linux/tools/perf/Documentation/
H A Dperf-script.txt1 perf-script(1)
5 ----
6 perf-script - Read perf.data (created by perf record) and display trace output
9 ---
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/linux/kernel/rcu/
H A Dsrcutree.c1 // SPDX-License-Identifier: GPL-2.0+
3 * Sleepable Read-Copy Update mechanism for mutual exclusion.
11 * For detailed explanation of Read-Copy Update mechanism see -
33 /* Holdoff in nanoseconds for auto-expediting. */
38 /* Overflow-check frequency. N bits roughly says every 2**N grace periods. */
63 /* Number of CPUs to trigger init_srcu_struct()-time transition to big. */
67 /* Contention events per jiff
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/linux/drivers/rtc/
H A Drtc-renesas-rtca3.c1 // SPDX-License-Identifier: GPL-2.0
3 * On-Chip RTC Support available on RZ/G3S SoC
93 * enum rtca3_alrm_set_step - RTCA3 alarm set steps
105 * struct rtca3_ppb_per_cycle - PPB per cycle
106 * @ten_sec: PPB per cycle in 10 seconds adjutment mode
107 * @sixty_sec: PPB per cycle in 60 seconds adjustment mode
115 * struct rtca3_priv - RTCA3 private data structure
122 * @ppb: ppb per cycle for each the available adjustment modes
140 tmp = readb(priv->base + off); in rtca3_byte_update_bits()
143 writeb(tmp, priv->base + off); in rtca3_byte_update_bits()
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/linux/drivers/net/ethernet/freescale/
H A Dfec_ptp.c1 // SPDX-License-Identifier: GPL-2.0
92 * fec_ptp_read - read raw cycle counter (to be used by time counter)
105 tempval = readl(fep->hwp + FEC_ATIME_CTRL); in fec_ptp_read()
107 writel(tempval, fep->hwp + FEC_ATIME_CTRL); in fec_ptp_read()
109 if (fep->quirks & FEC_QUIRK_BUG_CAPTURE) in fec_ptp_read()
112 return readl(fep->hwp + FEC_ATIME); in fec_ptp_read()
129 spin_lock_irqsave(&fep->tmreg_lock, flags); in fec_ptp_enable_pps()
131 if (fep->pps_enable == enable) { in fec_ptp_enable_pps()
132 spin_unlock_irqrestore(&fep->tmreg_lock, flags); in fec_ptp_enable_pps()
139 writel(FEC_T_TF_MASK, fep->hwp + FEC_TCSR(fep->pps_channel)); in fec_ptp_enable_pps()
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/linux/drivers/net/wireless/ath/ath5k/
H A Dani.c33 * - "noise immunity"
35 * - "spur immunity"
37 * - "firstep level"
39 * - "OFDM weak signal detection"
41 * - "CCK weak signal detection"
61 * ath5k_ani_set_noise_immunity_level() - Set noise immunity level
75 static const s8 lo[] = { -52, -56, -60, -64, -70 }; in ath5k_ani_set_noise_immunity_level()
76 static const s8 hi[] = { -18, -18, -16, -14, -12 }; in ath5k_ani_set_noise_immunity_level()
77 static const s8 sz[] = { -34, -41, -48, -55, -62 }; in ath5k_ani_set_noise_immunity_level()
78 static const s8 fr[] = { -70, -72, -75, -78, -80 }; in ath5k_ani_set_noise_immunity_level()
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H A Dphy.c2 * Copyright (c) 2004-2007 Reyk Floeter <reyk@openbsd.org>
3 * Copyright (c) 2006-2009 Nick Kossifidis <mickflemm@gmail.com>
4 * Copyright (c) 2007-2008 Jiri Slaby <jirislaby@gmail.com>
5 * Copyright (c) 2008-2009 Felix Fietkau <nbd@openwrt.org>
42 * Here we handle the low-level functions related to baseband
48 * - Channel setting/switching
50 * - Automatic Gain Control (AGC) calibration
52 * - Noise Floor calibration
54 * - I/Q imbalance calibration (QAM correction)
56 * - Calibration due to thermal changes (gain_F)
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/linux/drivers/net/ethernet/intel/ixgbe/
H A Dixgbe_ptp.c1 // SPDX-License-Identifier: GPL-2.0
2 /* Copyright(c) 1999 - 2018 Intel Corporation. */
18 * period of 6.4ns. In order to convert the scale counter into
25 * PeriodWidth: Number of bits to store the clock period
27 * Period: The clock period for the oscillator
30 * Period * [ 2 ^ ( MaxWidth - PeriodWidth ) ]
32 * For the X540, MaxWidth is 31 bits, and the base period is 6.4 ns
33 * For the 82599, MaxWidth is 24 bits, and the base period is 6.4 ns
35 * The period also changes based on the link speed:
36 * At 10Gb link or no link, the period remains the same.
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/linux/Documentation/admin-guide/blockdev/
H A Dzram.rst2 zram: Compressed RAM-based block devices
8 The zram module creates RAM-based block devices named /dev/zram<id>
20 There are several ways to configure and manage zram device(-s):
23 b) using zramctl utility, provided by util-linux (util-linux@vger.kernel.org).
25 In this document we will describe only 'manual' zram configuration steps,
28 In order to get a better idea about zramctl please consult util-linux
29 documentation, zramctl man-page or `zramctl --help`. Please be informed
30 that zram maintainers do not develop/maintain util-linux or zramctl, should
31 you have any questions please contact util-linux@vger.kernel.org
33 Following shows a typical sequence of steps for using zram.
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/linux/arch/x86/mm/
H A Dkmmio.c1 // SPDX-License-Identifier: GPL-2.0
76 /* Read-protected by RCU, write-protected by kmmio_lock. */
92 /* Accessed per-cpu */
101 * Space Efficient Dynamic Stabbing with Fast Queries - Mikkel Thorup
108 if (addr >= p->addr && addr < (p->addr + p->len)) in get_kmmio_probe()
127 if (f->addr == addr) in get_kmmio_fault_page()
163 pte_t *pte = lookup_address(f->addr, &level); in clear_page_presence()
166 pr_err("no pte for addr 0x%08lx\n", f->addr); in clear_page_presence()
167 return -1; in clear_page_presence()
172 clear_pmd_presence((pmd_t *)pte, clear, &f->old_presence); in clear_page_presence()
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