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/linux/drivers/thermal/qcom/
H A Dqcom-spmi-temp-alarm.c66 /* Temperature in Milli Celsius reported during stage 0 if no ADC is present */
76 unsigned int stage; member
78 /* protects .thresh, .stage and chip registers */
86 /* This array maps from GEN2 alarm state to GEN1 alarm stage */
109 * specified over-temperature stage
111 * @stage: Over-temperature stage
115 static long qpnp_tm_decode_temp(struct qpnp_tm_chip *chip, unsigned int stage) in qpnp_tm_decode_temp() argument
117 if (!chip->temp_map || chip->thresh >= THRESH_COUNT || stage == 0 || in qpnp_tm_decode_temp()
118 stage > STAGE_COUNT) in qpnp_tm_decode_temp()
121 return (*chip->temp_map)[chip->thresh][stage - 1]; in qpnp_tm_decode_temp()
[all …]
/linux/tools/perf/pmu-events/arch/arm64/arm/cortex-a510/
H A Dpipeline.json39 …on is stalled and there is an interlock. Stall cycles due to a stall in the Wr stage are excluded",
42 …ion is stalled and there is an interlock. Stall cycles due to a stall in the Wr stage are excluded"
45 …iting for data to calculate the address. Stall cycles due to a stall in the Wr stage are excluded",
48 …aiting for data to calculate the address. Stall cycles due to a stall in the Wr stage are excluded"
51 …ock that is caused by a VPU instruction. Stall cycles due to a stall in the Wr stage are excluded",
54 …lock that is caused by a VPU instruction. Stall cycles due to a stall in the Wr stage are excluded"
57 …backend, load. This event counts every cycle where there is a stall in the Wr stage due to a load",
60 … backend, load. This event counts every cycle where there is a stall in the Wr stage due to a load"
63 …ckend, store. This event counts every cycle where there is a stall in the Wr stage due to a store",
66 …ackend, store. This event counts every cycle where there is a stall in the Wr stage due to a store"
[all …]
/linux/drivers/watchdog/
H A Dkempld_wdt.c10 * First the pretimeout stage runs out before the timeout stage gets
77 struct kempld_wdt_stage stage[KEMPLD_WDT_MAX_STAGES]; member
103 struct kempld_wdt_stage *stage, in kempld_wdt_set_stage_action() argument
109 if (!stage || !stage->mask) in kempld_wdt_set_stage_action()
113 stage_cfg = kempld_read8(pld, KEMPLD_WDT_STAGE_CFG(stage->id)); in kempld_wdt_set_stage_action()
122 kempld_write8(pld, KEMPLD_WDT_STAGE_CFG(stage->id), stage_cfg); in kempld_wdt_set_stage_action()
129 struct kempld_wdt_stage *stage, in kempld_wdt_set_stage_timeout() argument
141 if (!stage) in kempld_wdt_set_stage_timeout()
149 if (stage_timeout64 > stage->mask) in kempld_wdt_set_stage_timeout()
152 stage_timeout = stage_timeout64 & stage->mask; in kempld_wdt_set_stage_timeout()
[all …]
H A Dsbsa_gwdt.c11 * ARM SBSA Generic Watchdog has two stage timeouts:
17 * This driver can operate ARM SBSA Generic Watchdog as a single stage watchdog
19 * In the single stage mode, when the timeout is reached, your system
24 * second stage (as long as the first stage) will be reached, system will be
33 * if action is 0 (the single stage mode):
37 * Note: Since this watchdog timer has two stages, and each stage is determined
38 * by WOR, in the single stage mode, the timeout is (WOR * 2); in the two
40 * is half of that in the single stage mode.
158 * In the single stage mode, The first signal (WS0) is ignored, in sbsa_gwdt_set_timeout()
173 * In the single stage mode, if WS0 is deasserted in sbsa_gwdt_get_timeleft()
[all …]
/linux/tools/perf/pmu-events/arch/arm64/ampere/emag/
H A Dcache.json126 "PublicDescription": "Level 1 stage 2 TLB refill",
129 "BriefDescription": "L1 stage 2 TLB refill"
132 "PublicDescription": "Page walk cache level-0 stage-1 hit",
135 "BriefDescription": "Page walk, L0 stage-1 hit"
138 "PublicDescription": "Page walk cache level-1 stage-1 hit",
141 "BriefDescription": "Page walk, L1 stage-1 hit"
144 "PublicDescription": "Page walk cache level-2 stage-1 hit",
147 "BriefDescription": "Page walk, L2 stage-1 hit"
150 "PublicDescription": "Page walk cache level-1 stage-2 hit",
153 "BriefDescription": "Page walk, L1 stage-2 hit"
[all …]
/linux/tools/testing/selftests/kvm/aarch64/
H A Dhypercalls.c
/linux/tools/testing/selftests/kvm/x86_64/
H A Dvmx_preemption_timer_test.c
H A Dset_boot_cpu_id.c
H A Dhyperv_ipi.c
H A Dhyperv_tlb_flush.c
H A Dhyperv_clock.c
H A Dsmm_test.c
/linux/tools/perf/pmu-events/arch/arm64/arm/cortex-a55/
H A Dpipeline.json39 … is due to an FPU/NEON instruction. Stall cycles due to a stall in the Wr stage (typically awaitin…
42 … is due to an FPU/NEON instruction. Stall cycles due to a stall in the Wr stage (typically awaitin…
45 …to the backend, load.This event counts every cycle there is a stall in the Wr stage due to a load",
48 … to the backend, load.This event counts every cycle there is a stall in the Wr stage due to a load"
51 … the backend, store.This event counts every cycle there is a stall in the Wr stage due to a store",
54 …o the backend, store.This event counts every cycle there is a stall in the Wr stage due to a store"
57 …load, cache miss.This event counts every cycle there is a stall in the Wr stage due to a load whic…
60 …load, cache miss.This event counts every cycle there is a stall in the Wr stage due to a load whic…
63 …, load, TLB miss.This event counts every cycle there is a stall in the Wr stage due to a load whic…
66 …, load, TLB miss.This event counts every cycle there is a stall in the Wr stage due to a load whic…
[all …]
/linux/tools/testing/selftests/kvm/s390x/
H A Dtprot.c
/linux/drivers/net/wwan/iosm/
H A Diosm_ipc_mmio.c22 /* CP execution stage */
47 * execution stage into mmio area
51 /* check if exec stage has one of the valid values */
52 static bool ipc_mmio_is_valid_exec_stage(enum ipc_mem_exec_stage stage) in ipc_mmio_is_valid_exec_stage() argument
54 switch (stage) { in ipc_mmio_is_valid_exec_stage()
87 enum ipc_mem_exec_stage stage; in ipc_mmio_init() local
98 /* Check for a valid execution stage to make sure that the boot code in ipc_mmio_init()
102 stage = ipc_mmio_get_exec_stage(ipc_mmio); in ipc_mmio_init()
103 if (ipc_mmio_is_valid_exec_stage(stage)) in ipc_mmio_init()
110 dev_err(ipc_mmio->dev, "invalid exec stage %X", stage); in ipc_mmio_init()
/linux/tools/testing/selftests/tc-testing/
H A DTdcPlugin.py43 def adjust_command(self, stage, command): argument
46 print(' -- {}.adjust_command {}'.format(self.sub_class, stage))
48 # if stage == 'pre':
50 # elif stage == 'setup':
52 # elif stage == 'execute':
54 # elif stage == 'verify':
56 # elif stage == 'teardown':
58 # elif stage == 'post':
/linux/Documentation/leds/
H A Dleds-sc27xx.rst16 for the high stage. To be compatible with the hardware pattern
17 format, we should set brightness as 0 for rise stage, fall
18 stage and low stage.
20 - Min stage duration: 125 ms
21 - Max stage duration: 31875 ms
23 Since the stage duration step is 125 ms, the duration should be
/linux/drivers/net/ethernet/microchip/vcap/
H A Dvcap_api.h17 #define VCAP_CID_INGRESS_L0 1000000 /* Ingress Stage 1 Lookup 0 */
18 #define VCAP_CID_INGRESS_L1 1100000 /* Ingress Stage 1 Lookup 1 */
19 #define VCAP_CID_INGRESS_L2 1200000 /* Ingress Stage 1 Lookup 2 */
20 #define VCAP_CID_INGRESS_L3 1300000 /* Ingress Stage 1 Lookup 3 */
21 #define VCAP_CID_INGRESS_L4 1400000 /* Ingress Stage 1 Lookup 4 */
22 #define VCAP_CID_INGRESS_L5 1500000 /* Ingress Stage 1 Lookup 5 */
24 #define VCAP_CID_PREROUTING_IPV6 3000000 /* Prerouting Stage */
25 #define VCAP_CID_PREROUTING 6000000 /* Prerouting Stage */
27 #define VCAP_CID_INGRESS_STAGE2_L0 8000000 /* Ingress Stage 2 Lookup 0 */
28 #define VCAP_CID_INGRESS_STAGE2_L1 8100000 /* Ingress Stage 2 Lookup 1 */
[all …]
/linux/arch/powerpc/crypto/
H A Daesp10-ppc.pl122 my ($stage,$outperm,$outmask,$outhead,$outtail)=map("v$_",(7..11));
204 vsel $stage,$outhead,$outtail,$outmask
207 stvx $stage,0,$out
224 vsel $stage,$outhead,$outtail,$outmask
227 stvx $stage,0,$out
241 vsel $stage,$outhead,$outtail,$outmask
244 stvx $stage,0,$out
254 vsel $stage,$outhead,$outtail,$outmask
256 stvx $stage,0,$out
269 vsel $stage,$outhead,$outtail,$outmask
[all …]
/linux/drivers/gpu/drm/ci/
H A Dtest.yml94 stage: msm
123 stage: msm
140 stage: msm
154 stage: msm
168 stage: msm
187 stage: rockchip
235 stage: i915
317 stage: amdgpu
336 stage: mediatek
343 stage: mediatek
[all …]
/linux/sound/soc/sprd/
H A Dsprd-pcm-compress.c28 /* Stage 0 IRAM buffer size definition */
36 /* Stage 1 DDR buffer size definition */
52 * The Spreadtrum Audio compress offload mode will use 2-stage DMA transfer to
58 * For 2-stage DMA transfer, we can allocate 2 buffers: IRAM buffer (always
77 /* Stage 0 IRAM buffer */
79 /* Stage 1 DDR buffer */
91 /* Stage 0 IRAM buffer received data size */
93 /* Stage 1 DDR buffer received data size */
95 /* Stage 1 DDR buffer pointer */
275 * Configure the DMA engine 2-stage transfer mode. Channel 1 set as the in sprd_platform_compr_set_params()
[all …]
/linux/arch/arm64/kvm/hyp/nvhe/
H A Dtlb.c79 * avoid a Stage-1 walk with the old VMID while we have in enter_vmid_context()
158 * Instead, we invalidate Stage-2 for this IPA, and the in __kvm_tlb_flush_vmid_ipa()
159 * whole of Stage-1. Weep... in __kvm_tlb_flush_vmid_ipa()
165 * We have to ensure completion of the invalidation at Stage-2, in __kvm_tlb_flush_vmid_ipa()
167 * complete (S1 + S2) walk based on the old Stage-2 mapping if in __kvm_tlb_flush_vmid_ipa()
168 * the Stage-1 invalidation happened first. in __kvm_tlb_flush_vmid_ipa()
188 * Instead, we invalidate Stage-2 for this IPA, and the in __kvm_tlb_flush_vmid_ipa_nsh()
189 * whole of Stage-1. Weep... in __kvm_tlb_flush_vmid_ipa_nsh()
195 * We have to ensure completion of the invalidation at Stage-2, in __kvm_tlb_flush_vmid_ipa_nsh()
197 * complete (S1 + S2) walk based on the old Stage-2 mapping if in __kvm_tlb_flush_vmid_ipa_nsh()
[all …]
/linux/arch/arm64/kvm/hyp/vhe/
H A Dtlb.c36 * we cannot trust stage-1 to be in a correct state at that in enter_vmid_context()
79 /* ... and the stage-2 MMU context that we switched away from */ in exit_vmid_context()
104 * Instead, we invalidate Stage-2 for this IPA, and the in __kvm_tlb_flush_vmid_ipa()
105 * whole of Stage-1. Weep... in __kvm_tlb_flush_vmid_ipa()
111 * We have to ensure completion of the invalidation at Stage-2, in __kvm_tlb_flush_vmid_ipa()
113 * complete (S1 + S2) walk based on the old Stage-2 mapping if in __kvm_tlb_flush_vmid_ipa()
114 * the Stage-1 invalidation happened first. in __kvm_tlb_flush_vmid_ipa()
136 * Instead, we invalidate Stage-2 for this IPA, and the in __kvm_tlb_flush_vmid_ipa_nsh()
137 * whole of Stage-1. Weep... in __kvm_tlb_flush_vmid_ipa_nsh()
143 * We have to ensure completion of the invalidation at Stage-2, in __kvm_tlb_flush_vmid_ipa_nsh()
[all …]
/linux/tools/testing/selftests/tc-testing/plugin-lib/
H A DnsPlugin.py86 def adjust_command(self, stage, command): argument
87 super().adjust_command(stage, command)
99 if stage == 'setup' or stage == 'execute' or stage == 'verify' or stage == 'teardown':
101 …print('adjust_command: stage is {}; inserting netns stuff in command [{}] list [{}]'.format(stage…
221 def _exec_cmd(self, stage, command): argument
240 def _exec_cmd_batched(self, stage, commands): argument
242 self._exec_cmd(stage, cmd)
/linux/tools/testing/selftests/kvm/
H A Dkvm_page_table_test.c71 /* Whether the test stage is updated, or completed */
100 * All vCPU threads will be started in this stage, in guest_code()
189 enum test_stage stage; in vcpu_worker() local
211 stage = READ_ONCE(*current_stage); in vcpu_worker()
217 pr_debug("vCPU %d has completed stage %s\n" in vcpu_worker()
219 vcpu->id, test_stage_string[stage], in vcpu_worker()
316 static void vcpus_complete_new_stage(enum test_stage stage) in vcpus_complete_new_stage() argument
321 /* Wake up all the vcpus to run new test stage */ in vcpus_complete_new_stage()
328 /* Wait for all the vcpus to complete new test stage */ in vcpus_complete_new_stage()
333 pr_debug("%d vcpus have completed stage %s\n", in vcpus_complete_new_stage()
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