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/freebsd/sys/dev/isci/scil/
H A Dscu_bios_definitions.h1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause OR GPL-2.0
9 * Copyright(c) 2008 - 2011 Intel Corporation. All rights reserved.
22 * Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
28 * Copyright(c) 2008 - 2011 Intel Corporation. All rights reserved.
64 * stand-alone where the library is excluded. By excluding
100 // port configuration mode
195 * This field indicates the port configuration mode for
207 * By default, the mode type is APC
208 * in APC mode, if ANY of the phy mask is non-zero,
[all …]
/freebsd/sys/contrib/device-tree/Bindings/misc/
H A Datmel-ssc.txt1 * Atmel SSC driver.
4 - compatible: "atmel,at91rm9200-ssc" or "atmel,at91sam9g45-ssc"
5 - atmel,at91rm9200-ssc: support pdc transfer
6 - atmel,at91sam9g45-ssc: support dma transfer
7 - reg: Should contain SSC registers location and length
8 - interrupts: Should contain SSC interrupt
9 - clock-names: tuple listing input clock names.
11 - clocks: phandles to input clocks.
14 Required properties for devices compatible with "atmel,at91sam9g45-ssc":
15 - dmas: DMA specifier, consisting of a phandle to DMA controller node,
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/freebsd/sys/contrib/device-tree/Bindings/i2c/
H A Di2c-st.txt1 ST SSC binding, for I2C mode operation
4 - compatible : Must be "st,comms-ssc-i2c" or "st,comms-ssc4-i2c"
5 - reg : Offset and length of the register set for the device
6 - interrupts : the interrupt specifier
7 - clock-names: Must contain "ssc".
8 - clocks: Must contain an entry for each name in clock-names. See the common
10 - A pinctrl state named "default" must be defined to set pins in mode of
14 - clock-frequency : Desired I2C bus clock frequency in Hz. If not specified,
17 - st,i2c-min-scl-pulse-width-us : The minimum valid SCL pulse width that is
19 - st,i2c-min-sda-pulse-width-us : The minimum valid SDA pulse width that is
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/freebsd/sys/contrib/device-tree/Bindings/clock/ti/
H A Ddpll.txt3 Binding status: Unstable - ABI compatibility may be broken in the future
6 register-mapped DPLL with usually two selectable input clocks
11 sub-types, which effectively result in slightly different setup
14 [1] Documentation/devicetree/bindings/clock/clock-bindings.txt
17 - compatible : shall be one of:
18 "ti,omap3-dpll-clock",
19 "ti,omap3-dpll-core-clock",
20 "ti,omap3-dpll-per-clock",
21 "ti,omap3-dpll-per-j-type-clock",
22 "ti,omap4-dpll-clock",
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/freebsd/sys/contrib/device-tree/Bindings/clock/
H A Dti,cdce925.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schema
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H A Dti,cdce925.txt6 [1] Documentation/devicetree/bindings/clock/clock-bindings.txt
15 - compatible: Shall be one of the following:
16 - "ti,cdce913": 1-PLL, 3 Outputs
17 - "ti,cdce925": 2-PLL, 5 Outputs
18 - "ti,cdce937": 3-PLL, 7 Outputs
19 - "ti,cdce949": 4-PLL, 9 Outputs
20 - reg: I2C device address.
21 - clocks: Points to a fixed parent clock that provides the input frequency.
22 - #clock-cells: From common clock bindings: Shall be 1.
25 - xtal-load-pf: Crystal load-capacitor value to fine-tune performance on a
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/freebsd/sys/arm64/rockchip/
H A Drk3568_combphy.c1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
49 #include <contrib/device-tree/include/dt-bindings/phy/phy.h>
57 {"rockchip,rk3568-naneng-combphy", 1},
72 int mode; member
174 switch (sc->mode) { in rk3568_combphy_enable()
179 bus_write_4(sc->mem, PHYREG7, in rk3568_combphy_enable()
183 bus_write_4(sc->mem, PHYREG15, in rk3568_combphy_enable()
184 bus_read_4(sc->mem, PHYREG15) | PHYREG15_CTLE_EN); in rk3568_combphy_enable()
187 SYSCON_WRITE_4(sc->pipe_phy_grf, PIPE_PHY_GRF_PIPE_CON3, in rk3568_combphy_enable()
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/freebsd/sys/dev/usb/serial/
H A Dusb_serial.c3 /*-
4 * SPDX-License-Identifier: BSD-2-Clause
6 * Copyright (c) 2001-2003, 2005, 2008
33 /*-
105 "pulse capture mode: 0/1/2=disabled/CTS/DCD; add 0x10 to invert");
111 "set to 1 to mark terminals as consoles when in device mode");
131 static int ucom_cons_unit = -1;
200 ucom_unrhdr = new_unrhdr(0, UCOM_UNIT_MAX - 1, NULL); in ucom_init()
203 SYSINIT(ucom_init, SI_SUB_KLD - 1, SI_ORDER_ANY, ucom_init, NULL);
219 SYSUNINIT(ucom_uninit, SI_SUB_KLD - 3, SI_ORDER_ANY, ucom_uninit, NULL);
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/freebsd/sys/contrib/device-tree/Bindings/phy/
H A Dphy-rockchip-naneng-combphy.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/phy/phy-rockchip-naneng-combphy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Heiko Stuebner <heiko@sntech.de>
15 - rockchip,rk3568-naneng-combphy
16 - rockchip,rk3588-naneng-combphy
23 - description: reference clock
24 - description: apb clock
25 - description: pipe clock
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H A Dbrcm-sata-phy.txt4 - compatible: should be one or more of
5 "brcm,bcm7216-sata-phy"
6 "brcm,bcm7425-sata-phy"
7 "brcm,bcm7445-sata-phy"
8 "brcm,iproc-ns2-sata-phy"
9 "brcm,iproc-nsp-sata-phy"
10 "brcm,phy-sata3"
11 "brcm,iproc-sr-sata-phy"
12 "brcm,bcm63138-sata-phy"
13 - address-cells: should be 1
[all …]
H A Dphy-cadence-torrent.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/phy/phy-cadence-torrent.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
16 - Swapnil Jakhade <sjakhade@cadence.com>
17 - Yuti Amonkar <yamonkar@cadence.com>
22 - cdns,torrent-phy
23 - ti,j721e-serdes-10g
25 '#address-cells':
28 '#size-cells':
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H A Dbrcm,sata-phy.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/phy/brcm,sata-phy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Florian Fainelli <f.fainelli@gmail.com>
14 pattern: "^sata[-|_]phy(@.*)?$"
18 - items:
19 - enum:
20 - brcm,bcm7216-sata-phy
21 - brcm,bcm7425-sata-phy
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/freebsd/sys/contrib/device-tree/src/arm/st/
H A Dstih407-family.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
6 #include "stih407-pinctrl.dtsi"
7 #include <dt-bindings/mfd/st-lpc.h>
8 #include <dt-bindings/phy/phy.h>
9 #include <dt-bindings/reset/stih407-reset
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/freebsd/sys/contrib/device-tree/src/arm/microchip/
H A Dmpa1600.dts1 // SPDX-License-Identifier: GPL-2.0-only
3 * mpa1600.dts - Device Tree file for Phontech MPA 1600
7 /dts-v1/;
20 clock-frequency = <32768>;
24 clock-frequency = <18432000>;
36 compatible = "atmel,tcb-timer";
41 compatible = "atmel,tcb-timer";
47 phy-mode = "rmii";
51 ssc0: ssc@fffd0000 {
55 ssc1: ssc@fffd4000 {
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H A Dat91rm9200.dtsi1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * at91rm9200.dtsi - Device Tree Include file for AT91RM9200 family SoC
12 #include <dt-bindings/pinctrl/at91.h>
13 #include <dt-bindings/interrupt-controller/irq.h>
14 #include <dt-binding
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H A Dat91sam9261.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
3 * at91sam9261.dtsi - Device Tree Include file for AT91SAM9261 SoC
5 * Copyright (C) 2013 Jean-Jacques Hiblot <jjhiblot@traphandler.com>
8 #include <dt-bindings/pinctrl/at91.h>
9 #include <dt-bindings/interrupt-controller/irq.h>
10 #include <dt-binding
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H A Dat91sam9g20ek_common.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
3 * at91sam9g20ek_common.dtsi - Device Tree file for Atmel at91sam9g20ek board
5 * Copyright (C) 2012 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
8 #include <dt-bindings/input/input.h>
14 stdout-path = "serial0:115200n8";
23 clock-frequency = <32768>;
27 clock-frequency = <18432000>;
50 pinctrl_board_mmc0_slot1: mmc0_slot1-board {
63 compatible = "atmel,tcb-timer";
68 compatible = "atmel,tcb-timer";
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H A Dat91-sama5d4ek.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * at91-sama5d4ek.dts - Device Tree file for SAMA5D4 Evaluation Kit
8 /dts-v1/;
12 model = "Atmel SAMA5D4-EK";
16 stdout-path = "serial0:115200n8";
25 clock-frequency = <32768>;
29 clock-frequency = <12000000>;
36 pinctrl-names = "default";
37 pinctrl-0 = <
45 /* The vref depends on JP22 of EK. If connect 1-2 then use 3.3V. connect 2-3 use 3.0V */
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H A Dsama5d3xmb_cmp.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * sama5d3xmb_cmp.dts - Device Tree file for SAMA5D3x CMP mother board
10 compatible = "atmel,sama5d3xmb-cmp", "atmel,sama5d3xcm-cmp", "atmel,sama5d3", "atmel,sama5";
15 pinctrl-names = "default";
16 pinctrl-0 = <&pinctrl_mmc0_clk_cmd_dat0 &pinctrl_mmc0_dat1_3 &pinctrl_mmc0_cd>;
20 bus-width = <4>;
21 cd-gpios = <&pioD 17 GPIO_ACTIVE_HIGH>;
30 spi-max-frequency = <50000000>;
35 ssc0: ssc@f0008000 {
36 atmel,clk-from-rk-pin;
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H A Dat91sam9rl.dtsi1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * at91sam9rl.dtsi - Device Tree Include file for AT91SAM9RL family SoC
6 * Alexandre Belloni <alexandre.belloni@free-electrons.com>
9 #include <dt-bindings/pinctrl/at91.h>
10 #include <dt-bindings/clock/at91.h>
11 #include <dt-binding
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H A Dat91sam9n12ek.dts1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * at91sam9n12ek.dts - Device Tree file for AT91SAM9N12-EK board
8 /dts-v1/;
12 model = "Atmel AT91SAM9N12-EK";
17 stdout-path = "serial0:115200n8";
26 clock-frequency = <32768>;
30 clock-frequency = <16000000>;
40 ssc0: ssc@f0010000 {
46 compatible = "atmel,tcb-timer";
51 compatible = "atmel,tcb-timer";
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H A Dat91sam9260ek.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
8 /dts-v1/;
10 #include <dt-bindings/input/input.h>
17 stdout-path = &dbgu;
26 clock-frequency = <32768>;
30 clock-frequency = <18432000>;
38 compatible = "atmel,tcb-timer";
43 compatible = "atmel,tcb-timer";
49 atmel,vbus-gpio = <&pioC 5 GPIO_ACTIVE_HIGH>;
54 pinctrl-0 = <
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/freebsd/sys/dev/ath/ath_rate/sample/
H A Dsample.c1 /*-
2 * SPDX-License-Identifier: BSD-3-Clause
17 * 3. Neither the names of the above-listed copyright holders nor the names
86 * in "Bit-rate Selection in Wireless Networks"
87 * (http://www.pdos.lcs.mit.edu/papers/jbicket-ms.ps)
89 * SampleRate chooses the bit-rate it predicts will provide the most
90 * throughput based on estimates of the expected per-packet
91 * transmission time for each bit-rate. SampleRate periodically sends
92 * packets at bit-rates other than the current one to estimate when
93 * another bit-rate will provide better performance. SampleRate
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/freebsd/sys/cam/scsi/
H A Dscsi_sa.h1 /*-
5 * SPDX-License-Identifier: BSD-2-Clause
49 #define RBL_GRAN(rblim) ((rblim)->gran & RBL_GRAN_MASK)
158 * Format tape media. The CDB opcode is the same as the disk-specific
192 * Dev specific mode page masks.
197 #define SMH_SA_BUF_MODE_SIBUF 0x10 /* Single-Initiator buffering */
198 #define SMH_SA_BUF_MODE_MIBUF 0x20 /* Multi-Initiator buffering */
203 * Sequential-access specific mode page numbers.
210 #define SA_DATA_COMPRESSION_PAGE 0x0f /* SCSI-3 */
213 * Mode page definitions.
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H A Dscsi_enc_internal.h1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
48 void *elm_private; /* per-type object data */
65 typedef int fsm_fill_handler_t(enc_softc_t *ssc,
71 typedef int fsm_done_handler_t(enc_softc_t *ssc,
117 void *private; /* per-type private data */
124 void *enc_private; /* per-type private data */
155 /* Callout for auto-updating enclosure status */
169 return (primary == &enc->enc_cache in enc_other_cache()
170 ? &enc->enc_daemon_cache : &enc->enc_cache); in enc_other_cache()
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