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/linux/Documentation/devicetree/bindings/phy/
H A Dmediatek,xsphy.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 ---
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: MediaTek XS-PHY Controller
11 - Chunfeng Yun <chunfeng.yun@mediatek.com>
14 The XS-PHY controller supports physical layer functionality for USB3.1
18 ----------------------------------
45 pattern: "^xs-phy@[0-9a-f]+$"
49 - enum:
50 - mediatek,mt3611-xsphy
[all …]
H A Dmediatek,tphy.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 ---
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: MediaTek T-PHY Controller
11 - Chunfeng Yun <chunfeng.yun@mediatek.com>
14 The T-PHY controller supports physical layer functionality for a number of
17 Layout differences of banks between T-PHY V1 (mt8173/mt2701) and
18 T-PHY V2 (mt2712) / V3 (mt8195) when works on USB mode:
19 -----------------------------------
67 pattern: "^t-phy(@[0-9a-f]+)?$"
[all …]
/linux/Documentation/devicetree/bindings/media/
H A Dnxp,imx8mq-mipi-csi2.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/media/nxp,imx8mq-mipi-csi2.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: NXP i.MX8MQ MIPI CSI-2 receiver
10 - Martin Kepplinger <martin.kepplinger@puri.sm>
12 description: |-
13 This binding covers the CSI-2 RX PHY and host controller included in the
20 - fsl,imx8mq-mipi-csi2
27 - description: core is the RX Controller Core Clock input. This clock
[all …]
/linux/drivers/phy/mediatek/
H A Dphy-mtk-xsphy.c1 // SPDX-License-Identifier: GPL-2.0
10 #include <dt-bindings/phy/phy.h>
11 #include <linux/clk.h>
19 #include "phy-mtk-io.h"
79 #define XSP_REF_CLK 26 /* MHZ */
87 struct clk *ref_clk; /* reference clock of anolog phy */
105 int src_ref_clk; /* MHZ, reference clock for slew rate calibrate */
112 void __iomem *pbase = inst->port_base; in u2_phy_slew_rate_calibrate()
118 if (inst->eye_src) in u2_phy_slew_rate_calibrate()
149 tmp = xsphy->src_ref_clk * xsphy->src_coef; in u2_phy_slew_rate_calibrate()
[all …]
H A Dphy-mtk-tphy.c1 // SPDX-License-Identifier: GPL-2.0
8 #include <dt-bindings/phy/phy.h>
9 #include <linux/clk.h>
15 #include <linux/nvmem-consumer.h>
22 #include "phy-mtk-io.h"
24 /* version V1 sub-banks offset base address */
35 /* version V2/V3 sub-banks offset base address */
213 #define U3P_REF_CLK 26 /* MHZ */
220 /* CDR Charge Pump P-path current adjustment */
239 /* TX driver tail current control for 0dB de-empahsis mdoe for Gen1 speed */
[all …]
/linux/drivers/gpu/drm/nouveau/nvkm/subdev/clk/
H A Dmcp77.c42 read_div(struct mcp77_clk *clk) in read_div() argument
44 struct nvkm_device *device = clk->base.subdev.device; in read_div()
49 read_pll(struct mcp77_clk *clk, u32 base) in read_pll() argument
51 struct nvkm_device *device = clk->base.subdev.device; in read_pll()
54 u32 ref = nvkm_clk_read(&clk->base, nv_clk_src_href); in read_pll() local
73 clock = ref * N1 / M1; in read_pll()
81 mcp77_clk_read(struct nvkm_clk *base, enum nv_clk_src src) in mcp77_clk_read() argument
83 struct mcp77_clk *clk = mcp77_clk(base); in mcp77_clk_read() local
84 struct nvkm_subdev *subdev = &clk->base.subdev; in mcp77_clk_read()
85 struct nvkm_device *device = subdev->device; in mcp77_clk_read()
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/linux/drivers/net/can/mscan/
H A Dmpc5xxx_can.c1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright (C) 2004-2005 Andrey Volkov <avolkov@varma-el.com>,
7 * Copyright (C) 2008-2009 Wolfgang Grandegger <wg@grandegger.com>
23 #include <linux/clk.h>
40 { .compatible = "fsl,mpc5200-cdm", },
68 freq = mpc5xxx_get_bus_frequency(&ofdev->dev); in mpc52xx_can_get_clock()
78 dev_err(&ofdev->dev, "can't get clock node!\n"); in mpc52xx_can_get_clock()
84 dev_err(&ofdev->dev, "can't map clock node!\n"); in mpc52xx_can_get_clock()
88 if (in_8(&cdm->ipb_clk_sel) & 0x1) in mpc52xx_can_get_clock()
90 val = in_be32(&cdm->rstcfg); in mpc52xx_can_get_clock()
[all …]
/linux/drivers/net/ethernet/stmicro/stmmac/
H A Ddwmac-stm32.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * dwmac-stm32.c - DWMAC Specific Glue layer for STM32 MCU
9 #include <linux/clk.h>
37 *------------------------------------------
38 * src |BIT(23)| BIT(22)| BIT(21)|BIT(20)|
39 *------------------------------------------
41 *------------------------------------------
43 *------------------------------------------
45 *------------------------------------------
47 *------------------------------------------
[all …]
/linux/drivers/phy/
H A Dphy-xgene.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * AppliedMicro X-Gene Multi-purpose PHY driver
10 * The APM X-Gene PHY consists of two PLL clock macro's (CMU) and lanes.
19 * -----------------
20 * | Internal | |------|
21 * | Ref PLL CMU |----| | ------------- ---------
22 * ------------ ---- | MUX |-----|PHY PLL CMU|----| Serdes|
23 * | | | | ---------
24 * External Clock ------| | -------------
25 * |------|
[all …]
/linux/sound/soc/codecs/
H A Drt5682s.c1 // SPDX-License-Identifier: GPL-2.0-only
3 // rt5682s.c -- RT5682I-VS ALSA SoC audio component driver
25 #include <sound/soc-dapm.h>
38 .dai_clk_names[RT5682S_DAI_WCLK_IDX] = "rt5682-dai-wclk",
39 .dai_clk_names[RT5682S_DAI_BCLK_IDX] = "rt5682-dai-bclk",
46 [RT5682S_SUPPLY_LDO1_IN] = "LDO1-IN",
69 ret = regmap_multi_reg_write(rt5682s->regmap, patch_list, ARRAY_SIZE(patch_list)); in rt5682s_apply_patch_list()
624 regmap_write(rt5682s->regmap, RT5682S_RESET, 0); in rt5682s_reset()
634 dev_dbg(component->dev, "%s btn_type=%x\n", __func__, btn_type); in rt5682s_button_detect()
651 mutex_lock(&rt5682s->sar_mutex); in rt5682s_sar_power_mode()
[all …]
H A Drt5682.c1 // SPDX-License-Identifier: GPL-2.0-only
3 // rt5682.c -- RT5682 ALSA SoC audio component driver
25 #include <sound/soc-dapm.h>
38 "LDO1-IN",
60 ret = regmap_multi_reg_write(rt5682->regmap, patch_list, in rt5682_apply_patch_list()
749 static const DECLARE_TLV_DB_SCALE(dac_vol_tlv, -6525, 75, 0);
750 static const DECLARE_TLV_DB_SCALE(adc_vol_tlv, -1725, 75, 0);
817 regmap_write(rt5682->regmap, RT5682_RESET, 0); in rt5682_reset()
818 if (!rt5682->is_sdw) in rt5682_reset()
819 regmap_write(rt5682->regmap, RT5682_I2C_MODE, 1); in rt5682_reset()
[all …]
H A Dmadera.c1 // SPDX-License-Identifier: GPL-2.0-only
5 // Copyright (C) 2015-2019 Cirrus Logic, Inc. and
18 #include <linux/irqchip/irq-madera.h>
22 #include <sound/madera-pdata.h>
24 #include <dt-bindings/sound/madera.h>
143 dev_err(_fll->madera->dev, "FLL%d: " fmt, _fll->id, ##__VA_ARGS__)
145 dev_warn(_fll->madera->dev, "FLL%d: " fmt, _fll->id, ##__VA_ARGS__)
147 dev_dbg(_fll->madera->dev, "FLL%d: " fmt, _fll->id, ##__VA_ARGS__)
150 dev_err(_dai->dev, "AIF%d: " fmt, _dai->id, ##__VA_ARGS__)
152 dev_warn(_dai->dev, "AIF%d: " fmt, _dai->id, ##__VA_ARGS__)
[all …]
H A Drt5668.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * rt5668.c -- RT5668B ALSA SoC audio component driver
26 #include <sound/soc-dapm.h>
746 static const DECLARE_TLV_DB_SCALE(hp_vol_tlv, -2250, 150, 0);
747 static const DECLARE_TLV_DB_SCALE(dac_vol_tlv, -65625, 375, 0);
748 static const DECLARE_TLV_DB_SCALE(adc_vol_tlv, -17625, 375, 0);
803 * rt5668_sel_asrc_clk_src - select ASRC clock source for a set of filters
827 return -EINVAL; in rt5668_sel_asrc_clk_src()
887 * rt5668_headset_detect - Detect headset.
922 rt5668->jack_type = SND_JACK_HEADSET; in rt5668_headset_detect()
[all …]
H A Dmt6351.c1 // SPDX-License-Identifier: GPL-2.0
3 // mt6351.c -- mt6351 ALSA SoC audio codec driver
8 #include <linux/dma-mapping.h>
202 regmap_update_bits(cmpnt->regmap, MT6351_ZCD_CON2, in set_hp_gain_zero()
204 regmap_update_bits(cmpnt->regmap, MT6351_ZCD_CON2, in set_hp_gain_zero()
225 dev_warn(cmpnt->dev, "%s(), error rate %d, return 3", in get_cap_reg_val()
256 dev_warn(cmpnt->dev, "%s(), error rate %d, return 8", in get_play_reg_val()
266 struct snd_soc_component *cmpnt = dai->component; in mt6351_codec_dai_hw_params()
270 dev_dbg(priv->dev, "%s(), substream->stream %d, rate %d\n", in mt6351_codec_dai_hw_params()
271 __func__, substream->stream, rate); in mt6351_codec_dai_hw_params()
[all …]
H A Drt5665.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * rt5665.c -- RT5665/RT5658 ALSA SoC audio codec driver
26 #include <sound/soc-dapm.h>
887 static const DECLARE_TLV_DB_SCALE(hp_vol_tlv, -2250, 150, 0);
888 static const DECLARE_TLV_DB_SCALE(mono_vol_tlv, -1400, 150, 0);
889 static const DECLARE_TLV_DB_SCALE(out_vol_tlv, -4650, 150, 0);
890 static const DECLARE_TLV_DB_SCALE(dac_vol_tlv, -65625, 375, 0);
891 static const DECLARE_TLV_DB_SCALE(in_vol_tlv, -3450, 150, 0);
892 static const DECLARE_TLV_DB_SCALE(adc_vol_tlv, -17625, 375, 0);
894 static const DECLARE_TLV_DB_SCALE(in_bst_tlv, -1200, 75, 0);
[all …]
/linux/drivers/gpu/drm/gma500/
H A Dcdv_intel_display.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright © 2006-2011 Intel Corporation
57 /* The single-channel range is 25-112Mhz, and dual-channel
58 * is 80-224Mhz. Prefer single channel as much as possible.
118 ret__ = -ETIMEDOUT; \
217 int pipe = gma_crtc->pipe; in cdv_dpll_set_clock_cdv()
231 /* Follow the BIOS and write the REF/SFR Register. Hardcoded value */ in cdv_dpll_set_clock_cdv()
240 * The BIT 14:13 of 0x8010/0x8030 is used to select the ref clk in cdv_dpll_set_clock_cdv()
248 * if DPLLA sets 01 and DPLLB sets 02, both use clk from DPLLA in cdv_dpll_set_clock_cdv()
272 m |= ((clock->m2) << SB_M_DIVIDER_SHIFT); in cdv_dpll_set_clock_cdv()
[all …]
/linux/arch/arm64/boot/dts/freescale/
H A Dimx8mp.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 #include <dt-bindings/clock/imx8mp-clock.h>
7 #include <dt-bindings/power/imx8mp-power.h>
8 #include <dt-bindings/reset/imx8mp-reset.h>
9 #include <dt-bindings/gpio/gpio.h>
10 #include <dt-bindings/input/input.h>
11 #include <dt-bindings/interconnect/fsl,imx8mp.h>
12 #include <dt-bindings/interrupt-controller/arm-gic.h>
13 #include <dt-bindings/thermal/thermal.h>
15 #include "imx8mp-pinfunc.h"
[all …]
/linux/drivers/gpu/drm/amd/display/dc/dccg/dcn31/
H A Ddcn31_dccg.c35 (dccg_dcn->regs->reg)
39 dccg_dcn->dccg_shift->field_name, dccg_dcn->dccg_mask->field_name
42 dccg_dcn->base.ctx
44 dccg->ctx->logger
50 if (dccg->dpp_clock_gated[dpp_inst]) { in dccg31_update_dpp_dto()
58 if (dccg->ref_dppclk && req_dppclk) { in dccg31_update_dpp_dto()
59 int ref_dppclk = dccg->ref_dppclk; in dccg31_update_dpp_dto()
62 // phase / modulo = dpp pipe clk / dpp global clk in dccg31_update_dpp_dto()
64 phase = ((modulo * req_dppclk) + ref_dppclk - 1) / ref_dppclk; in dccg31_update_dpp_dto()
80 dccg->pipe_dppclk_khz[dpp_inst] = req_dppclk; in dccg31_update_dpp_dto()
[all …]
/linux/drivers/clk/
H A Dclk-versaclock3.c1 // SPDX-License-Identifier: GPL-2.0+
8 #include <linux/clk-provider.h>
88 #define VC3_DIV_MASK(width) ((1 << (width)) - 1)
131 VC3_SE1_MUX = VC3_SE1 - 1,
132 VC3_SE2_MUX = VC3_SE2 - 1,
133 VC3_SE3_MUX = VC3_SE3 - 1,
134 VC3_DIFF1_MUX = VC3_DIFF1 - 1,
135 VC3_DIFF2_MUX = VC3_DIFF2 - 1,
216 const struct vc3_clk_data *pfd_mux = vc3->data; in vc3_pfd_mux_get_parent()
217 u32 src; in vc3_pfd_mux_get_parent() local
[all …]
/linux/arch/arm64/boot/dts/exynos/
H A Dexynos850.dtsi1 // SPDX-License-Identifier: GPL-2.0
13 #include <dt-bindings/clock/exynos850.h>
14 #include <dt-bindings/interrupt-controller/arm-gic.h>
15 #include <dt-bindings/soc/samsung,exynos-usi.h>
20 #address-cells = <2>;
21 #size-cells = <1>;
23 interrupt-parent = <&gic>;
34 arm-pmu {
35 compatible = "arm,cortex-a55-pmu";
44 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>,
[all …]
/linux/drivers/gpu/drm/amd/display/dc/dce/
H A Ddce_clk_mgr.c2 * Copyright 2012-16 Advanced Micro Devices, Inc.
39 (clk_mgr_dce->regs->reg)
43 clk_mgr_dce->clk_mgr_shift->field_name, clk_mgr_dce->clk_mgr_mask->field_name
46 clk_mgr_dce->base.ctx
48 clk_mgr->ctx->logger
52 /* ClocksStateInvalid - should not be used */
54 /* ClocksStateUltraLow - not expected to be used for DCE 8.0 */
64 /*ClocksStateInvalid - should not be used*/
66 /*ClocksStateUltraLow - currently by HW design team not supposed to be used*/
76 /*ClocksStateInvalid - should not be used*/
[all …]
/linux/drivers/media/i2c/
H A Dtc358746.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * TC358746 - Parallel <-> CSI-2 Bridge
8 * - Currently only 'Parallel-in -> CSI-out' mode is supported!
12 #include <linux/clk.h>
13 #include <linux/clk-provider.h>
19 #include <linux/phy/phy-mipi-dphy.h>
24 #include <media/v4l2-ctrls.h>
25 #include <media/v4l2-device.h>
26 #include <media/v4l2-fwnode.h>
27 #include <media/v4l2-mc.h>
[all …]
/linux/drivers/comedi/drivers/
H A Dadv_pci1710.c1 // SPDX-License-Identifier: GPL-2.0
4 * Comedi driver for Advantech PCI-1710 series boards
13 * Description: Comedi driver for Advantech PCI-1710 series boards
14 * Devices: [Advantech] PCI-1710 (adv_pci1710), PCI-1710HG, PCI-1711,
15 * PCI-1713, PCI-1731
17 * Updated: Fri, 29 Oct 2015 17:19:35 -0700
26 * The PCI-1710 and PCI-1710HG have the same PCI device ID, so the
39 * PCI BAR2 Register map (dev->iobase)
57 #define PCI171X_CTRL_CNT0 BIT(6) /* 1=ext. clk, 0=int. 100kHz clk */
117 UNI_RANGE(5), /* internal -5V ref */
[all …]
/linux/arch/arm/boot/dts/samsung/
H A Dexynos3250.dtsi1 // SPDX-License-Identifier: GPL-2.0
17 #include "exynos4-cpu-thermal.dtsi"
18 #include <dt-bindings/clock/exynos3250.h>
19 #include <dt-bindings/interrupt-controller/arm-gic.h>
20 #include <dt-bindings/interrupt-controller/irq.h>
24 interrupt-parent = <&gic>;
25 #address-cells = <1>;
26 #size-cells = <1>;
46 bus_dmc: bus-dmc {
47 compatible = "samsung,exynos-bus";
[all …]
/linux/drivers/gpu/drm/amd/display/dc/bios/
H A Dbios_parser2.c2 * Copyright 2012-15 Advanced Micro Devices, Inc.
48 bp->base.ctx->logger
92 #define DATA_TABLES(table) (bp->master_data_tbl->listOfdatatables.table)
96 kfree(bp->base.bios_local_image); in bios_parser2_destruct()
97 kfree(bp->base.integrated_info); in bios_parser2_destruct()
123 tbl_revision->major = 0; in get_atom_data_table_revision()
124 tbl_revision->minor = 0; in get_atom_data_table_revision()
129 tbl_revision->major = in get_atom_data_table_revision()
130 (uint32_t) atom_data_tbl->format_revision & 0x3f; in get_atom_data_table_revision()
131 tbl_revision->minor = in get_atom_data_table_revision()
[all …]

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