Lines Matching +full:src +full:- +full:ref +full:- +full:clk +full:- +full:mhz
1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/media/nxp,imx8mq-mipi-csi2.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: NXP i.MX8MQ MIPI CSI-2 receiver
10 - Martin Kepplinger <martin.kepplinger@puri.sm>
12 description: |-
13 This binding covers the CSI-2 RX PHY and host controller included in the
20 - fsl,imx8mq-mipi-csi2
27 - description: core is the RX Controller Core Clock input. This clock
30 - description: esc is the Rx Escape Clock. This must be the same escape
32 - description: ui is the pixel clock (phy_ref up to 333Mhz).
35 clock-names:
37 - const: core
38 - const: esc
39 - const: ui
41 power-domains:
46 - description: CORE_RESET reset register bit definition
47 - description: PHY_REF_RESET reset register bit definition
48 - description: ESC_RESET reset register bit definition
50 fsl,mipi-phy-gpr:
52 The phandle to the imx8mq syscon iomux-gpr with the register
59 $ref: /schemas/types.yaml#/definitions/phandle-array
61 - items:
62 - description: The 'gpr' is the phandle to general purpose register node.
63 - description: The 'req_gpr' is the gpr register offset containing
70 interconnect-names:
74 $ref: /schemas/graph.yaml#/properties/ports
78 $ref: /schemas/graph.yaml#/$defs/port-base
81 Input port node, single endpoint describing the CSI-2 transmitter.
85 $ref: video-interfaces.yaml#
89 data-lanes:
92 - const: 1
93 - const: 2
94 - const: 3
95 - const: 4
98 - data-lanes
101 $ref: /schemas/graph.yaml#/properties/port
106 - port@0
107 - port@1
110 - compatible
111 - reg
112 - clocks
113 - clock-names
114 - power-domains
115 - resets
116 - fsl,mipi-phy-gpr
117 - ports
122 - |
123 #include <dt-bindings/clock/imx8mq-clock.h>
124 #include <dt-bindings/interconnect/imx8mq.h>
125 #include <dt-bindings/reset/imx8mq-reset.h>
128 compatible = "fsl,imx8mq-mipi-csi2";
130 clocks = <&clk IMX8MQ_CLK_CSI1_CORE>,
131 <&clk IMX8MQ_CLK_CSI1_ESC>,
132 <&clk IMX8MQ_CLK_CSI1_PHY_REF>;
133 clock-names = "core", "esc", "ui";
134 assigned-clocks = <&clk IMX8MQ_CLK_CSI1_CORE>,
135 <&clk IMX8MQ_CLK_CSI1_PHY_REF>,
136 <&clk IMX8MQ_CLK_CSI1_ESC>;
137 assigned-clock-rates = <266000000>, <200000000>, <66000000>;
138 assigned-clock-parents = <&clk IMX8MQ_SYS1_PLL_266M>,
139 <&clk IMX8MQ_SYS2_PLL_1000M>,
140 <&clk IMX8MQ_SYS1_PLL_800M>;
141 power-domains = <&pgc_mipi_csi1>;
142 resets = <&src IMX8MQ_RESET_MIPI_CSI1_CORE_RESET>,
143 <&src IMX8MQ_RESET_MIPI_CSI1_PHY_REF_RESET>,
144 <&src IMX8MQ_RESET_MIPI_CSI1_ESC_RESET>;
145 fsl,mipi-phy-gpr = <&iomuxc_gpr 0x88>;
147 interconnect-names = "dram";
150 #address-cells = <1>;
151 #size-cells = <0>;
157 remote-endpoint = <&imx477_out>;
158 data-lanes = <1 2 3 4>;
166 remote-endpoint = <&csi_in>;