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/freebsd/sys/contrib/device-tree/Bindings/phy/
H A Dphy-mtk-xsphy.txt1 MediaTek XS-PHY binding
2 --------------------------
4 The XS-PHY controller supports physical layer functionality for USB3.1
8 - compatible : should be "mediatek,<soc-model>-xsphy", "mediatek,xsphy",
9 soc-model is the name of SoC, such as mt3611 etc;
12 - "mediatek,mt3611-xsphy"
14 - #address-cells, #size-cells : should use the same values as the root node
15 - ranges: must be present
18 - reg : offset and length of register shared by multiple U3 ports,
21 - mediatek,src-ref-clk-mhz : u32, frequency of reference clock for slew rate
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H A Dmediatek,xsphy.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 ---
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: MediaTek XS-PHY Controller
11 - Chunfeng Yun <chunfeng.yun@mediatek.com>
14 The XS-PHY controller supports physical layer functionality for USB3.1
18 ----------------------------------
45 pattern: "^xs-phy@[0-9a-f]+$"
49 - enum:
50 - mediatek,mt3611-xsphy
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H A Dphy-mtk-tphy.txt1 MediaTek T-PHY binding
2 --------------------------
4 T-phy controller supports physical layer functionality for a number of
8 - compatible : should be one of
9 "mediatek,generic-tphy-v1"
10 "mediatek,generic-tphy-v2"
11 "mediatek,mt2701-u3phy" (deprecated)
12 "mediatek,mt2712-u3phy" (deprecated)
13 "mediatek,mt8173-u3phy";
14 make use of "mediatek,generic-tphy-v1" on mt2701 instead and
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H A Dmediatek,tphy.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 ---
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: MediaTek T-PHY Controller
11 - Chunfeng Yun <chunfeng.yun@mediatek.com>
14 The T-PHY controller supports physical layer functionality for a number of
17 Layout differences of banks between T-PHY V1 (mt8173/mt2701) and
18 T-PHY V2 (mt2712) / V3 (mt8195) when works on USB mode:
19 -----------------------------------
67 pattern: "^t-phy(@[0-9a-f]+)?$"
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/freebsd/contrib/ntp/util/
H A Dtg2.c6 * broadcast timecode. Alternatively, it can generate the IRIG-B
24 * over the range 0-255. The signal generator by default uses WWV
26 * switches to IRIG-B format.
42 * the transmissionorder is low-order first as the frame is processed
44 * For IRIG the on-time marker M preceeds the first (units) bit, so its
54 * v0.23 2007-02-12 dmw:
55 * - Changed statistics to include calculated error
60 * v0.22 2007-02-08 dmw:
61 * - Changed default for rate correction to "enabled", "-j" switch now disables.
62 * - Adjusted help message accordingly.
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/freebsd/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86InstrInfo.cpp1 //===-- X86InstrInfo.cpp - X86 Instruction Information --------------------===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
11 //===----------------------------------------------------------------------===//
52 #define DEBUG_TYPE "x86-instr-info"
58 NoFusing("disable-spill-fusing",
62 PrintFailedFusing("print-failed-fuse-candidates",
67 ReMatPICStubLoad("remat-pic-stub-load",
68 cl::desc("Re-materialize load from stub in PIC mode"),
71 PartialRegUpdateClearance("partial-reg-update-clearance",
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/freebsd/sys/contrib/dev/rtw88/
H A Dmain.h1 /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */
2 /* Copyright(c) 2018-2019 Realtek Corporation
50 #define RTW_TP_SHIFT 18 /* bytes/2s --> Mbps */
444 /* the power index is represented by differences, which cck-1s & ht40-1s are
813 /* SU-MIMO */
816 /* MU-MIMO */
1113 (*tbl->parse)(rtwdev, tbl); in rtw_load_table()
1505 bool wl_slot_toggle_change; /* if toggle to no-toggle */
1617 u32 coef[RTW_RF_PATH_MAX][20]; member
1956 * which might not re-use same format with array common.
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