Lines Matching +full:src +full:- +full:coef
1 //===-- X86InstrInfo.cpp - X86 Instruction Information --------------------===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
11 //===----------------------------------------------------------------------===//
52 #define DEBUG_TYPE "x86-instr-info"
58 NoFusing("disable-spill-fusing",
62 PrintFailedFusing("print-failed-fuse-candidates",
67 ReMatPICStubLoad("remat-pic-stub-load",
68 cl::desc("Re-materialize load from stub in PIC mode"),
71 PartialRegUpdateClearance("partial-reg-update-clearance",
77 "undef-reg-clearance",
98 // If the target does not have egpr, then r16-r31 will be resereved for all in getRegClass()
106 switch (RC->getID()) { in getRegClass()
136 // It's not always legal to reference the low 8-bit of the larger in isCoalescableExtInstr()
137 // register in 32-bit mode. in isCoalescableExtInstr()
178 // Some target-independent operations that trivially lower to data-invariant in isDataInvariant()
217 // Arithmetic with just 32-bit and 64-bit variants and no immediates. in isDataInvariant()
425 const MachineFunction *MF = MI.getParent()->getParent(); in getSPAdjust()
426 const TargetFrameLowering *TFI = MF->getSubtarget().getFrameLowering(); in getSPAdjust()
429 int SPAdj = alignTo(getFrameSize(MI), TFI->getStackAlign()); in getSPAdjust()
430 SPAdj -= getFrameAdjustment(MI); in getSPAdjust()
432 SPAdj = -SPAdj; in getSPAdjust()
442 for (auto E = MBB->end(); I != E; ++I) { in getSPAdjust()
443 if (I->getOpcode() == getCallFrameDestroyOpcode() || I->isCall()) in getSPAdjust()
449 if (I->getOpcode() != getCallFrameDestroyOpcode()) in getSPAdjust()
452 return -(I->getOperand(1).getImm()); in getSPAdjust()
711 // Check for post-frame index elimination operations in isLoadFromStackSlotPostFE()
715 cast<FixedStackPseudoSourceValue>(Accesses.front()->getPseudoValue()) in isLoadFromStackSlotPostFE()
716 ->getFrameIndex(); in isLoadFromStackSlotPostFE()
746 // Check for post-frame index elimination operations in isStoreToStackSlotPostFE()
750 cast<FixedStackPseudoSourceValue>(Accesses.front()->getPseudoValue()) in isStoreToStackSlotPostFE()
751 ->getFrameIndex(); in isStoreToStackSlotPostFE()
760 // Don't waste compile time scanning use-def chains of physregs. in regIsPICBase()
865 // AVX-512 in isReallyTriviallyReMaterializable()
937 // Allow re-materialization of PIC load. in isReallyTriviallyReMaterializable()
939 const MachineFunction &MF = *MI.getParent()->getParent(); in isReallyTriviallyReMaterializable()
960 // Allow re-materialization of lea PICBase + x. in isReallyTriviallyReMaterializable()
961 const MachineFunction &MF = *MI.getParent()->getParent(); in isReallyTriviallyReMaterializable()
980 // The instruction clobbers EFLAGS. Re-materialize as MOV32ri to avoid side in reMaterialize()
991 Value = -1; in reMaterialize()
1002 MachineInstr *MI = MBB.getParent()->CloneMachineInstr(&Orig); in reMaterialize()
1021 /// Check whether the shift count for a machine operand is non-zero.
1033 // Left shift instructions can be transformed into load-effective-address in isTruncatedShiftCountForLEA()
1066 (MRI->getVRegDef(CmpInstr.getOperand(0).getReg()) == &CmpValDefInstr) && in findRedundantFlagInstr()
1073 VregDefInstr = MRI->getVRegDef(CmpValDefInstr.getOperand(1).getReg()); in findRedundantFlagInstr()
1079 if (!((VregDefInstr->getOpcode() == X86::AND32ri || in findRedundantFlagInstr()
1080 VregDefInstr->getOpcode() == X86::AND64ri32) && in findRedundantFlagInstr()
1081 isUInt<16>(VregDefInstr->getOperand(2).getImm()))) in findRedundantFlagInstr()
1096 VregDefInstr = MRI->getVRegDef(CmpValDefInstr.getOperand(2).getReg()); in findRedundantFlagInstr()
1104 // FIXME: If `VregDefInstr->getParent()` is the only predecessor of in findRedundantFlagInstr()
1106 if (VregDefInstr->getParent() != CmpValDefInstr.getParent()) in findRedundantFlagInstr()
1109 if (X86::isAND(VregDefInstr->getOpcode())) { in findRedundantFlagInstr()
1114 // test64rr %extended_reg, %extended_reg, implicit-def $eflags in findRedundantFlagInstr()
1119 // test16rr %src_reg, %src_reg, implicit-def $eflags in findRedundantFlagInstr()
1160 bool X86InstrInfo::classifyLEAReg(MachineInstr &MI, const MachineOperand &Src, in classifyLEAReg() argument
1164 MachineFunction &MF = *MI.getParent()->getParent(); in classifyLEAReg()
1171 Register SrcReg = Src.getReg(); in classifyLEAReg()
1175 // type (32-bit or 64-bit) we may just need to forbid SP. in classifyLEAReg()
1178 assert(!Src.isUndef() && "Undef op doesn't need optimization"); in classifyLEAReg()
1186 // This is for an LEA64_32r and incoming registers are 32-bit. One way or in classifyLEAReg()
1187 // another we need to add 64-bit registers to the final MI. in classifyLEAReg()
1189 ImplicitOp = Src; in classifyLEAReg()
1194 assert(!Src.isUndef() && "Undef op doesn't need optimization"); in classifyLEAReg()
1196 // Virtual register of the wrong class, we have to create a temporary 64-bit in classifyLEAReg()
1208 LV->replaceKillInstruction(SrcReg, MI, *Copy); in classifyLEAReg()
1211 SlotIndex CopyIdx = LIS->InsertMachineInstrInMaps(*Copy); in classifyLEAReg()
1212 SlotIndex Idx = LIS->getInstructionIndex(MI); in classifyLEAReg()
1213 LiveInterval &LI = LIS->getInterval(SrcReg); in classifyLEAReg()
1215 if (S->end.getBaseIndex() == Idx) in classifyLEAReg()
1216 S->end = CopyIdx.getRegSlot(); in classifyLEAReg()
1229 // We handle 8-bit adds and various 16-bit opcodes in the switch below. in convertToThreeAddressWithLEA()
1231 MachineRegisterInfo &RegInfo = MBB.getParent()->getRegInfo(); in convertToThreeAddressWithLEA()
1233 RegInfo.getTargetRegisterInfo()->getRegSizeInBits( in convertToThreeAddressWithLEA()
1237 // TODO: For a 32-bit target, we need to adjust the LEA variables with in convertToThreeAddressWithLEA()
1253 // we will be shifting and then extracting the lower 8/16-bits. in convertToThreeAddressWithLEA()
1256 // leal -65(%rdx), %esi in convertToThreeAddressWithLEA()
1257 // But testing has shown this *does* help performance in 64-bit mode (at in convertToThreeAddressWithLEA()
1261 Register Src = MI.getOperand(1).getReg(); in convertToThreeAddressWithLEA() local
1272 .addReg(Src, getKillRegState(IsKill)); in convertToThreeAddressWithLEA()
1297 addRegOffset(MIB, InRegLEA, true, -1); in convertToThreeAddressWithLEA()
1312 if (Src == Src2) { in convertToThreeAddressWithLEA()
1322 // we will be shifting and then extracting the lower 8/16-bits. in convertToThreeAddressWithLEA()
1331 LV->replaceKillInstruction(Src2, MI, *InsMI2); in convertToThreeAddressWithLEA()
1344 LV->getVarInfo(InRegLEA).Kills.push_back(NewMI); in convertToThreeAddressWithLEA()
1346 LV->getVarInfo(InRegLEA2).Kills.push_back(NewMI); in convertToThreeAddressWithLEA()
1347 LV->getVarInfo(OutRegLEA).Kills.push_back(ExtMI); in convertToThreeAddressWithLEA()
1349 LV->replaceKillInstruction(Src, MI, *InsMI); in convertToThreeAddressWithLEA()
1351 LV->replaceKillInstruction(Dest, MI, *ExtMI); in convertToThreeAddressWithLEA()
1355 LIS->InsertMachineInstrInMaps(*ImpDef); in convertToThreeAddressWithLEA()
1356 SlotIndex InsIdx = LIS->InsertMachineInstrInMaps(*InsMI); in convertToThreeAddressWithLEA()
1358 LIS->InsertMachineInstrInMaps(*ImpDef2); in convertToThreeAddressWithLEA()
1361 Ins2Idx = LIS->InsertMachineInstrInMaps(*InsMI2); in convertToThreeAddressWithLEA()
1362 SlotIndex NewIdx = LIS->ReplaceMachineInstrInMaps(MI, *NewMI); in convertToThreeAddressWithLEA()
1363 SlotIndex ExtIdx = LIS->InsertMachineInstrInMaps(*ExtMI); in convertToThreeAddressWithLEA()
1364 LIS->getInterval(InRegLEA); in convertToThreeAddressWithLEA()
1365 LIS->getInterval(OutRegLEA); in convertToThreeAddressWithLEA()
1367 LIS->getInterval(InRegLEA2); in convertToThreeAddressWithLEA()
1369 // Move the use of Src up to InsMI. in convertToThreeAddressWithLEA()
1370 LiveInterval &SrcLI = LIS->getInterval(Src); in convertToThreeAddressWithLEA()
1372 if (SrcSeg->end == NewIdx.getRegSlot()) in convertToThreeAddressWithLEA()
1373 SrcSeg->end = InsIdx.getRegSlot(); in convertToThreeAddressWithLEA()
1377 LiveInterval &Src2LI = LIS->getInterval(Src2); in convertToThreeAddressWithLEA()
1379 if (Src2Seg->end == NewIdx.getRegSlot()) in convertToThreeAddressWithLEA()
1380 Src2Seg->end = Ins2Idx.getRegSlot(); in convertToThreeAddressWithLEA()
1384 LiveInterval &DestLI = LIS->getInterval(Dest); in convertToThreeAddressWithLEA()
1387 assert(DestSeg->start == NewIdx.getRegSlot() && in convertToThreeAddressWithLEA()
1388 DestSeg->valno->def == NewIdx.getRegSlot()); in convertToThreeAddressWithLEA()
1389 DestSeg->start = ExtIdx.getRegSlot(); in convertToThreeAddressWithLEA()
1390 DestSeg->valno->def = ExtIdx.getRegSlot(); in convertToThreeAddressWithLEA()
1398 /// may be able to convert a two-address instruction into a true
1399 /// three-address instruction on demand. This allows the X86 target (for
1401 /// would require register copies due to two-addressness.
1415 MachineFunction &MF = *MI.getParent()->getParent(); in convertToThreeAddress()
1416 // All instructions input are two-addr instructions. Get the known operands. in convertToThreeAddress()
1418 const MachineOperand &Src = MI.getOperand(1); in convertToThreeAddress() local
1424 if (Src.isUndef()) in convertToThreeAddress()
1447 if (Src.getReg().isVirtual() && !MF.getRegInfo().constrainRegClass( in convertToThreeAddress()
1448 Src.getReg(), &X86::GR64_NOSPRegClass)) in convertToThreeAddress()
1455 .add(Src) in convertToThreeAddress()
1471 if (!classifyLEAReg(MI, Src, Opc, /*AllowSP=*/false, SrcReg, isKill, in convertToThreeAddress()
1487 if (LV && SrcReg != Src.getReg()) in convertToThreeAddress()
1488 LV->getVarInfo(SrcReg).Kills.push_back(NewMI); in convertToThreeAddress()
1509 if (!classifyLEAReg(MI, Src, Opc, /*AllowSP=*/false, SrcReg, isKill, in convertToThreeAddress()
1522 if (LV && SrcReg != Src.getReg()) in convertToThreeAddress()
1523 LV->getVarInfo(SrcReg).Kills.push_back(NewMI); in convertToThreeAddress()
1535 if (!classifyLEAReg(MI, Src, Opc, /*AllowSP=*/false, SrcReg, isKill, in convertToThreeAddress()
1545 NewMI = addOffset(MIB, -1); in convertToThreeAddress()
1548 if (LV && SrcReg != Src.getReg()) in convertToThreeAddress()
1549 LV->getVarInfo(SrcReg).Kills.push_back(NewMI); in convertToThreeAddress()
1579 if (Src.getReg() == Src2.getReg()) { in convertToThreeAddress()
1585 if (!classifyLEAReg(MI, Src, Opc, /*AllowSP=*/true, SrcReg, isKill, in convertToThreeAddress()
1601 LV->getVarInfo(SrcReg2).Kills.push_back(NewMI); in convertToThreeAddress()
1602 if (SrcReg != SrcReg2 && SrcReg != Src.getReg()) in convertToThreeAddress()
1603 LV->getVarInfo(SrcReg).Kills.push_back(NewMI); in convertToThreeAddress()
1619 BuildMI(MF, MI.getDebugLoc(), get(X86::LEA64r)).add(Dest).add(Src), in convertToThreeAddress()
1629 if (!classifyLEAReg(MI, Src, Opc, /*AllowSP=*/true, SrcReg, isKill, in convertToThreeAddress()
1642 if (LV && SrcReg != Src.getReg()) in convertToThreeAddress()
1643 LV->getVarInfo(SrcReg).Kills.push_back(NewMI); in convertToThreeAddress()
1661 if (!isInt<32>(-Imm)) in convertToThreeAddress()
1669 if (!classifyLEAReg(MI, Src, Opc, /*AllowSP=*/true, SrcReg, isKill, in convertToThreeAddress()
1679 NewMI = addOffset(MIB, -Imm); in convertToThreeAddress()
1682 if (LV && SrcReg != Src.getReg()) in convertToThreeAddress()
1683 LV->getVarInfo(SrcReg).Kills.push_back(NewMI); in convertToThreeAddress()
1691 if (!isInt<32>(-Imm)) in convertToThreeAddress()
1697 BuildMI(MF, MI.getDebugLoc(), get(X86::LEA64r)).add(Dest).add(Src); in convertToThreeAddress()
1698 NewMI = addOffset(MIB, -Imm); in convertToThreeAddress()
1875 .add(Src) in convertToThreeAddress()
2014 .add(Src) in convertToThreeAddress()
2028 LV->replaceKillInstruction(Op.getReg(), MI, *NewMI); in convertToThreeAddress()
2036 LIS->ReplaceMachineInstrInMaps(MI, *NewMI); in convertToThreeAddress()
2038 LIS->getInterval(SrcReg); in convertToThreeAddress()
2040 LIS->getInterval(SrcReg2); in convertToThreeAddress()
2048 /// All prevents commuting a passthru operand. Returns -1 if the commute isn't
2050 /// Case 0 - Possible to commute the first and second operands.
2051 /// Case 1 - Possible to commute the first and third operands.
2052 /// Case 2 - Possible to commute the second and third operands.
2071 llvm_unreachable("Unknown three src commute case."); in getThreeSrcCommuteCase()
2144 uint8_t Imm = MI.getOperand(MI.getNumOperands() - 1).getImm(); in commuteVPTERNLOG()
2157 MI.getOperand(MI.getNumOperands() - 1).setImm(NewImm); in commuteVPTERNLOG()
2288 ? MI.getParent()->getParent()->CloneMachineInstr(&MI) in commuteInstructionImpl()
2299 // SHLD B, C, I <-> SHRD C, B, (BitWidth - I) in commuteInstructionImpl()
2334 WorkingMI->setDesc(get(Opc)); in commuteInstructionImpl()
2335 WorkingMI->getOperand(3).setImm(Size - MI.getOperand(3).getImm()); in commuteInstructionImpl()
2340 // PFSUB x, y: x = x - y in commuteInstructionImpl()
2341 // PFSUBR x, y: x = y - x in commuteInstructionImpl()
2343 WorkingMI->setDesc( in commuteInstructionImpl()
2351 if (MI.getParent()->getParent()->getFunction().hasOptSize()) { in commuteInstructionImpl()
2367 WorkingMI->setDesc(get(Opc)); in commuteInstructionImpl()
2368 WorkingMI->removeOperand(3); in commuteInstructionImpl()
2424 WorkingMI->getOperand(3).setImm(Mask ^ Imm); in commuteInstructionImpl()
2430 unsigned Imm = MI.getOperand(MI.getNumOperands() - 1).getImm(); in commuteInstructionImpl()
2443 WorkingMI->getOperand(MI.getNumOperands() - 1).setImm(AltImm); in commuteInstructionImpl()
2477 WorkingMI->setDesc(get(Opc)); in commuteInstructionImpl()
2478 WorkingMI->addOperand(MachineOperand::CreateImm(Mask)); in commuteInstructionImpl()
2483 WorkingMI->setDesc(get(X86::SHUFPDrri)); in commuteInstructionImpl()
2484 WorkingMI->addOperand(MachineOperand::CreateImm(0x02)); in commuteInstructionImpl()
2491 WorkingMI->setDesc(get(X86::MOVSDrr)); in commuteInstructionImpl()
2492 WorkingMI->removeOperand(3); in commuteInstructionImpl()
2507 WorkingMI->getOperand(3).setImm((Src1Hi << 4) | (Src2Hi >> 4)); in commuteInstructionImpl()
2560 WorkingMI->getOperand(MI.getNumOperands() - 1) in commuteInstructionImpl()
2562 MI.getOperand(MI.getNumOperands() - 1).getImm() & 0x7)); in commuteInstructionImpl()
2574 WorkingMI->getOperand(3).setImm( in commuteInstructionImpl()
2596 WorkingMI->getOperand(MI.getNumExplicitOperands() - 1) in commuteInstructionImpl()
2598 MI.getOperand(MI.getNumExplicitOperands() - 1).getImm() & 0x1f)); in commuteInstructionImpl()
2606 WorkingMI->getOperand(3).setImm((MI.getOperand(3).getImm() & 0xFF) ^ 0x22); in commuteInstructionImpl()
2639 WorkingMI->setDesc(get(Opc)); in commuteInstructionImpl()
2645 unsigned OpNo = MI.getDesc().getNumOperands() - 1; in commuteInstructionImpl()
2647 WorkingMI->getOperand(OpNo).setImm(X86::GetOppositeBranchCondition(CC)); in commuteInstructionImpl()
2699 WorkingMI->setDesc(get(getCommutedVPERMV3Opcode(Opc))); in commuteInstructionImpl()
2705 WorkingMI->setDesc( in commuteInstructionImpl()
2721 unsigned KMaskOp = -1U; in findThreeSrcCommutedOpIndices()
2723 // For k-zero-masked operations it is Ok to commute the first vector in findThreeSrcCommutedOpIndices()
2725 // For regular k-masked operations a conservative choice is done as the in findThreeSrcCommutedOpIndices()
2727 // in the k-mask operand is set to 0, are copied to the result of the in findThreeSrcCommutedOpIndices()
2730 // k-mask operand is set to either all ones or all zeroes. in findThreeSrcCommutedOpIndices()
2732 // the elements enabled by the k-mask operand. For example, in findThreeSrcCommutedOpIndices()
2735 // VMOVAPSZmrk <mem_addr>, k, v4; // this is the ONLY user of v4 -> in findThreeSrcCommutedOpIndices()
2738 // The k-mask operand has index = 2 for masked and zero-masked operations. in findThreeSrcCommutedOpIndices()
2742 // which the corresponding bit in the k-mask is set to 0. in findThreeSrcCommutedOpIndices()
2754 LastCommutableVecOp--; in findThreeSrcCommutedOpIndices()
2790 CommutableOpIdx1 >= FirstCommutableVecOp; CommutableOpIdx1--) { in findThreeSrcCommutedOpIndices()
2791 // Just ignore and skip the k-mask operand. in findThreeSrcCommutedOpIndices()
3029 FMA3Group->isIntrinsic()); in findCommutedOpIndices()
3040 MCOI::TIED_TO) != -1)) { in findCommutedOpIndices()
3043 // be a 3 input instruction and we want the first two non-mask inputs. in findCommutedOpIndices()
3050 --CommutableOpIdx1; in findCommutedOpIndices()
3071 unsigned Opcode = MI->getOpcode(); in isConvertibleLEA()
3076 const MachineOperand &Scale = MI->getOperand(1 + X86::AddrScaleAmt); in isConvertibleLEA()
3077 const MachineOperand &Disp = MI->getOperand(1 + X86::AddrDisp); in isConvertibleLEA()
3078 const MachineOperand &Segment = MI->getOperand(1 + X86::AddrSegmentReg); in isConvertibleLEA()
3099 const MachineRegisterInfo &MRI = MI.getParent()->getParent()->getRegInfo(); in hasCommutePreference()
3105 if (isConvertibleLEA(Inst) && Inst->getParent() == MI.getParent()) { in hasCommutePreference()
3113 if (isConvertibleLEA(Inst) && Inst->getParent() == MI.getParent()) { in hasCommutePreference()
3127 return -1; in getCondSrcNoFromDesc()
3129 unsigned NumUses = MCID.getNumOperands() - MCID.getNumDefs(); in getCondSrcNoFromDesc()
3130 return NumUses - 1; in getCondSrcNoFromDesc()
3170 // - SCC: source conditonal code (same as CMOV) in getCCMPCondFlagsFromCondCode()
3171 // - DCF: destination conditional flags, which has 4 valid bits in getCCMPCondFlagsFromCondCode()
3173 // +----+----+----+----+ in getCCMPCondFlagsFromCondCode()
3175 // +----+----+----+----+ in getCCMPCondFlagsFromCondCode()
3232 return (I == Table.end() || I->OldOpc != Opc) ? 0U : I->NewOpc; in getNewOpcFromTable()
3323 // Floating-point Predicates in getX86ConditionCode()
3452 break; // LT -> NLE in getSwappedVPCMPImm()
3455 break; // LE -> NLT in getSwappedVPCMPImm()
3458 break; // NLT -> LE in getSwappedVPCMPImm()
3461 break; // NLE -> LT in getSwappedVPCMPImm()
3479 break; // LT -> GT in getSwappedVPCOMImm()
3482 break; // LE -> GE in getSwappedVPCOMImm()
3485 break; // GT -> LT in getSwappedVPCOMImm()
3488 break; // GE -> LE in getSwappedVPCOMImm()
3560 // Directly invoke the MC-layer routine for real (i.e., non-pseudo) in getFirstAddrOperandIdx()
3570 return -1; in getFirstAddrOperandIdx()
3582 return -1; in getFirstAddrOperandIdx()
3586 // reference. We expect the following AddrNumOperand-1 operands to also have in getFirstAddrOperandIdx()
3588 for (unsigned I = 0, E = NumOps - X86::AddrNumOperands; I != E; ++I) { in getFirstAddrOperandIdx()
3601 return -1; in getFirstAddrOperandIdx()
3618 MI.getParent()->getParent()->getConstantPool()->getConstants(); in getConstantFromPool()
3649 if (MF->getTarget().getCodeModel() == CodeModel::Kernel) { in canMakeTailCallConditional()
3666 if (Subtarget.isTargetWin64() && MF->hasWinCFI()) { in canMakeTailCallConditional()
3677 const X86MachineFunctionInfo *X86FI = MF->getInfo<X86MachineFunctionInfo>(); in canMakeTailCallConditional()
3678 if (X86FI->getTCReturnAddrDelta() != 0 || in canMakeTailCallConditional()
3694 --I; in replaceBranchWithTailCall()
3695 if (I->isDebugInstr()) in replaceBranchWithTailCall()
3697 if (!I->isBranch()) in replaceBranchWithTailCall()
3712 MIB->addOperand(TailCall.getOperand(0)); // Destination. in replaceBranchWithTailCall()
3714 MIB->addOperand(BranchCond[0]); // Condition. in replaceBranchWithTailCall()
3715 MIB.copyImplicitOps(TailCall); // Regmask and (imp-used) parameters. in replaceBranchWithTailCall()
3728 I->eraseFromParent(); in replaceBranchWithTailCall()
3736 // Look for non-EHPad successors other than TBB. If we find exactly one, it in getFallThroughMBB()
3741 for (MachineBasicBlock *Succ : MBB->successors()) { in getFallThroughMBB()
3742 if (Succ->isEHPad() || (Succ == TBB && FallthroughBB)) in getFallThroughMBB()
3762 --I; in analyzeBranchImpl()
3763 if (I->isDebugInstr()) in analyzeBranchImpl()
3766 // Working from the bottom, when we see a non-terminator instruction, we're in analyzeBranchImpl()
3773 if (!I->isBranch()) in analyzeBranchImpl()
3777 if (I->getOpcode() == X86::JMP_1) { in analyzeBranchImpl()
3781 TBB = I->getOperand(0).getMBB(); in analyzeBranchImpl()
3791 // Delete the JMP if it's equivalent to a fall-through. in analyzeBranchImpl()
3792 if (MBB.isLayoutSuccessor(I->getOperand(0).getMBB())) { in analyzeBranchImpl()
3794 I->eraseFromParent(); in analyzeBranchImpl()
3801 TBB = I->getOperand(0).getMBB(); in analyzeBranchImpl()
3812 if (I->findRegisterUseOperand(X86::EFLAGS, /*TRI=*/nullptr)->isUndef()) in analyzeBranchImpl()
3818 TBB = I->getOperand(0).getMBB(); in analyzeBranchImpl()
3826 // opcodes fit one of the special multi-branch idioms. in analyzeBranchImpl()
3832 auto NewTBB = I->getOperand(0).getMBB(); in analyzeBranchImpl()
3896 return -1; in getJumpTableIndexFromAddr()
3904 return -1; in getJumpTableIndexFromReg()
3907 return -1; in getJumpTableIndexFromReg()
3908 unsigned Opcode = MI->getOpcode(); in getJumpTableIndexFromReg()
3910 return -1; in getJumpTableIndexFromReg()
3916 // Switch-jump pattern for non-PIC code looks like: in getJumpTableIndex()
3917 // JMP64m $noreg, 8, %X, %jump-table.X, $noreg in getJumpTableIndex()
3922 // %0 = LEA64r $rip, 1, $noreg, %jump-table.X in getJumpTableIndex()
3929 return -1; in getJumpTableIndex()
3930 const MachineFunction &MF = *MI.getParent()->getParent(); in getJumpTableIndex()
3934 return -1; in getJumpTableIndex()
3935 if (Add->getOpcode() != X86::ADD64rr && Add->getOpcode() != X86::ADD32rr) in getJumpTableIndex()
3936 return -1; in getJumpTableIndex()
3937 int JTI1 = getJumpTableIndexFromReg(MRI, Add->getOperand(1).getReg()); in getJumpTableIndex()
3940 int JTI2 = getJumpTableIndexFromReg(MRI, Add->getOperand(2).getReg()); in getJumpTableIndex()
3944 return -1; in getJumpTableIndex()
3986 if (Succ->isLiveIn(X86::EFLAGS)) in analyzeBranchPredicate()
4001 if (ConditionDef->getOpcode() == TestOpcode && in analyzeBranchPredicate()
4002 ConditionDef->getNumOperands() == 3 && in analyzeBranchPredicate()
4003 ConditionDef->getOperand(0).isIdenticalTo(ConditionDef->getOperand(1)) && in analyzeBranchPredicate()
4005 MBP.LHS = ConditionDef->getOperand(0); in analyzeBranchPredicate()
4024 --I; in removeBranch()
4025 if (I->isDebugInstr()) in removeBranch()
4027 if (I->getOpcode() != X86::JMP_1 && in removeBranch()
4031 I->eraseFromParent(); in removeBranch()
4057 // If FBB is null, it is implied to be a fall-through block. in insertBranch()
4076 "body is a fall-through."); in insertBranch()
4090 // Two-way Conditional branch. Insert the second branch. in insertBranch()
4112 const MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo(); in canInsertSelect()
4139 MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo(); in insertSelect()
4164 // SrcReg(MaskReg) -> DestReg(GR64) in CopyToFromAsymmetricReg()
4165 // SrcReg(MaskReg) -> DestReg(GR32) in CopyToFromAsymmetricReg()
4179 // SrcReg(GR64) -> DestReg(MaskReg) in CopyToFromAsymmetricReg()
4180 // SrcReg(GR32) -> DestReg(MaskReg) in CopyToFromAsymmetricReg()
4194 // SrcReg(VR128) -> DestReg(GR64) in CopyToFromAsymmetricReg()
4195 // SrcReg(VR64) -> DestReg(GR64) in CopyToFromAsymmetricReg()
4196 // SrcReg(GR64) -> DestReg(VR128) in CopyToFromAsymmetricReg()
4197 // SrcReg(GR64) -> DestReg(VR64) in CopyToFromAsymmetricReg()
4219 // SrcReg(VR128) -> DestReg(GR32) in CopyToFromAsymmetricReg()
4220 // SrcReg(GR32) -> DestReg(VR128) in CopyToFromAsymmetricReg()
4254 // Copying to or from a physical H register on x86-64 requires a NOREX in copyPhysReg()
4260 "8-bit H register can not be copied outside GR8_NOREX"); in copyPhysReg()
4272 // 512-bit move. in copyPhysReg()
4276 TRI->getMatchingSuperReg(DestReg, X86::sub_xmm, &X86::VR512RegClass); in copyPhysReg()
4278 TRI->getMatchingSuperReg(SrcReg, X86::sub_xmm, &X86::VR512RegClass); in copyPhysReg()
4287 // 512-bit move. in copyPhysReg()
4291 TRI->getMatchingSuperReg(DestReg, X86::sub_ymm, &X86::VR512RegClass); in copyPhysReg()
4293 TRI->getMatchingSuperReg(SrcReg, X86::sub_ymm, &X86::VR512RegClass); in copyPhysReg()
4361 switch (STI.getRegisterInfo()->getSpillSize(*RC)) { in getLoadStoreRegOpcode()
4365 assert(X86::GR8RegClass.hasSubClassEq(RC) && "Unknown 1-byte regclass"); in getLoadStoreRegOpcode()
4367 // Copying to or from a physical H register on x86-64 requires a NOREX in getLoadStoreRegOpcode()
4376 assert(X86::GR16RegClass.hasSubClassEq(RC) && "Unknown 2-byte regclass"); in getLoadStoreRegOpcode()
4406 llvm_unreachable("Unknown 4-byte regclass"); in getLoadStoreRegOpcode()
4426 llvm_unreachable("Unknown 8-byte regclass"); in getLoadStoreRegOpcode()
4428 assert(X86::RFP80RegClass.hasSubClassEq(RC) && "Unknown 10-byte regclass"); in getLoadStoreRegOpcode()
4452 llvm_unreachable("Unknown 16-byte regclass"); in getLoadStoreRegOpcode()
4455 assert(X86::VR256XRegClass.hasSubClassEq(RC) && "Unknown 32-byte regclass"); in getLoadStoreRegOpcode()
4472 assert(X86::VR512RegClass.hasSubClassEq(RC) && "Unknown 64-byte regclass"); in getLoadStoreRegOpcode()
4473 assert(STI.hasAVX512() && "Using 512-bit register requires AVX512"); in getLoadStoreRegOpcode()
4479 assert(X86::TILERegClass.hasSubClassEq(RC) && "Unknown 1024-byte regclass"); in getLoadStoreRegOpcode()
4480 assert(STI.hasAMXTILE() && "Using 8*1024-bit register requires AMX-TILE"); in getLoadStoreRegOpcode()
4536 ErrInfo = "Displacement in address must fit into 32-bit signed " in verifyInstruction()
4550 // Follow use-def for SUBREG_TO_REG to find the real move immediate in getConstValDefinedInReg()
4551 // instruction. It is quite common for x86-64. in getConstValDefinedInReg()
4554 // %8:gr32 = MOV32r0 implicit-def dead $eflags in getConstValDefinedInReg()
4563 const MachineRegisterInfo &MRI = MI.getParent()->getParent()->getRegInfo(); in getConstValDefinedInReg()
4569 if (MovMI->getOpcode() == X86::MOV32r0 && in getConstValDefinedInReg()
4570 MovMI->getOperand(0).getReg() == MovReg) { in getConstValDefinedInReg()
4575 if (MovMI->getOpcode() != X86::MOV32ri && in getConstValDefinedInReg()
4576 MovMI->getOpcode() != X86::MOV64ri && in getConstValDefinedInReg()
4577 MovMI->getOpcode() != X86::MOV32ri64 && MovMI->getOpcode() != X86::MOV8ri) in getConstValDefinedInReg()
4579 // Mov Src can be a global address. in getConstValDefinedInReg()
4580 if (!MovMI->getOperand(1).isImm() || MovMI->getOperand(0).getReg() != MovReg) in getConstValDefinedInReg()
4582 ImmVal = MovMI->getOperand(1).getImm(); in getConstValDefinedInReg()
4589 if (!MI->modifiesRegister(NullValueReg, TRI)) in preservesZeroValueInReg()
4591 switch (MI->getOpcode()) { in preservesZeroValueInReg()
4598 assert(MI->getOperand(0).isDef() && MI->getOperand(1).isUse() && in preservesZeroValueInReg()
4600 return MI->getOperand(0).getReg() == NullValueReg && in preservesZeroValueInReg()
4601 MI->getOperand(1).getReg() == NullValueReg; in preservesZeroValueInReg()
4602 // Zero extend of a sub-reg of NullValueReg into itself does not change the in preservesZeroValueInReg()
4605 return llvm::all_of(MI->operands(), [&](const MachineOperand &MO) { in preservesZeroValueInReg()
4606 return TRI->isSubRegisterEq(NullValueReg, MO.getReg()); in preservesZeroValueInReg()
4627 if (!BaseOp->isReg()) // Can be an MO_FrameIndex in getMemOperandsWithOffsetWidth()
4645 if (!BaseOp->isReg()) in getMemOperandsWithOffsetWidth()
4651 // there is no use of `Width` for X86 back-end at the moment. in getMemOperandsWithOffsetWidth()
4653 !MemOp.memoperands_empty() ? MemOp.memoperands().front()->getSize() : 0; in getMemOperandsWithOffsetWidth()
4693 MachineRegisterInfo &RegInfo = MBB.getParent()->getRegInfo(); in loadStoreTileReg()
4699 MachineOperand &MO = NewMI->getOperand(X86::AddrIndexReg); in loadStoreTileReg()
4707 MachineRegisterInfo &RegInfo = MBB.getParent()->getRegInfo(); in loadStoreTileReg()
4712 MachineOperand &MO = NewMI->getOperand(1 + X86::AddrIndexReg); in loadStoreTileReg()
4726 assert(MFI.getObjectSize(FrameIdx) >= TRI->getSpillSize(*RC) && in storeRegToStackSlot()
4729 unsigned Alignment = std::max<uint32_t>(TRI->getSpillSize(*RC), 16); in storeRegToStackSlot()
4731 (Subtarget.getFrameLowering()->getStackAlign() >= Alignment) || in storeRegToStackSlot()
4750 assert(MFI.getObjectSize(FrameIdx) >= TRI->getSpillSize(*RC) && in loadRegFromStackSlot()
4752 unsigned Alignment = std::max<uint32_t>(TRI->getSpillSize(*RC), 16); in loadRegFromStackSlot()
4754 (Subtarget.getFrameLowering()->getStackAlign() >= Alignment) || in loadRegFromStackSlot()
4895 static_cast<uint64_t>(OIValue) - 1) { in isRedundantFlagInstr()
4896 *ImmDelta = -1; in isRedundantFlagInstr()
4921 // "ELF Handling for Thread-Local Storage" specifies that x86-64 GOTTPOFF, and in isDefConvertible()
4936 // The shift instructions only modify ZF if their shift count is non-zero. in isDefConvertible()
5223 if (!MRI->use_nodbg_empty(CmpInstr.getOperand(0).getReg())) in optimizeCompareInstr()
5258 // The following code tries to remove the comparison by re-using EFLAGS in optimizeCompareInstr()
5266 MachineInstr *SrcRegDef = MRI->getVRegDef(SrcReg); in optimizeCompareInstr()
5285 for (MachineInstr &Inst : make_range(From, MBB->rend())) { in optimizeCompareInstr()
5289 // testl %eax, %eax // <-- can be removed in optimizeCompareInstr()
5304 // test16rr %src_reg, %src_reg, implicit-def $eflags in optimizeCompareInstr()
5309 // test64rr %src_reg, %src_reg, implicit-def $eflags in optimizeCompareInstr()
5314 assert(AndInstr != nullptr && X86::isAND(AndInstr->getOpcode())); in optimizeCompareInstr()
5329 // testl %eax, %eax // <-- can be removed in optimizeCompareInstr()
5344 // cmp x, y // <-- can be removed in optimizeCompareInstr()
5370 if (MBB->pred_size() != 1) in optimizeCompareInstr()
5372 MBB = *MBB->pred_begin(); in optimizeCompareInstr()
5373 From = MBB->rbegin(); in optimizeCompareInstr()
5379 // live-out. in optimizeCompareInstr()
5458 unsigned BitWidth = TRI->getRegSizeInBits(*MRI->getRegClass(SrcReg)); in optimizeCompareInstr()
5462 case X86::COND_L: // x <s (C + 1) --> x <=s C in optimizeCompareInstr()
5467 case X86::COND_B: // x <u (C + 1) --> x <=u C in optimizeCompareInstr()
5472 case X86::COND_GE: // x >=s (C + 1) --> x >s C in optimizeCompareInstr()
5477 case X86::COND_AE: // x >=u (C + 1) --> x >u C in optimizeCompareInstr()
5482 case X86::COND_G: // x >s (C - 1) --> x >=s C in optimizeCompareInstr()
5483 if (ImmDelta != -1 || APInt::getSignedMaxValue(BitWidth) == CmpValue) in optimizeCompareInstr()
5487 case X86::COND_A: // x >u (C - 1) --> x >=u C in optimizeCompareInstr()
5488 if (ImmDelta != -1 || APInt::getMaxValue(BitWidth) == CmpValue) in optimizeCompareInstr()
5492 case X86::COND_LE: // x <=s (C - 1) --> x <s C in optimizeCompareInstr()
5493 if (ImmDelta != -1 || APInt::getSignedMaxValue(BitWidth) == CmpValue) in optimizeCompareInstr()
5497 case X86::COND_BE: // x <=u (C - 1) --> x <u C in optimizeCompareInstr()
5498 if (ImmDelta != -1 || APInt::getMaxValue(BitWidth) == CmpValue) in optimizeCompareInstr()
5521 // If we have to update users but EFLAGS is live-out abort, since we cannot in optimizeCompareInstr()
5525 if (Successor->isLiveIn(X86::EFLAGS)) in optimizeCompareInstr()
5532 MachineBasicBlock *SubBB = Sub->getParent(); in optimizeCompareInstr()
5541 InsertE = Sub->getParent()->rend(); in optimizeCompareInstr()
5544 if (!Instr->readsRegister(X86::EFLAGS, TRI) && in optimizeCompareInstr()
5545 Instr->modifiesRegister(X86::EFLAGS, TRI)) { in optimizeCompareInstr()
5546 Movr0Inst->getParent()->remove(Movr0Inst); in optimizeCompareInstr()
5547 Instr->getParent()->insert(MachineBasicBlock::iterator(Instr), in optimizeCompareInstr()
5558 Sub->findRegisterDefOperand(X86::EFLAGS, /*TRI=*/nullptr); in optimizeCompareInstr()
5560 FlagDef->setIsDead(false); in optimizeCompareInstr()
5566 Op.first->getOperand(Op.first->getDesc().getNumOperands() - 1) in optimizeCompareInstr()
5569 // Add EFLAGS to block live-ins between CmpBB and block of flags producer. in optimizeCompareInstr()
5571 MBB = *MBB->pred_begin()) { in optimizeCompareInstr()
5572 assert(MBB->pred_size() == 1 && "Expected exactly one predecessor"); in optimizeCompareInstr()
5573 if (!MBB->isLiveIn(X86::EFLAGS)) in optimizeCompareInstr()
5574 MBB->addLiveIn(X86::EFLAGS); in optimizeCompareInstr()
5582 /// instructions in-between do not load or store, and have no side effects.
5588 DefMI = MRI->getVRegDef(FoldAsLoadDefReg); in optimizeLoadInstr()
5591 if (!DefMI->isSafeToMove(nullptr, SawStore)) in optimizeLoadInstr()
5708 RC = MRI->getRegClass(Reg); in foldImmediateImpl()
5715 if (UseMI.findRegisterUseOperand(Reg, /*TRI=*/nullptr)->getSubReg()) in foldImmediateImpl()
5719 if (UseMI.getMF()->getFunction().hasOptSize() && Reg.isVirtual() && in foldImmediateImpl()
5720 !MRI->hasOneNonDBGUse(Reg)) in foldImmediateImpl()
5729 RC = MRI->getRegClass(ToReg); in foldImmediateImpl()
5753 if (UseMI.getParent()->computeRegisterLiveness( in foldImmediateImpl()
5809 // MRI. Let the caller handle it, or pass dead-mi-elimination can delete in foldImmediateImpl()
5851 if (Reg.isVirtual() && MRI->use_nodbg_empty(Reg)) in foldImmediateImpl()
5852 DefMI->eraseFromBundle(); in foldImmediateImpl()
5857 /// foldImmediate - 'Reg' is known to be defined by a move immediate
5868 /// Expand a single-def pseudo instruction to a two-addr
5877 assert(Desc.getNumOperands() == 3 && "Expected two-addr instruction."); in Expand2AddrUndef()
5879 MIB->setDesc(Desc); in Expand2AddrUndef()
5889 /// Expand a single-def pseudo instruction to a two-addr
5897 assert(Desc.getNumOperands() == 3 && "Expected two-addr instruction."); in Expand2AddrKreg()
5898 MIB->setDesc(Desc); in Expand2AddrKreg()
5905 MachineBasicBlock &MBB = *MIB->getParent(); in expandMOV32r1()
5906 const DebugLoc &DL = MIB->getDebugLoc(); in expandMOV32r1()
5915 MIB->setDesc(TII.get(MinusOne ? X86::DEC32r : X86::INC32r)); in expandMOV32r1()
5924 MachineBasicBlock &MBB = *MIB->getParent(); in ExpandMOVImmSExti8()
5925 const DebugLoc &DL = MIB->getDebugLoc(); in ExpandMOVImmSExti8()
5926 int64_t Imm = MIB->getOperand(1).getImm(); in ExpandMOVImmSExti8()
5933 assert(MIB->getOpcode() == X86::MOV64ImmSExti8 || in ExpandMOVImmSExti8()
5934 MIB->getOpcode() == X86::MOV32ImmSExti8); in ExpandMOVImmSExti8()
5938 MBB.getParent()->getInfo<X86MachineFunctionInfo>(); in ExpandMOVImmSExti8()
5939 if (X86FI->getUsesRedZone()) { in ExpandMOVImmSExti8()
5940 MIB->setDesc(TII.get(MIB->getOpcode() == X86::MOV32ImmSExti8 in ExpandMOVImmSExti8()
5946 // 64-bit mode doesn't have 32-bit push/pop, so use 64-bit operations and in ExpandMOVImmSExti8()
5950 MIB->setDesc(TII.get(X86::POP64r)); in ExpandMOVImmSExti8()
5951 MIB->getOperand(0).setReg(getX86SubSuperRegister(MIB.getReg(0), 64)); in ExpandMOVImmSExti8()
5953 assert(MIB->getOpcode() == X86::MOV32ImmSExti8); in ExpandMOVImmSExti8()
5956 MIB->setDesc(TII.get(X86::POP32r)); in ExpandMOVImmSExti8()
5958 MIB->removeOperand(1); in ExpandMOVImmSExti8()
5959 MIB->addImplicitDefUseOperands(*MBB.getParent()); in ExpandMOVImmSExti8()
5964 bool IsWin64Prologue = MF.getTarget().getMCAsmInfo()->usesWindowsCFI(); in ExpandMOVImmSExti8()
5966 bool EmitCFI = !TFL->hasFP(MF) && NeedsDwarfCFI; in ExpandMOVImmSExti8()
5968 TFL->BuildCFI( in ExpandMOVImmSExti8()
5971 TFL->BuildCFI( in ExpandMOVImmSExti8()
5973 MCCFIInstruction::createAdjustCfaOffset(nullptr, -StackAdjustment)); in ExpandMOVImmSExti8()
5979 // LoadStackGuard has so far only been implemented for 64-bit MachO. Different
5983 MachineBasicBlock &MBB = *MIB->getParent(); in expandLoadStackGuard()
5984 const DebugLoc &DL = MIB->getDebugLoc(); in expandLoadStackGuard()
5987 cast<GlobalValue>((*MIB->memoperands_begin())->getValue()); in expandLoadStackGuard()
5991 MachineMemOperand *MMO = MBB.getParent()->getMachineMemOperand( in expandLoadStackGuard()
6002 MIB->setDebugLoc(DL); in expandLoadStackGuard()
6003 MIB->setDesc(TII.get(X86::MOV64rm)); in expandLoadStackGuard()
6008 MachineBasicBlock &MBB = *MIB->getParent(); in expandXorFP()
6013 MIB->getOpcode() == X86::XOR64_FP ? X86::XOR64rr : X86::XOR32rr; in expandXorFP()
6014 MIB->setDesc(TII.get(XorOp)); in expandXorFP()
6015 MIB.addReg(TRI->getFrameRegister(MF), RegState::Undef); in expandXorFP()
6019 // This is used to handle spills for 128/256-bit registers when we have AVX512,
6021 // that loads the lower 128/256-bit, but is available with only AVX512F.
6027 // Check if DestReg is XMM16-31 or YMM16-31. in expandNOVLXLoad()
6028 if (TRI->getEncodingValue(DestReg) < 16) { in expandNOVLXLoad()
6030 MIB->setDesc(LoadDesc); in expandNOVLXLoad()
6032 // Use a 128/256-bit VBROADCAST instruction. in expandNOVLXLoad()
6033 MIB->setDesc(BroadcastDesc); in expandNOVLXLoad()
6034 // Change the destination to a 512-bit register. in expandNOVLXLoad()
6035 DestReg = TRI->getMatchingSuperReg(DestReg, SubIdx, &X86::VR512RegClass); in expandNOVLXLoad()
6036 MIB->getOperand(0).setReg(DestReg); in expandNOVLXLoad()
6041 // This is used to handle spills for 128/256-bit registers when we have AVX512,
6043 // that stores the lower 128/256-bit, but is available with only AVX512F.
6049 // Check if DestReg is XMM16-31 or YMM16-31. in expandNOVLXStore()
6050 if (TRI->getEncodingValue(SrcReg) < 16) { in expandNOVLXStore()
6052 MIB->setDesc(StoreDesc); in expandNOVLXStore()
6055 MIB->setDesc(ExtractDesc); in expandNOVLXStore()
6056 // Change the destination to a 512-bit register. in expandNOVLXStore()
6057 SrcReg = TRI->getMatchingSuperReg(SrcReg, SubIdx, &X86::VR512RegClass); in expandNOVLXStore()
6058 MIB->getOperand(X86::AddrNumOperands).setReg(SrcReg); in expandNOVLXStore()
6066 MIB->setDesc(Desc); in expandSHXDROT()
6067 int64_t ShiftAmt = MIB->getOperand(2).getImm(); in expandSHXDROT()
6069 MIB->removeOperand(2); in expandSHXDROT()
6071 MIB.addReg(MIB.getReg(1), getUndefRegState(MIB->getOperand(1).isUndef())); in expandSHXDROT()
6079 MachineInstrBuilder MIB(*MI.getParent()->getParent(), MI); in expandPostRAPseudo()
6106 Register XReg = TRI->getSubReg(SrcReg, X86::sub_xmm); in expandPostRAPseudo()
6107 MIB->getOperand(0).setReg(XReg); in expandPostRAPseudo()
6120 if (HasVLX || TRI->getEncodingValue(SrcReg) < 16) in expandPostRAPseudo()
6125 TRI->getMatchingSuperReg(SrcReg, X86::sub_xmm, &X86::VR512RegClass); in expandPostRAPseudo()
6126 MIB->getOperand(0).setReg(SrcReg); in expandPostRAPseudo()
6134 if (HasVLX || TRI->getEncodingValue(SrcReg) < 16) { in expandPostRAPseudo()
6135 Register XReg = TRI->getSubReg(SrcReg, X86::sub_xmm); in expandPostRAPseudo()
6136 MIB->getOperand(0).setReg(XReg); in expandPostRAPseudo()
6144 TRI->getMatchingSuperReg(SrcReg, X86::sub_ymm, &X86::VR512RegClass); in expandPostRAPseudo()
6145 MIB->getOperand(0).setReg(ZReg); in expandPostRAPseudo()
6157 MIB->setDesc(get(X86::VCMPPSYrri)); in expandPostRAPseudo()
6163 MIB->setDesc(get(X86::VPTERNLOGDZrri)); in expandPostRAPseudo()
6176 unsigned MaskState = getRegState(MIB->getOperand(1)); in expandPostRAPseudo()
6181 MIB->setDesc(get(Opc)); in expandPostRAPseudo()
6219 MIB->getOperand(0).setReg(Reg32); in expandPostRAPseudo()
6227 MachineBasicBlock &MBB = *MIB->getParent(); in expandPostRAPseudo()
6229 MachineInstr *NewMI = BuildMI(MBB, MI, MIB->getDebugLoc(), in expandPostRAPseudo()
6237 assert(NewMI->getOperand(2).getReg() == X86::EFLAGS && in expandPostRAPseudo()
6239 NewMI->getOperand(2).setIsUndef(); in expandPostRAPseudo()
6240 assert(NewMI->getOperand(3).getReg() == X86::DF && in expandPostRAPseudo()
6242 NewMI->getOperand(3).setIsUndef(); in expandPostRAPseudo()
6244 MIB->setDesc(get(Is64Bit ? X86::POP64r : X86::POP32r)); in expandPostRAPseudo()
6251 MachineBasicBlock &MBB = *MIB->getParent(); in expandPostRAPseudo()
6253 BuildMI(MBB, MI, MIB->getDebugLoc(), in expandPostRAPseudo()
6256 BuildMI(MBB, MI, MIB->getDebugLoc(), in expandPostRAPseudo()
6262 // KNL does not recognize dependency-breaking idioms for mask registers, in expandPostRAPseudo()
6296 MIB->setDesc(get(X86::OR8rr)); in expandPostRAPseudo()
6299 MIB->setDesc(get(X86::OR16rr)); in expandPostRAPseudo()
6302 MIB->setDesc(get(X86::OR32rr)); in expandPostRAPseudo()
6305 MIB->setDesc(get(X86::OR64rr)); in expandPostRAPseudo()
6308 MIB->setDesc(get(X86::OR8ri)); in expandPostRAPseudo()
6311 MIB->setDesc(get(X86::OR16ri)); in expandPostRAPseudo()
6314 MIB->setDesc(get(X86::OR32ri)); in expandPostRAPseudo()
6317 MIB->setDesc(get(X86::OR64ri32)); in expandPostRAPseudo()
6324 /// the first 32 or 64-bits of the destination register and leave the rest
6326 /// only update part of the destination register, and the non-updated part is
6793 // AVX-512 in hasUndefRegUpdate()
6887 // AVX-512 in hasUndefRegUpdate()
7021 /// high bits that are passed-through are not live.
7049 // It wants to read and write the xmm sub-register. in breakPartialRegDependency()
7050 Register XReg = TRI->getSubReg(Reg, X86::sub_xmm); in breakPartialRegDependency()
7071 // It wants to read and write the xmm sub-register. in breakPartialRegDependency()
7072 Register XReg = TRI->getSubReg(Reg, X86::sub_xmm); in breakPartialRegDependency()
7081 Register XReg = TRI->getSubReg(Reg, X86::sub_32bit); in breakPartialRegDependency()
7100 // FrameIndex only - add an immediate offset (whether its zero or not). in addOperands()
7105 // General Memory Addressing - we need to add any offset to an existing in addOperands()
7158 unsigned NumOps = MI.getDesc().getNumOperands() - 2; in fuseTwoAddrInst()
7168 MachineBasicBlock *MBB = InsertPt->getParent(); in fuseTwoAddrInst()
7169 MBB->insert(InsertPt, NewMI); in fuseTwoAddrInst()
7198 NewMI->setFlag(MachineInstr::MIFlag::NoFPExcept); in fuseInst()
7200 MachineBasicBlock *MBB = InsertPt->getParent(); in fuseInst()
7201 MBB->insert(InsertPt, NewMI); in fuseInst()
7210 MachineInstrBuilder MIB = BuildMI(*InsertPt->getParent(), InsertPt, in makeM0Inst()
7227 unsigned Imm = MI.getOperand(MI.getNumOperands() - 1).getImm(); in foldMemoryOperandCustom()
7245 NewMI->getOperand(NewMI->getNumOperands() - 1).setImm(NewImm); in foldMemoryOperandCustom()
7253 // Move the upper 64-bits of the second operand to the lower 64-bits. in foldMemoryOperandCustom()
7255 // TODO: In most cases AVX doesn't have a 8-byte alignment requirement. in foldMemoryOperandCustom()
7305 // -Register has the undef flag set. in shouldPreventUndefRegUpdateMemFold()
7306 // -Register is produced by the IMPLICIT_DEF instruction. in shouldPreventUndefRegUpdateMemFold()
7313 return VRegDef && VRegDef->isImplicitDef(); in shouldPreventUndefRegUpdateMemFold()
7392 // Folding a memory location into the two-address part of a two-address in foldMemoryOperandImpl()
7396 // Utilize the mapping NonNDD -> RMW for the NDD variant. in foldMemoryOperandImpl()
7404 unsigned Opcode = I->DstOp; in foldMemoryOperandImpl()
7406 Align(1ULL << ((I->Flags & TB_ALIGN_MASK) >> TB_ALIGN_SHIFT))) in foldMemoryOperandImpl()
7416 if ((I->Flags & TB_FOLDED_LOAD) && Size < RCSize) { in foldMemoryOperandImpl()
7417 // If this is a 64-bit load, but the spill slot is 32, then we can do in foldMemoryOperandImpl()
7418 // a 32-bit load which is implicitly zero-extended. This likely is in foldMemoryOperandImpl()
7430 if ((I->Flags & TB_FOLDED_STORE) && Size != RCSize) in foldMemoryOperandImpl()
7438 // If this is the special case where we use a MOV32rm to load a 32-bit in foldMemoryOperandImpl()
7439 // value and zero-extend the top bits. Change the destination register in foldMemoryOperandImpl()
7440 // to a 32-bit one. in foldMemoryOperandImpl()
7441 Register DstReg = NewMI->getOperand(0).getReg(); in foldMemoryOperandImpl()
7443 NewMI->getOperand(0).setReg(RI.getSubReg(DstReg, X86::sub_32bit)); in foldMemoryOperandImpl()
7445 NewMI->getOperand(0).setSubReg(X86::sub_32bit); in foldMemoryOperandImpl()
7463 // Folding failed again - undo the commute before returning. in foldMemoryOperandImpl()
7489 // MOV32r0 is special b/c it's used to clear a 64-bit register too. in foldMemoryOperandImpl()
7504 std::min(Alignment, Subtarget.getFrameLowering()->getStackAlign()); in foldMemoryOperandImpl()
7555 /// ->
7561 /// ->
8021 Alignment = (*LoadMI.memoperands_begin())->getAlign(); in foldMemoryOperandImpl()
8107 // Create a constant-pool entry and operands to load from it. in foldMemoryOperandImpl()
8113 // x86-32 PIC requires a PIC base register for constant pools. in foldMemoryOperandImpl()
8116 // RIP-relative addressing for a smaller encoding. in foldMemoryOperandImpl()
8127 // Create a constant-pool entry. in foldMemoryOperandImpl()
8203 MOs.append(LoadMI.operands_begin() + NumOps - X86::AddrNumOperands, \ in foldMemoryOperandImpl()
8229 MOs.append(LoadMI.operands_begin() + NumOps - X86::AddrNumOperands, in foldMemoryOperandImpl()
8246 ? fuseInst(MF, I->DstOp, OpNum, MOs, InsertPt, MI, *this) in foldMemoryBroadcast()
8262 // Folding failed again - undo the commute before returning. in foldMemoryBroadcast()
8275 if (!MMO->isLoad()) in extractLoadMMOs()
8278 if (!MMO->isStore()) { in extractLoadMMOs()
8284 MMO, MMO->getFlags() & ~MachineMemOperand::MOStore)); in extractLoadMMOs()
8296 if (!MMO->isStore()) in extractStoreMMOs()
8299 if (!MMO->isLoad()) { in extractStoreMMOs()
8305 MMO, MMO->getFlags() & ~MachineMemOperand::MOLoad)); in extractStoreMMOs()
8316 unsigned SpillSize = STI.getRegisterInfo()->getSpillSize(*RC); in getBroadcastOpcode()
8334 switch (I->Flags & TB_BCAST_MASK) { in getBroadcastOpcode()
8358 unsigned Opc = I->DstOp; in unfoldMemoryOperand()
8359 unsigned Index = I->Flags & TB_INDEX_MASK; in unfoldMemoryOperand()
8360 bool FoldedLoad = I->Flags & TB_FOLDED_LOAD; in unfoldMemoryOperand()
8361 bool FoldedStore = I->Flags & TB_FOLDED_STORE; in unfoldMemoryOperand()
8373 // TODO: Check if 32-byte or greater accesses are slow too? in unfoldMemoryOperand()
8401 if (I->Flags & TB_BCAST_MASK) { in unfoldMemoryOperand()
8405 bool isAligned = !MMOs.empty() && MMOs.front()->getAlign() >= Alignment; in unfoldMemoryOperand()
8419 MachineOperand &MO = NewMIs[0]->getOperand(i); in unfoldMemoryOperand()
8446 switch (DataMI->getOpcode()) { in unfoldMemoryOperand()
8453 MachineOperand &MO0 = DataMI->getOperand(0); in unfoldMemoryOperand()
8454 MachineOperand &MO1 = DataMI->getOperand(1); in unfoldMemoryOperand()
8457 switch (DataMI->getOpcode()) { in unfoldMemoryOperand()
8473 DataMI->setDesc(get(NewOpc)); in unfoldMemoryOperand()
8485 bool isAligned = !MMOs.empty() && MMOs.front()->getAlign() >= Alignment; in unfoldMemoryOperand()
8501 if (!N->isMachineOpcode()) in unfoldMemoryOperand()
8504 const X86FoldTableEntry *I = lookupUnfoldTable(N->getMachineOpcode()); in unfoldMemoryOperand()
8507 unsigned Opc = I->DstOp; in unfoldMemoryOperand()
8508 unsigned Index = I->Flags & TB_INDEX_MASK; in unfoldMemoryOperand()
8509 bool FoldedLoad = I->Flags & TB_FOLDED_LOAD; in unfoldMemoryOperand()
8510 bool FoldedStore = I->Flags & TB_FOLDED_STORE; in unfoldMemoryOperand()
8520 unsigned NumOps = N->getNumOperands(); in unfoldMemoryOperand()
8521 for (unsigned i = 0; i != NumOps - 1; ++i) { in unfoldMemoryOperand()
8522 SDValue Op = N->getOperand(i); in unfoldMemoryOperand()
8523 if (i >= Index - NumDefs && i < Index - NumDefs + X86::AddrNumOperands) in unfoldMemoryOperand()
8525 else if (i < Index - NumDefs) in unfoldMemoryOperand()
8527 else if (i > Index - NumDefs) in unfoldMemoryOperand()
8530 SDValue Chain = N->getOperand(NumOps - 1); in unfoldMemoryOperand()
8537 auto MMOs = extractLoadMMOs(cast<MachineSDNode>(N)->memoperands(), MF); in unfoldMemoryOperand()
8542 // FIXME: If a VR128 can have size 32, we should be checking if a 32-byte in unfoldMemoryOperand()
8546 if (I->Flags & TB_BCAST_MASK) { in unfoldMemoryOperand()
8550 bool isAligned = !MMOs.empty() && MMOs.front()->getAlign() >= Alignment; in unfoldMemoryOperand()
8568 for (unsigned i = 0, e = N->getNumValues(); i != e; ++i) { in unfoldMemoryOperand()
8569 EVT VT = N->getValueType(i); in unfoldMemoryOperand()
8612 auto MMOs = extractStoreMMOs(cast<MachineSDNode>(N)->memoperands(), MF); in unfoldMemoryOperand()
8617 // FIXME: If a VR128 can have size 32, we should be checking if a 32-byte in unfoldMemoryOperand()
8620 bool isAligned = !MMOs.empty() && MMOs.front()->getAlign() >= Alignment; in unfoldMemoryOperand()
8640 bool FoldedLoad = I->Flags & TB_FOLDED_LOAD; in getOpcodeAfterMemoryUnfold()
8641 bool FoldedStore = I->Flags & TB_FOLDED_STORE; in getOpcodeAfterMemoryUnfold()
8647 *LoadRegIndex = I->Flags & TB_INDEX_MASK; in getOpcodeAfterMemoryUnfold()
8648 return I->DstOp; in getOpcodeAfterMemoryUnfold()
8654 if (!Load1->isMachineOpcode() || !Load2->isMachineOpcode()) in areLoadsFromSameBasePtr()
8748 if (!IsLoadOpcode(Load1->getMachineOpcode()) || in areLoadsFromSameBasePtr()
8749 !IsLoadOpcode(Load2->getMachineOpcode())) in areLoadsFromSameBasePtr()
8754 return Load1->getOperand(I) == Load2->getOperand(I); in areLoadsFromSameBasePtr()
8767 auto Disp1 = dyn_cast<ConstantSDNode>(Load1->getOperand(X86::AddrDisp)); in areLoadsFromSameBasePtr()
8768 auto Disp2 = dyn_cast<ConstantSDNode>(Load2->getOperand(X86::AddrDisp)); in areLoadsFromSameBasePtr()
8772 Offset1 = Disp1->getSExtValue(); in areLoadsFromSameBasePtr()
8773 Offset2 = Disp2->getSExtValue(); in areLoadsFromSameBasePtr()
8781 if ((Offset2 - Offset1) / 8 > 64) in shouldScheduleLoadsNear()
8784 unsigned Opc1 = Load1->getMachineOpcode(); in shouldScheduleLoadsNear()
8785 unsigned Opc2 = Load2->getMachineOpcode(); in shouldScheduleLoadsNear()
8800 EVT VT = Load1->getValueType(0); in shouldScheduleLoadsNear()
8803 // XMM registers. In 64-bit mode we can be a bit more aggressive since we in shouldScheduleLoadsNear()
8868 X86MachineFunctionInfo *X86FI = MF->getInfo<X86MachineFunctionInfo>(); in getGlobalBaseReg()
8869 Register GlobalBaseReg = X86FI->getGlobalBaseReg(); in getGlobalBaseReg()
8875 MachineRegisterInfo &RegInfo = MF->getRegInfo(); in getGlobalBaseReg()
8878 X86FI->setGlobalBaseReg(GlobalBaseReg); in getGlobalBaseReg()
8888 if (Row[domain - 1] == opcode) in lookup()
8897 if (Row[domain - 1] == opcode || (domain == 3 && Row[3] == opcode)) in lookupAVX512()
8911 unsigned SubMask = (1u << Scale) - 1; in AdjustBlendMask()
8921 unsigned SubMask = (1u << Scale) - 1; in AdjustBlendMask()
8940 if (MI.getOperand(NumOperands - 1).isImm()) { in getExecutionDomainCustom()
8941 unsigned Imm = MI.getOperand(NumOperands - 1).getImm(); in getExecutionDomainCustom()
8977 // Treat VPBLENDWY as a 128-bit vector as it repeats the lo/hi masks. in getExecutionDomainCustom()
9059 if (MI.getOperand(NumOperands - 1).isImm()) { in setExecutionDomainCustom()
9060 unsigned Imm = MI.getOperand(NumOperands - 1).getImm() & 255; in setExecutionDomainCustom()
9080 assert(!Is256 && "128-bit vector expected"); in setExecutionDomainCustom()
9085 assert(table && table[Domain - 1] && "Unknown domain op"); in setExecutionDomainCustom()
9086 MI.setDesc(get(table[Domain - 1])); in setExecutionDomainCustom()
9087 MI.getOperand(NumOperands - 1).setImm(NewImm & 255); in setExecutionDomainCustom()
9164 MI.setDesc(get(table[Domain - 1])); in setExecutionDomainCustom()
9252 "256-bit vector operations only available in AVX2"); in setExecutionDomain()
9262 "256-bit insert/extract only available in AVX2"); in setExecutionDomain()
9266 assert(Subtarget.hasAVX512() && "Requires AVX-512"); in setExecutionDomain()
9273 assert((Subtarget.hasDQI() || Domain >= 3) && "Requires AVX-512DQ"); in setExecutionDomain()
9281 assert((Subtarget.hasDQI() || Domain >= 3) && "Requires AVX-512DQ"); in setExecutionDomain()
9287 MI.setDesc(get(table[Domain - 1])); in setExecutionDomain()
9637 if (FlagDef && !FlagDef->isDead()) in hasReassociableOperands()
9981 auto Expr = DIExpression::get(MI.getMF()->getFunction().getContext(), {}); in describeMOVrrLoadedValue()
9987 // If the described register is a sub-register of the destination register, in describeMOVrrLoadedValue()
9988 // then pick out the source register's corresponding sub-register. in describeMOVrrLoadedValue()
9989 if (unsigned SubRegIdx = TRI->getSubRegIndex(DestReg, DescribedReg)) { in describeMOVrrLoadedValue()
9990 Register SrcSubReg = TRI->getSubReg(SrcReg, SubRegIdx); in describeMOVrrLoadedValue()
9995 // super-register of the destination register. MOV8rr and MOV16rr does not in describeMOVrrLoadedValue()
9998 // non-overlapping bits in the described register, which is not currently in describeMOVrrLoadedValue()
10001 !TRI->isSuperRegister(DestReg, DescribedReg)) in describeMOVrrLoadedValue()
10004 assert(MI.getOpcode() == X86::MOV32rr && "Unexpected super-register case"); in describeMOVrrLoadedValue()
10019 // We may need to describe a 64-bit parameter with a 32-bit LEA. in describeLoadedValue()
10020 if (!TRI->isSuperRegisterEq(MI.getOperand(0).getReg(), Reg)) in describeLoadedValue()
10039 TRI->regsOverlap(Op1.getReg(), MI.getOperand(0).getReg())) || in describeLoadedValue()
10041 TRI->regsOverlap(Op2.getReg(), MI.getOperand(0).getReg()))) in describeLoadedValue()
10044 int64_t Coef = MI.getOperand(2).getImm(); in describeLoadedValue() local
10053 if (Op && Op->isReg() && Op->getReg() == Op2.getReg() && Coef > 0) { in describeLoadedValue()
10055 Ops.push_back(Coef + 1); in describeLoadedValue()
10059 int dwarfReg = TRI->getDwarfRegNum(Op2.getReg(), false); in describeLoadedValue()
10075 if (Coef > 1) { in describeLoadedValue()
10078 Ops.push_back(Coef); in describeLoadedValue()
10089 Expr = DIExpression::get(MI.getMF()->getFunction().getContext(), Ops); in describeLoadedValue()
10100 // MOV32ri may be used for producing zero-extended 32-bit immediates in in describeLoadedValue()
10101 // 64-bit parameters, so we need to consider super-registers. in describeLoadedValue()
10102 if (!TRI->isSuperRegisterEq(MI.getOperand(0).getReg(), Reg)) in describeLoadedValue()
10111 // 64-bit parameters are zero-materialized using XOR32rr, so also consider in describeLoadedValue()
10112 // super-registers. in describeLoadedValue()
10113 if (!TRI->isSuperRegisterEq(MI.getOperand(0).getReg(), Reg)) in describeLoadedValue()
10126 if (!TRI->isSubRegisterEq(MI.getOperand(0).getReg(), Reg)) in describeLoadedValue()
10129 Expr = DIExpression::get(MI.getMF()->getFunction().getContext(), {}); in describeLoadedValue()
10132 // sign-extend the source register from 32 bits. The other case we handle in describeLoadedValue()
10133 // is when the described register is the 32-bit sub-register of the in describeLoadedValue()
10140 "Unhandled sub-register case for MOVSX64rr32"); in describeLoadedValue()
10150 /// This is an architecture-specific helper function of reassociateOps.
10168 assert(OldFlagDef1->isDead() && OldFlagDef2->isDead() && in setSpecialOperandAttr()
10183 NewFlagDef1->setIsDead(); in setSpecialOperandAttr()
10184 NewFlagDef2->setIsDead(); in setSpecialOperandAttr()
10196 {MO_GOT_ABSOLUTE_ADDRESS, "x86-got-absolute-address"}, in getSerializableDirectMachineOperandTargetFlags()
10197 {MO_PIC_BASE_OFFSET, "x86-pic-base-offset"}, in getSerializableDirectMachineOperandTargetFlags()
10198 {MO_GOT, "x86-got"}, in getSerializableDirectMachineOperandTargetFlags()
10199 {MO_GOTOFF, "x86-gotoff"}, in getSerializableDirectMachineOperandTargetFlags()
10200 {MO_GOTPCREL, "x86-gotpcrel"}, in getSerializableDirectMachineOperandTargetFlags()
10201 {MO_GOTPCREL_NORELAX, "x86-gotpcrel-norelax"}, in getSerializableDirectMachineOperandTargetFlags()
10202 {MO_PLT, "x86-plt"}, in getSerializableDirectMachineOperandTargetFlags()
10203 {MO_TLSGD, "x86-tlsgd"}, in getSerializableDirectMachineOperandTargetFlags()
10204 {MO_TLSLD, "x86-tlsld"}, in getSerializableDirectMachineOperandTargetFlags()
10205 {MO_TLSLDM, "x86-tlsldm"}, in getSerializableDirectMachineOperandTargetFlags()
10206 {MO_GOTTPOFF, "x86-gottpoff"}, in getSerializableDirectMachineOperandTargetFlags()
10207 {MO_INDNTPOFF, "x86-indntpoff"}, in getSerializableDirectMachineOperandTargetFlags()
10208 {MO_TPOFF, "x86-tpoff"}, in getSerializableDirectMachineOperandTargetFlags()
10209 {MO_DTPOFF, "x86-dtpoff"}, in getSerializableDirectMachineOperandTargetFlags()
10210 {MO_NTPOFF, "x86-ntpoff"}, in getSerializableDirectMachineOperandTargetFlags()
10211 {MO_GOTNTPOFF, "x86-gotntpoff"}, in getSerializableDirectMachineOperandTargetFlags()
10212 {MO_DLLIMPORT, "x86-dllimport"}, in getSerializableDirectMachineOperandTargetFlags()
10213 {MO_DARWIN_NONLAZY, "x86-darwin-nonlazy"}, in getSerializableDirectMachineOperandTargetFlags()
10214 {MO_DARWIN_NONLAZY_PIC_BASE, "x86-darwin-nonlazy-pic-base"}, in getSerializableDirectMachineOperandTargetFlags()
10215 {MO_TLVP, "x86-tlvp"}, in getSerializableDirectMachineOperandTargetFlags()
10216 {MO_TLVP_PIC_BASE, "x86-tlvp-pic-base"}, in getSerializableDirectMachineOperandTargetFlags()
10217 {MO_SECREL, "x86-secrel"}, in getSerializableDirectMachineOperandTargetFlags()
10218 {MO_COFFSTUB, "x86-coffstub"}}; in getSerializableDirectMachineOperandTargetFlags()
10224 /// global base register for x86-32.
10235 if (!TM->isPositionIndependent()) in runOnMachineFunction()
10239 Register GlobalBaseReg = X86FI->getGlobalBaseReg(); in runOnMachineFunction()
10259 if (TM->getCodeModel() == CodeModel::Large) { in runOnMachineFunction()
10263 // movq $_GLOBAL_OFFSET_TABLE_ - .LN$pb, %rcx in runOnMachineFunction()
10268 BuildMI(FirstMBB, MBBI, DL, TII->get(X86::LEA64r), PBReg) in runOnMachineFunction()
10274 std::prev(MBBI)->setPreInstrSymbol(MF, MF.getPICBaseSymbol()); in runOnMachineFunction()
10275 BuildMI(FirstMBB, MBBI, DL, TII->get(X86::MOV64ri), GOTReg) in runOnMachineFunction()
10278 BuildMI(FirstMBB, MBBI, DL, TII->get(X86::ADD64rr), PC) in runOnMachineFunction()
10282 // In other code models, use a RIP-relative LEA to materialize the in runOnMachineFunction()
10284 BuildMI(FirstMBB, MBBI, DL, TII->get(X86::LEA64r), PC) in runOnMachineFunction()
10294 BuildMI(FirstMBB, MBBI, DL, TII->get(X86::MOVPC32r), PC).addImm(0); in runOnMachineFunction()
10299 // Generate addl $__GLOBAL_OFFSET_TABLE_ + [.-piclabel], in runOnMachineFunction()
10301 BuildMI(FirstMBB, MBBI, DL, TII->get(X86::ADD32ri), GlobalBaseReg) in runOnMachineFunction()
10335 if (MFI->getNumLocalDynamicTLSAccesses() < 2) { in runOnMachineFunction()
10342 return VisitNode(DT->getRootNode(), 0); in runOnMachineFunction()
10345 // Visit the dominator subtree rooted at Node in pre-order.
10346 // If TLSBaseAddrReg is non-null, then use that to replace any
10351 MachineBasicBlock *BB = Node->getBlock(); in VisitNode()
10355 for (MachineBasicBlock::iterator I = BB->begin(), E = BB->end(); I != E; in VisitNode()
10357 switch (I->getOpcode()) { in VisitNode()
10383 MachineFunction *MF = I.getParent()->getParent(); in ReplaceTLSBaseAddrCall()
10384 const X86Subtarget &STI = MF->getSubtarget<X86Subtarget>(); in ReplaceTLSBaseAddrCall()
10391 TII->get(TargetOpcode::COPY), is64Bit ? X86::RAX : X86::EAX) in ReplaceTLSBaseAddrCall()
10403 MachineFunction *MF = I.getParent()->getParent(); in SetRegister()
10404 const X86Subtarget &STI = MF->getSubtarget<X86Subtarget>(); in SetRegister()
10409 MachineRegisterInfo &RegInfo = MF->getRegInfo(); in SetRegister()
10416 TII->get(TargetOpcode::COPY), *TLSBaseAddrReg) in SetRegister()
10423 return "Local Dynamic TLS Access Clean-up"; in getPassName()
10447 /// I2 --> call OUTLINED_FUNCTION I1
10460 /// I2 --> jmp OUTLINED_FUNCTION I1
10497 C.getMF()->getFrameInstructions(); in getOutliningCandidateInfo()
10530 if (Subtarget.getFrameLowering()->has128ByteRedZone(MF)) { in isFunctionSafeToOutlineFrom()
10533 if (!X86FI || X86FI->getUsesRedZone()) in isFunctionSafeToOutlineFrom()
10627 // Convert register to the 32-bit version. Both 'movl' and 'xorl' clear the in buildClearRegister()
10628 // upper bits of a 64-bit register automagically. in buildClearRegister()
10717 MachineRegisterInfo &RegInfo = MF->getRegInfo(); in genAlternativeDpCodeSequence()
10727 // --> in genAlternativeDpCodeSequence()
10747 // --> in genAlternativeDpCodeSequence()
10767 // --> in genAlternativeDpCodeSequence()
10783 MachineInstr *Madd = Root.getMF()->CloneMachineInstr(&Root); in genAlternativeDpCodeSequence()
10784 Madd->setDesc(TII.get(MaddOpc)); in genAlternativeDpCodeSequence()
10785 Madd->untieRegOperand(1); in genAlternativeDpCodeSequence()
10786 Madd->removeOperand(1); in genAlternativeDpCodeSequence()
10787 Madd->getOperand(0).setReg(NewReg); in genAlternativeDpCodeSequence()
10795 .addReg(Madd->getOperand(0).getReg(), getKillRegState(true)); in genAlternativeDpCodeSequence()