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/linux/Documentation/devicetree/bindings/clock/
H A Dti,cdce925.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Alexander Stein <alexander.stein@ew.tq-group.com>
15 - CDCE(L)913: 1-PLL, 3 Outputs https://www.ti.com/product/cdce913
16 - CDCE(L)925: 2-PLL, 5 Outputs https://www.ti.com/product/cdce925
17 - CDCE(L)937: 3-PLL, 7 Outputs https://www.ti.com/product/cdce937
18 - CDCE(L)949: 4-PLL, 9 Outputs https://www.ti.com/product/cdce949
23 - ti,cdce913
24 - ti,cdce925
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/linux/Documentation/driver-api/thermal/
H A Dintel_dptf.rst1 .. SPDX-License-Identifier: GPL-2.0
12 ------------
31 ----------------------------
43 "42A441D6-AE6A-462b-A84B-4A8CE79027D3" : Passive 1
45 "3A95C389-E4B8-4629-A526-C52C88626BAE" : Active
47 "97C68AE7-15FA-499c-B8C9-5DA81D606E0A" : Critical
49 "63BE270F-1C11-48FD-A6F7-3AF253FF3E2D" : Adaptive performance
51 "5349962F-71E6-431D-9AE8-0A635B710AEE" : Emergency call
53 "9E04115A-AE87-4D1C-9500-0F3E340BFE75" : Passive 2
55 "F5A35014-C209-46A4-993A-EB56DE7530A1" : Power Boss
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/linux/drivers/scsi/isci/
H A Dprobe_roms.h7 * Copyright(c) 2008 - 2011 Intel Corporation. All rights reserved.
20 * Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
26 * Copyright(c) 2008 - 2011 Intel Corporation. All rights reserved.
103 * - A value of 1 indicates generation 1 (i.e. 1.5 Gb/s).
104 * - A value of 2 indicates generation 2 (i.e. 3.0 Gb/s).
105 * - A value of 3 indicates generation 3 (i.e. 6.0 Gb/s).
228 * Spread Spectrum Clocking (SSC) settings for SATA and SAS.
234 * NOTE: Max spread for SATA is +0 / -5000 PPM.
235 * Down-spreading SSC (only method allowed for SATA):
237 * SATA SSC Tx at +0 / -1419 PPM Spread = 0x2
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/linux/drivers/gpu/drm/amd/display/include/
H A Dbios_parser_types.h2 * Copyright 2012-15 Advanced Micro Devices, Inc.
197 /* Input: Signal Type - to be converted to Encoder mode */
207 /* Output: If non-zero, this refDiv value should be used to calculate
210 /* Output: If non-zero, this postDiv value should be used to calculate
213 /* Input: Enable spread spectrum */
220 /* signal_type -> Encoder Mode - needed by VBIOS Exec table */
234 /* VBIOS returns a fixed display clock when DFS-bypass feature
285 /* 1 = Center Spread; 0 = down spread */
289 /* 1 = delta-sigma type parameter; 0 = ver1 */
/linux/drivers/gpu/drm/radeon/
H A Datombios.h2 * Copyright 2006-2007 Advanced Micro Devices, Inc.
214 UCHAR uaFirmWareSignature[4]; /*Signature to distinguish between Atombios and non-atombios,
397 …ONG ulPointerReturnFlag:1; // BYTE_3[7]=1 - Return the pointer to the right Data Block; BYTE_…
403 …ONG ulPointerReturnFlag:1; // BYTE_3[7]=1 - Return the pointer to the right Data Block; BYTE_…
410 …ULONG ulClock; //When returen, it's the re-calculated clock based on given Fb_div Post_Di…
504 …UCHAR ucInputFlag; //Input Flags. ucInputFlag[0] - Strobe(1)/Performance(0)…
536 #define ATOM_PLL_INPUT_FLAG_PLL_STROBE_MODE_EN 1 // 1-StrobeMode, 0-PerformanceMode
544 …bDiv; //Output:UPPER_WORD=FB_DIV_INTEGER, LOWER_WORD=FB_DIV_FRAC shl (16-FB_FRACTION_BITS)
549 … //Input : ATOM_PLL_INPUT_FLAG_PLL_STROBE_MODE_EN: 1-StrobeMode, 0-PerformanceMode
815 // Following function ENABLE sub-function will be used by driver when TMDS/HDMI/LVDS is used, disab…
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/linux/drivers/gpu/drm/amd/include/
H A Datombios.h2 * Copyright 2006-2007 Advanced Micro Devices, Inc.
107 #define ATOM_SCALER_DISABLE 0 //For Fudo, it's bypass and auto-cengter & no replication
108 #define ATOM_SCALER_CENTER 1 //For Fudo, it's bypass and auto-center & auto replication
110 #define ATOM_SCALER_MULTI_EX 3 //For Fudo only, it's multi-tap mode only used to drive TV or CV,…
222 UCHAR uaFirmWareSignature[4]; //Signature to distinguish between Atombios and non-atombios,
245 UCHAR uaFirmWareSignature[4]; //Signature to distinguish between Atombios and non-atombios,
427 …ONG ulPointerReturnFlag:1; // BYTE_3[7]=1 - Return the pointer to the right Data Block; BYTE_…
433 …ONG ulPointerReturnFlag:1; // BYTE_3[7]=1 - Return the pointer to the right Data Block; BYTE_…
440 …ULONG ulClock; //When returen, it's the re-calculated clock based on given Fb_div Post_Di…
538 …UCHAR ucInputFlag; //Input Flags. ucInputFlag[0] - Strobe(1)/Performance(0)…
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H A Datomfirmware.h6 * Description header file of general definitions for OS and pre-OS video drivers
31 * If a change in VBIOS/Driver/Tool's interface is only needed for pre-SoC15 products, then the chan…
115 ATOM_SCALER_DISABLE =0, /*scaler bypass mode, auto-center & no replication*/
116 ATOM_SCALER_CENTER =1, //For Fudo, it's bypass and auto-center & auto replication
202 #define BIOS_VERSION_PREFIX "ATOMBIOSBK-AMD"
245 …tom_string_def atom_bios_string; //Signature to distinguish between Atombios and non-atombios,
604 uint32_t maco_pwrlimit_mw; // bomaco mode power limit in unit of m-watt
605 uint32_t usb_pwrlimit_mw; // power limit when USB is enable in unit of m-watt
636 uint32_t maco_pwrlimit_mw; // bomaco mode power limit in unit of m-watt
637 uint32_t usb_pwrlimit_mw; // power limit when USB is enable in unit of m-watt
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/linux/drivers/clk/
H A Dclk-cdce925.c5 * Y4/Y5 to PLL2, and so on. PLL frequency is set on a first-come-first-serve
14 #include <linux/clk-provider.h>
54 u16 pdiv; /* 1..127 for Y2-Y9; 1..1023 for Y1 */
92 return cdce925_pll_calculate_rate(parent_rate, data->n, data->m); in cdce925_pll_recalc_rate()
146 data->m = 0; /* Bypass mode */ in cdce925_pll_set_rate()
147 data->n = 0; in cdce925_pll_set_rate()
154 return -EINVAL; in cdce925_pll_set_rate()
160 return -EINVAL; in cdce925_pll_set_rate()
163 cdce925_pll_find_rate(rate, parent_rate, &data->n, &data->m); in cdce925_pll_set_rate()
168 /* calculate p = max(0, 4 - int(log2 (n/m))) */
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/linux/drivers/phy/broadcom/
H A Dphy-brcm-sata.c1 // SPDX-License-Identifier: GPL-2.0-or-later
196 struct brcm_sata_phy *priv = port->phy_priv; in brcm_sata_ctrl_base()
199 switch (priv->version) { in brcm_sata_ctrl_base()
204 dev_err(priv->dev, "invalid phy version\n"); in brcm_sata_ctrl_base()
208 return priv->ctrl_base + (port->portnum * size); in brcm_sata_ctrl_base()
214 struct brcm_sata_phy *priv = port->phy_priv; in brcm_sata_phy_wr()
215 void __iomem *pcb_base = priv->phy_base; in brcm_sata_phy_wr()
218 if (priv->version == BRCM_SATA_PHY_STB_40NM) in brcm_sata_phy_wr()
219 bank += (port->portnum * SATA_PCB_REG_40NM_SPACE_SIZE); in brcm_sata_phy_wr()
221 pcb_base += (port->portnum * SATA_PCB_REG_28NM_SPACE_SIZE); in brcm_sata_phy_wr()
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/linux/include/uapi/linux/
H A Dnl80211.h6 * Copyright 2006-2010 Johannes Berg <johannes@sipsolutions.net>
13 * Copyright 2015-2017 Intel Deutschland GmbH
14 * Copyright (C) 2018-2024 Intel Corporation
32 * be careful not to break things - i.e. don't move anything around or so
74 * - a setup station entry is added, not yet authorized, without any rate
76 * - when the TDLS setup is done, a single NL80211_CMD_SET_STATION is valid
79 * - %NL80211_TDLS_ENABLE_LINK is then used
80 * - after this, the only valid operation is to remove it by tearing down
95 * Frame registration is done on a per-interface basis and registrations
137 * software, like the AP-VLAN type in mac80211 for example, there's
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/linux/include/net/
H A Dcfg80211.h1 /* SPDX-License-Identifier: GPL-2.0-only */
7 * Copyright 2006-2010 Johannes Berg <johannes@sipsolutions.net>
8 * Copyright 2013-2014 Intel Mobile Communications GmbH
9 * Copyright 2015-2017 Intel Deutschland GmbH
10 * Copyright (C) 2018-2024 Intel Corporation
38 * Additionally, cfg80211 contains code to help enforce regulatory spectrum
72 * enum ieee80211_channel_flags - channel flags
167 * struct ieee80211_channel - channel definition
172 * @center_freq: center frequency in MHz
174 * @hw_value: hardware-specific value for the channel
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/linux/drivers/gpu/drm/i915/display/
H A Dintel_display.c2 * Copyright © 2006-2007 Intel Corporation
27 #include <linux/dma-resv.h>
161 drm_WARN(&dev_priv->drm, (val & CCK_FREQUENCY_STATUS) != in vlv_get_cck_clock()
175 if (dev_priv->hpll_freq == 0) in vlv_get_cck_clock_hpll()
176 dev_priv->hpll_freq = vlv_get_hpll_vco(dev_priv); in vlv_get_cck_clock_hpll()
178 hpll = vlv_get_cck_clock(dev_priv, name, reg, dev_priv->hpll_freq); in vlv_get_cck_clock_hpll()
190 dev_priv->czclk_freq = vlv_get_cck_clock_hpll(dev_priv, "czclk", in intel_update_czclk()
193 drm_dbg(&dev_priv->drm, "CZ clock rate: %d kHz\n", in intel_update_czclk()
194 dev_priv->czclk_freq); in intel_update_czclk()
199 return (crtc_state->active_planes & in is_hdr_mode()
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