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/linux/drivers/clk/uniphier/
H A Dclk-uniphier-sys.c12 UNIPHIER_CLK_FACTOR("sd-200m", -1, "spll", 1, 8), \
16 UNIPHIER_CLK_FACTOR("sd-200m", -1, "spll", 1, 12), \
17 UNIPHIER_CLK_FACTOR("sd-133m", -1, "spll", 1, 18)
20 UNIPHIER_CLK_FACTOR("sd-200m", -1, "spll", 1, 10), \
21 UNIPHIER_CLK_FACTOR("sd-133m", -1, "spll", 1, 15)
24 UNIPHIER_CLK_FACTOR("sd-200m", -1, "spll", 1, 4), \
25 UNIPHIER_CLK_FACTOR("sd-133m", -1, "spll", 1, 6)
28 UNIPHIER_CLK_FACTOR("nand-50m", -1, "spll", 1, 32), \
32 UNIPHIER_CLK_FACTOR("nand-50m", -1, "spll", 1, 48), \
36 UNIPHIER_CLK_FACTOR("nand-50m", -1, "spll", 1, 40), \
[all …]
/linux/drivers/gpu/drm/radeon/
H A Dradeon_clocks.c42 struct radeon_pll *spll = &rdev->clock.spll; in radeon_legacy_get_engine_clock() local
48 fb_div *= spll->reference_freq; in radeon_legacy_get_engine_clock()
111 struct radeon_pll *spll = &rdev->clock.spll; in radeon_read_clocks_OF() local
150 spll->reference_freq = mpll->reference_freq = p1pll->reference_freq; in radeon_read_clocks_OF()
151 spll->reference_div = mpll->reference_div = in radeon_read_clocks_OF()
186 struct radeon_pll *spll = &rdev->clock.spll; in radeon_get_clock_info() local
214 if (spll->reference_div < 2) in radeon_get_clock_info()
215 spll->reference_div = in radeon_get_clock_info()
220 mpll->reference_div = spll->reference_div; in radeon_get_clock_info()
233 spll->reference_freq = 1432; in radeon_get_clock_info()
[all …]
H A Dradeon_combios.c720 struct radeon_pll *spll = &rdev->clock.spll; in radeon_combios_get_clock_info() local
747 spll->reference_freq = RBIOS16(pll_info + 0x1a); in radeon_combios_get_clock_info()
748 spll->reference_div = RBIOS16(pll_info + 0x1c); in radeon_combios_get_clock_info()
749 spll->pll_out_min = RBIOS32(pll_info + 0x1e); in radeon_combios_get_clock_info()
750 spll->pll_out_max = RBIOS32(pll_info + 0x22); in radeon_combios_get_clock_info()
753 spll->pll_in_min = RBIOS32(pll_info + 0x48); in radeon_combios_get_clock_info()
754 spll->pll_in_max = RBIOS32(pll_info + 0x4c); in radeon_combios_get_clock_info()
757 spll->pll_in_min = 40; in radeon_combios_get_clock_info()
758 spll->pll_in_max = 500; in radeon_combios_get_clock_info()
H A Dradeon_atombios.c1135 struct radeon_pll *spll = &rdev->clock.spll; in radeon_atom_get_clock_info() local
1188 spll->reference_freq = in radeon_atom_get_clock_info()
1191 spll->reference_freq = in radeon_atom_get_clock_info()
1193 spll->reference_div = 0; in radeon_atom_get_clock_info()
1195 spll->pll_out_min = in radeon_atom_get_clock_info()
1197 spll->pll_out_max = in radeon_atom_get_clock_info()
1201 if (spll->pll_out_min == 0) { in radeon_atom_get_clock_info()
1203 spll->pll_out_min = 64800; in radeon_atom_get_clock_info()
1205 spll->pll_out_min = 20000; in radeon_atom_get_clock_info()
1208 spll->pll_in_min = in radeon_atom_get_clock_info()
[all …]
H A Drv6xx_dpm.c163 u32 ref_clk = rdev->clock.spll.reference_freq; in rv6xx_output_stepping()
428 u32 ref_clk = rdev->clock.spll.reference_freq; in rv6xx_compute_count_for_delay()
551 u32 ref_clk = rdev->clock.spll.reference_freq; in rv6xx_program_engine_spread_spectrum()
840 u32 ref_clk = rdev->clock.spll.reference_freq; in rv6xx_program_bsp()
H A Drs780_dpm.c990 u32 sclk = (rdev->clock.spll.reference_freq * current_fb_div) / in rs780_dpm_debugfs_print_current_performance_level()
1012 u32 sclk = (rdev->clock.spll.reference_freq * current_fb_div) / in rs780_dpm_get_current_sclk()
H A Drv740_dpm.c130 u32 reference_clock = rdev->clock.spll.reference_freq; in rv740_populate_sclk_value()
H A Drv730_dpm.c49 u32 reference_clock = rdev->clock.spll.reference_freq; in rv730_populate_sclk_value()
H A Dradeon_kms.c346 *value = rdev->clock.spll.reference_freq * 10; in radeon_info_ioctl()
/linux/drivers/clk/imx/
H A Dclk-imx7ulp.c24 static const char * const spll_sels[] = { "spll", "spll_pfd_sel", };
34 /* used by sosc/sirc/firc/ddr/spll/apll dividers */
81 …hws[IMX7ULP_CLK_SPLL] = imx_clk_hw_pllv4(IMX_PLLV4_IMX7ULP, "spll", "spll_pre_div", base + 0x600… in imx7ulp_clk_scg1_init()
89 /* SPLL PFDs */ in imx7ulp_clk_scg1_init()
90 …hws[IMX7ULP_CLK_SPLL_PFD0] = imx_clk_hw_pfdv2(IMX_PFDV2_IMX7ULP, "spll_pfd0", "spll", base + 0x60C… in imx7ulp_clk_scg1_init()
91 …hws[IMX7ULP_CLK_SPLL_PFD1] = imx_clk_hw_pfdv2(IMX_PFDV2_IMX7ULP, "spll_pfd1", "spll", base + 0x60C… in imx7ulp_clk_scg1_init()
92 …hws[IMX7ULP_CLK_SPLL_PFD2] = imx_clk_hw_pfdv2(IMX_PFDV2_IMX7ULP, "spll_pfd2", "spll", base + 0x60C… in imx7ulp_clk_scg1_init()
93 …hws[IMX7ULP_CLK_SPLL_PFD3] = imx_clk_hw_pfdv2(IMX_PFDV2_IMX7ULP, "spll_pfd3", "spll", base + 0x60C… in imx7ulp_clk_scg1_init()
H A Dclk-imx1.c48 clk[IMX1_CLK_SPLL] = imx_clk_pllv1(IMX_PLLV1_IMX1, "spll", "prem", CCM_SPCTL0); in mx1_clocks_init_dt()
49 clk[IMX1_CLK_SPLL_GATE] = imx_clk_gate("spll_gate", "spll", CCM_CSCR, 1); in mx1_clocks_init_dt()
/linux/drivers/gpu/drm/nouveau/nvkm/subdev/clk/
H A Dnv40.c36 u32 spll; member
175 clk->spll = 0xc0000000 | (log2P << 16) | (N1 << 8) | M1; in nv40_clk_calc()
178 clk->spll = 0x00000000; in nv40_clk_calc()
193 nvkm_mask(device, 0x004008, 0xc007ffff, clk->spll); in nv40_clk_prog()
H A Dnv50.c468 /* shader: tie to nvclk if possible, otherwise use spll. have to be in nv50_clk_calc()
475 clk_mask(hwsq, spll[0], 0xc03f0100, (P1 << 19) | (P1 << 16)); in nv50_clk_calc()
482 clk_mask(hwsq, spll[0], 0xc03f0100, in nv50_clk_calc()
484 clk_mask(hwsq, spll[1], 0x0000ffff, (N << 8) | M); in nv50_clk_calc()
H A Dmcp77.c237 /* sclk: nvpll + divisor, href or spll */ in mcp77_clk_calc()
272 nvkm_debug(subdev, " spll: %08x %08x %08x\n", in mcp77_clk_calc()
285 nvkm_debug(subdev, "shader: spll\n"); in mcp77_clk_calc()
/linux/drivers/gpu/drm/amd/amdgpu/
H A Damdgpu_atombios.c590 struct amdgpu_pll *spll = &adev->clock.spll; in amdgpu_atombios_get_clock_info() local
636 spll->reference_freq = in amdgpu_atombios_get_clock_info()
638 spll->reference_div = 0; in amdgpu_atombios_get_clock_info()
640 spll->pll_out_min = in amdgpu_atombios_get_clock_info()
642 spll->pll_out_max = in amdgpu_atombios_get_clock_info()
646 if (spll->pll_out_min == 0) in amdgpu_atombios_get_clock_info()
647 spll->pll_out_min = 64800; in amdgpu_atombios_get_clock_info()
649 spll->pll_in_min = in amdgpu_atombios_get_clock_info()
651 spll->pll_in_max = in amdgpu_atombios_get_clock_info()
654 spll->min_post_div = 1; in amdgpu_atombios_get_clock_info()
[all …]
H A Dsoc21.c259 u32 reference_clock = adev->clock.spll.reference_freq; in soc21_get_xclk()
H A Dsoc15.c347 u32 reference_clock = adev->clock.spll.reference_freq; in soc15_get_xclk()
/linux/drivers/clk/rockchip/
H A Dclk-rk3576.c287 PNAME(gpll_spll_p) = { "gpll", "spll" };
290 PNAME(gpll_cpll_24m_spll_p) = { "gpll", "cpll", "xin24m", "spll" };
292 PNAME(gpll_cpll_aupll_spll_p) = { "gpll", "cpll", "aupll", "spll" };
293 PNAME(gpll_cpll_aupll_spll_lpll_p) = { "gpll", "cpll", "aupll", "spll", "lpll_dummy" };
294 PNAME(gpll_cpll_spll_bpll_p) = { "gpll", "cpll", "spll", "bpll_dummy" };
296 PNAME(gpll_spll_cpll_bpll_lpll_p) = { "gpll", "spll", "cpll", "bpll_dummy", "lpll_dummy" };
298 PNAME(gpll_cpll_spll_aupll_bpll_p) = { "gpll", "cpll", "spll", "aupll", "bpll_dummy" };
299 PNAME(gpll_cpll_spll_bpll_lpll_p) = { "gpll", "cpll", "spll", "bpll_dummy", "lpll_dummy" };
300 PNAME(gpll_cpll_spll_lpll_bpll_p) = { "gpll", "cpll", "spll", "lpll_dummy", "bpll_dummy" };
302 PNAME(gpll_spll_aupll_bpll_lpll_p) = { "gpll", "spll", "aupll", "bpll_dummy", "lpll_dummy" };
[all …]
H A Dclk-rk3588.c434 PNAME(gpll_spll_p) = { "gpll", "spll" };
439 PNAME(gpll_cpll_24m_spll_p) = { "gpll", "cpll", "xin24m", "spll" };
440 PNAME(gpll_cpll_aupll_spll_p) = { "gpll", "cpll", "aupll", "spll" };
443 PNAME(gpll_cpll_v0pll_spll_p) = { "gpll", "cpll", "v0pll", "spll" };
444 PNAME(gpll_cpll_aupll_npll_spll_p) = { "gpll", "cpll", "aupll", "npll", "spll" };
445 PNAME(gpll_cpll_dmyaupll_npll_spll_p) = { "gpll", "cpll", "dummy_aupll", "npll", "spll" };
446 PNAME(gpll_cpll_npll_aupll_spll_p) = { "gpll", "cpll", "npll", "aupll", "spll" };
448 PNAME(mux_24m_spll_gpll_cpll_p) = { "xin24m", "spll", "gpll", "cpll" };
514 PNAME(mux_24m_ppll_spll_p) = { "xin24m", "ppll", "spll" };
/linux/arch/arm/mach-imx/
H A Dpm-imx27.c30 /* Clear MPEN and SPEN to disable MPLL/SPLL */ in mx27_suspend_enter()
/linux/Documentation/devicetree/bindings/clock/
H A Dimx31-clock.yaml23 spll 4
/linux/drivers/clk/microchip/
H A Dclk-pic32mzda.c23 /* SPLL fields */
/linux/drivers/video/fbdev/aty/
H A Dradeon_pm.c1477 /* Switch SPLL to PCI source */ in radeon_pm_start_mclk_sclk()
1481 /* Reconfigure SPLL charge pump, VCO gain, duty cycle */ in radeon_pm_start_mclk_sclk()
1488 /* Set SPLL feedback divider */ in radeon_pm_start_mclk_sclk()
1493 /* Power up SPLL */ in radeon_pm_start_mclk_sclk()
1500 /* Release SPLL reset */ in radeon_pm_start_mclk_sclk()
1653 /* Reconfigure SPLL charge pump, VCO gain, duty cycle, in radeon_pm_restore_pixel_pll()
/linux/drivers/memory/samsung/
H A Dexynos5422-dmc.c136 * @fout_spll: clock: SPLL
138 * @mout_spll: clock: mux SPLL
/linux/arch/arm64/boot/dts/rockchip/
H A Drk3576.dtsi67 spll: clock-spll { label
71 clock-output-names = "spll";

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