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Searched +full:spi +full:- +full:src +full:- +full:clk (Results 1 – 25 of 74) sorted by relevance

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/linux/Documentation/devicetree/bindings/iio/adc/
H A Dst,stm32-dfsdm-adc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/iio/adc/st,stm32-dfsdm-adc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Fabrice Gasnier <fabrice.gasnier@foss.st.com>
11 - Olivier Moysan <olivier.moysan@foss.st.com>
14 STM32 DFSDM ADC is a sigma delta analog-to-digital converter dedicated to
17 - Sigma delta modulators (motor control, metering...)
18 - PDM microphones (audio digital microphone)
20 It features up to 8 serial digital interfaces (SPI or Manchester) and
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/linux/Documentation/devicetree/bindings/spi/
H A Dsamsung,spi.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/spi/samsung,spi.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Samsung S3C/S5P/Exynos SoC SPI controller
10 - Krzysztof Kozlowski <krzk@kernel.org>
13 All the SPI controller nodes should be represented in the aliases node using
14 the following format 'spi{n}' where n is a unique number for the alias.
19 - enum:
20 - google,gs101-spi
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/linux/drivers/spi/
H A Dspi-meson-spicc.c2 * Driver for Amlogic Meson SPI communication controller (SPICC)
7 * SPDX-License-Identifier: GPL-2.0+
11 #include <linux/clk.h>
12 #include <linux/clk-provider.h>
19 #include <linux/spi/spi.h>
30 * - all transfers are cutted in 16 words burst because the FIFO hangs on
31 * TX underflow, and there is no TX "Half-Empty" interrupt, so we go by
33 * - CS management is dumb, and goes UP between every burst, so is really a
69 #define SPICC_TH_EN BIT(1) /* TX FIFO Half-Full Interrupt */
72 #define SPICC_RH_EN BIT(4) /* RX FIFO Half-Full Interrupt */
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H A Dspi-sh-msiof.c1 // SPDX-License-Identifier: GPL-2.0
3 * SuperH MSIOF SPI Controller Interface
7 * Copyright (C) 2014-2017 Glider bvba
11 #include <linux/clk.h>
14 #include <linux/dma-mapping.h>
27 #include <linux/spi/sh_msiof.h>
28 #include <linux/spi/spi.h>
46 struct clk *clk; member
87 #define SIMDR1_SYNCMD_SPI (2 << 28) /* Level mode/SPI */
89 #define SIMDR1_SYNCAC_SHIFT 25 /* Sync Polarity (1 = Active-low) */
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H A Dspi-npcm-fiu.c1 // SPDX-License-Identifier: GPL-2.0
10 #include <linux/clk.h>
16 #include <linux/spi/spi-mem.h>
107 /* FIU UMA Write Data Bytes 0-3 Register */
113 /* FIU UMA Write Data Bytes 4-7 Register */
119 /* FIU UMA Write Data Bytes 8-11 Register */
125 /* FIU UMA Write Data Bytes 12-15 Register */
131 /* FIU UMA Read Data Bytes 0-3 Register */
137 /* FIU UMA Read Data Bytes 4-7 Register */
143 /* FIU UMA Read Data Bytes 8-11 Register */
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H A Dspi-aspeed-smc.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * ASPEED FMC/SPI Memory Controller Driver
5 * Copyright (c) 2015-2022, IBM Corporation.
9 #include <linux/clk.h>
14 #include <linux/spi/spi.h>
15 #include <linux/spi/spi-mem.h>
17 #define DEVICE_NAME "spi-aspeed-smc"
33 #define CTRL_IO_ADDRESS_4B BIT(13) /* AST2400 SPI only */
100 struct clk *clk; member
108 switch (op->data.buswidth) { in aspeed_spi_get_io_mode()
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H A Dspi-rockchip-sfc.c1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright (c) 2017-2021, Rockchip Inc.
6 * Author: Shawn Lin <shawn.lin@rock-chips.com>
8 * Jon Lin <Jon.lin@rock-chips.com>
12 #include <linux/clk.h>
14 #include <linux/dma-mapping.h>
22 #include <linux/spi/spi-mem.h>
124 /* Src or Dst addr for master */
154 * devices (0-3), however I have only been able to test a single CS (CS 0)
159 /* The SFC can transfer max 16KB - 1 at one time
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H A Datmel-quadspi.c1 // SPDX-License-Identifier: GPL-2.0
11 * This driver is based on drivers/mtd/spi-nor/fsl-quadspi.c from Freescale.
14 #include <linux/clk.h>
25 #include <linux/spi/spi-mem.h>
69 #define QSPI_MR_NBBITS(n) ((((n) - 8) << 8) & QSPI_MR_NBBITS_MASK)
139 #define QSPI_WPSR_WPVSRC(src) (((src) << 8) & QSPI_WPSR_WPVSRC) argument
149 struct clk *pclk;
150 struct clk *qspick;
228 u32 value = readl_relaxed(aq->regs + offset); in atmel_qspi_read()
233 dev_vdbg(&aq->pdev->dev, "read 0x%08x from %s\n", value, in atmel_qspi_read()
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H A Dspi-geni-qcom.c1 // SPDX-License-Identifier: GPL-2.0
2 // Copyright (c) 2017-2018, The Linux foundation. All rights reserved.
4 #include <linux/clk.h>
6 #include <linux/dma-mapping.h>
7 #include <linux/dma/qcom-gpi-dma.h>
16 #include <linux/soc/qcom/geni-se.h>
17 #include <linux/spi/spi.h>
20 /* SPI SE specific registers and respective register fields */
59 /* M_CMD OP codes for SPI */
66 /* M_CMD params for SPI */
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H A Dspi-mtk-nor.c1 // SPDX-License-Identifier: GPL-2.0
3 // Mediatek SPI NOR controller driver
8 #include <linux/clk.h>
10 #include <linux/dma-mapping.h>
19 #include <linux/spi/spi.h>
20 #include <linux/spi/spi-mem.h>
23 #define DRIVER_NAME "mtk-spi-nor"
91 // Reading DMA src/dst addresses have to be 16-byte aligned
93 #define MTK_NOR_DMA_ALIGN_MASK (MTK_NOR_DMA_ALIGN - 1)
97 // Buffered page program can do one 128-byte transfer
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/linux/arch/arm64/boot/dts/exynos/
H A Dexynosautov9.dtsi1 // SPDX-License-Identifier: GPL-2.0
9 #include <dt-bindings/clock/samsung,exynosautov9.h>
10 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 #include <dt-bindings/soc/samsung,boot-mode.h>
12 #include <dt-bindings/soc/samsung,exynos-usi.h>
16 #address-cells = <2>;
17 #size-cells = <1>;
19 interrupt-parent = <&gic>;
31 arm-pmu {
32 compatible = "arm,cortex-a76-pmu";
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H A Dexynos850.dtsi1 // SPDX-License-Identifier: GPL-2.0
13 #include <dt-bindings/clock/exynos850.h>
14 #include <dt-bindings/interrupt-controller/arm-gic.h>
15 #include <dt-bindings/soc/samsung,exynos-usi.h>
20 #address-cells = <2>;
21 #size-cells = <1>;
23 interrupt-parent = <&gic>;
34 arm-pmu {
35 compatible = "arm,cortex-a55-pmu";
44 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>,
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/linux/arch/arm64/boot/dts/freescale/
H A Dimx93.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 #include <dt-bindings/clock/imx93-clock.h>
7 #include <dt-bindings/dma/fsl-edma.h>
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/input/input.h>
10 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 #include <dt-bindings/power/fsl,imx93-power.h>
12 #include <dt-bindings/thermal/thermal.h>
14 #include "imx93-pinfunc.h"
17 interrupt-parent = <&gic>;
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H A Dimx8mq.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
4 * Copyright (C) 2017-2018 Pengutronix, Lucas Stach <kernel@pengutronix.de>
7 #include <dt-bindings/clock/imx8mq-clock.h>
8 #include <dt-bindings/power/imx8mq-power.h>
9 #include <dt-bindings/reset/imx8mq-reset.h>
10 #include <dt-bindings/gpio/gpio.h>
11 #include "dt-bindings/input/input.h"
12 #include <dt-bindings/interrupt-controller/arm-gic.h>
13 #include <dt-bindings/thermal/thermal.h>
14 #include <dt-bindings/interconnect/imx8mq.h>
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H A Dimx8mm.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 #include <dt-bindings/clock/imx8mm-clock.h>
7 #include <dt-bindings/gpio/gpio.h>
8 #include <dt-bindings/input/input.h>
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 #include <dt-bindings/power/imx8mm-power.h>
11 #include <dt-bindings/reset/imx8mq-reset.h>
12 #include <dt-bindings/thermal/thermal.h>
14 #include "imx8mm-pinfunc.h"
17 interrupt-parent = <&gic>;
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H A Dimx8mn.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 #include <dt-bindings/clock/imx8mn-clock.h>
7 #include <dt-bindings/power/imx8mn-power.h>
8 #include <dt-bindings/reset/imx8mq-reset.h>
9 #include <dt-bindings/gpio/gpio.h>
10 #include <dt-bindings/input/input.h>
11 #include <dt-bindings/interrupt-controller/arm-gic.h>
12 #include <dt-bindings/thermal/thermal.h>
14 #include "imx8mn-pinfunc.h"
17 interrupt-parent = <&gic>;
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H A Dimx8mp.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 #include <dt-bindings/clock/imx8mp-clock.h>
7 #include <dt-bindings/power/imx8mp-power.h>
8 #include <dt-bindings/reset/imx8mp-reset.h>
9 #include <dt-bindings/gpio/gpio.h>
10 #include <dt-bindings/input/input.h>
11 #include <dt-bindings/interconnect/fsl,imx8mp.h>
12 #include <dt-bindings/interrupt-controller/arm-gic.h>
13 #include <dt-bindings/thermal/thermal.h>
15 #include "imx8mp-pinfunc.h"
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/linux/drivers/iio/adc/
H A Dti-ads131e08.c1 // SPDX-License-Identifier: GPL-2.0
3 * Texas Instruments ADS131E0x 4-, 6- and 8-Channel ADCs
12 #include <linux/clk.h>
24 #include <linux/spi/spi.h>
92 struct spi_device *spi; member
94 struct clk *adc_clk;
166 ret = spi_write_then_read(st->spi, &cmd, 1, NULL, 0); in ads131e08_exec_cmd()
168 dev_err(&st->spi->dev, "Exec cmd(%02x) failed\n", cmd); in ads131e08_exec_cmd()
178 .tx_buf = &st->tx_buf, in ads131e08_read_reg()
181 .value = st->sdecode_delay_us, in ads131e08_read_reg()
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/linux/drivers/net/wireless/st/cw1200/
H A Dcw1200_spi.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Mac80211 SPI driver for ST-Ericsson CW1200 device
9 * Copyright (c) 2010, ST-Ericsson
20 #include <linux/spi/spi.h>
25 #include <linux/platform_data/net-cw1200.h>
29 MODULE_DESCRIPTION("mac80211 ST-Ericsson CW1200 SPI driver");
31 MODULE_ALIAS("spi:cw1200_wlan_spi");
54 Hardware expects 32-bit data to be written as 16-bit BE words:
87 /* We have to byteswap if the SPI bus is limited to 8b operation in cw1200_spi_memcpy_fromio()
91 if (self->func->bits_per_word == 8) in cw1200_spi_memcpy_fromio()
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/linux/drivers/dma/
H A Dsun4i-dma.c1 // SPDX-License-Identifier: GPL-2.0-or-later
9 #include <linux/clk.h>
10 #include <linux/dma-mapping.h>
20 #include "virt-dma.h"
75 #define SUN4I_DDMA_PARA_DST_DATA_BLK_SIZE(n) (((n) - 1) << 24)
76 #define SUN4I_DDMA_PARA_DST_WAIT_CYCLES(n) (((n) - 1) << 16)
77 #define SUN4I_DDMA_PARA_SRC_DATA_BLK_SIZE(n) (((n) - 1) << 8)
78 #define SUN4I_DDMA_PARA_SRC_WAIT_CYCLES(n) (((n) - 1) << 0)
113 #define SUN4I_NDMA_NR_MAX_VCHANS (29 * 2 - 1)
119 * working with the SPI driver and seem to make it behave correctly */
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/linux/sound/soc/codecs/
H A Drt5677-spi.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * rt5677-spi.c -- RT5677 ALSA SoC audio codec driver
11 #include <linux/spi/spi.h>
23 #include <linux/clk.h>
30 #include "rt5677-spi.h"
38 /* The AddressPhase and DataPhase of SPI commands are MSB first on the wire.
39 * DataPhase word size of 16-bit commands is 2 bytes.
40 * DataPhase word size of 32-bit commands is 4 bytes.
42 * The DSP CPU is little-endian.
54 #define RT5677_MIC_BUF_BYTES ((u32)(RT5677_BUF_BYTES_TOTAL - \
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H A Dwm8995.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * wm8995.c -- WM8995 ALSA SoC Audio driver
19 #include <linux/spi/spi.h>
26 #include <sound/soc-dapm.h>
372 int src; member
400 regcache_mark_dirty(wm8995->regmap); \
414 static const DECLARE_TLV_DB_SCALE(digital_tlv, -7200, 75, 1);
415 static const DECLARE_TLV_DB_SCALE(in1lr_pga_tlv, -1650, 150, 0);
417 static const DECLARE_TLV_DB_SCALE(sidetone_tlv, -3600, 150, 0);
420 "Differential", "Single-ended IN1LN", "Single-ended IN1LP"
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/linux/arch/arm64/boot/dts/tesla/
H A Dfsd.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 * Tesla Full Self-Driving SoC device tree source
5 * Copyright (c) 2017-2022 Samsung Electronics Co., Ltd.
7 * Copyright (c) 2017-2022 Tesla, Inc.
11 #include <dt-bindings/clock/fsd-clk.h>
12 #include <dt-bindings/interrupt-controller/arm-gic.h>
16 interrupt-parent = <&gic>;
17 #address-cells = <2>;
18 #size-cells = <2>;
38 #address-cells = <2>;
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/linux/sound/pci/hda/
H A Dcs35l41_hda.c1 // SPDX-License-Identifier: GPL-2.0
15 #include <linux/spi/spi.h>
37 #define CS35L41_UUID "50d90cdc-3de4-4f18-b528-c7fe3b71f40d"
84 { CS35L41_DSP_CLK_CTRL, 0x00000003 }, // DSP CLK EN
88 { CS35L41_SP_FORMAT, 0x20200200 }, // 32 bits RX/TX slots, I2S, clk consumer
89 { CS35L41_SP_HIZ_CTRL, 0x00000002 }, // Hi-Z unused
93 { CS35L41_ASP_TX1_SRC, 0x00000018 }, // ASPTX1 SRC = VMON
94 { CS35L41_ASP_TX2_SRC, 0x00000019 }, // ASPTX2 SRC = IMON
95 { CS35L41_ASP_TX3_SRC, 0x00000032 }, // ASPTX3 SRC = ERRVOL
96 { CS35L41_ASP_TX4_SRC, 0x00000033 }, // ASPTX4 SRC = CLASSH_TGT
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/linux/drivers/mtd/devices/
H A Dst_spi_fsm.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * st_spi_fsm.c - ST Fast Sequence Mode (FSM) Serial Flash Controller
7 * Copyright (C) 2010-2014 STMicroelectronics Limited
18 #include <linux/mtd/spi-nor.h>
23 #include <linux/clk.h>
28 * FSM SPI Controller Registers
156 * FSM SPI Instruction Opcodes
170 * FSM SPI Instructions (== opcode + operand).
261 struct clk *clk; member
286 /* SPI Flash Device Table */
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