1 // SPDX-License-Identifier: GPL-2.0-only
3  * st_spi_fsm.c	- ST Fast Sequence Mode (FSM) Serial Flash Controller
7  * Copyright (C) 2010-2014 STMicroelectronics Limited
18 #include <linux/mtd/spi-nor.h>
23 #include <linux/clk.h>
28  * FSM SPI Controller Registers
156  * FSM SPI Instruction Opcodes
170  * FSM SPI Instructions (== opcode + operand).
261 	struct clk              *clk;  member
286 /* SPI Flash Device Table */
318 	 * ST Microelectronics/Numonyx --
338 	 *     - Support for 'FLASH_FLAG_WRITE_1_4_4' is omitted for devices
375 	 *     - 256KiB and 64KiB sector variants (identified by ext. JEDEC)
393 	 *     - 256KiB and 64KiB sector variants (identified by ext. JEDEC)
394 	 *     - RESET# signal supported by die but not bristled out on all
397 	 *     - Supports 'DYB' sector protection. Depending on variant, sectors
398 	 *       may default to locked state on power-on.
412 	/* Winbond -- w25x "blocks" are 64K, "sectors" are 4KiB */
423 	/* Winbond -- w25q "blocks" are 64K, "sectors" are 4KiB */
478 /* N25Q 3-byte Address READ configurations
479  *	- 'FAST' variants configured for 8 dummy cycles.
485  * force until the device is power-cycled.  Since the SPIBoot controller is
486  * hard-wired to use 8 dummy cycles, we must configure the device to also use 8
499 /* N25Q 4-byte Address READ configurations
500  *	- use special 4-byte address READ commands (reduces overheads, and
502  *	- 'FAST' variants configured for 8 dummy cycles (see note above.)
521 	seq->seq_opc[0] = (SEQ_OPC_PADS_1 |  in stfsm_mx25_en_32bit_addr_seq()
526 	seq->seq[0] = STFSM_INST_CMD1;  in stfsm_mx25_en_32bit_addr_seq()
527 	seq->seq[1] = STFSM_INST_WAIT;  in stfsm_mx25_en_32bit_addr_seq()
528 	seq->seq[2] = STFSM_INST_STOP;  in stfsm_mx25_en_32bit_addr_seq()
530 	seq->seq_cfg = (SEQ_CFG_PADS_1 |  in stfsm_mx25_en_32bit_addr_seq()
545  * S25FLxxxS devices provide three ways of supporting 32-bit addressing: Bank
546  * Register, Extended Address Modes, and a 32-bit address command set.  The
547  * 32-bit address command set is used here, since it avoids any problems with
682 	seq->seq_opc[0] = (SEQ_OPC_PADS_1 | SEQ_OPC_CYCLES(8) |  in stfsm_n25q_en_32bit_addr_seq()
684 	seq->seq_opc[1] = (SEQ_OPC_PADS_1 | SEQ_OPC_CYCLES(8) |  in stfsm_n25q_en_32bit_addr_seq()
688 	seq->seq[0] = STFSM_INST_CMD2;  in stfsm_n25q_en_32bit_addr_seq()
689 	seq->seq[1] = STFSM_INST_CMD1;  in stfsm_n25q_en_32bit_addr_seq()
690 	seq->seq[2] = STFSM_INST_WAIT;  in stfsm_n25q_en_32bit_addr_seq()
691 	seq->seq[3] = STFSM_INST_STOP;  in stfsm_n25q_en_32bit_addr_seq()
693 	seq->seq_cfg = (SEQ_CFG_PADS_1 |  in stfsm_n25q_en_32bit_addr_seq()
704 	return readl(fsm->base + SPI_FAST_SEQ_STA) & 0x10;  in stfsm_is_idle()
709 	return (readl(fsm->base + SPI_FAST_SEQ_STA) >> 5) & 0x7f;  in stfsm_fifo_available()
715 	void __iomem *dst = fsm->base + SPI_FAST_SEQ_TRANSFER_SIZE;  in stfsm_load_seq()
716 	const uint32_t *src = (const uint32_t *)seq;  in stfsm_load_seq()  local
717 	int words = sizeof(*seq) / sizeof(*src);  in stfsm_load_seq()
721 	while (words--) {  in stfsm_load_seq()
722 		writel(*src, dst);  in stfsm_load_seq()
723 		src++;  in stfsm_load_seq()
745 	dev_err(fsm->dev, "timeout on sequence completion\n");  in stfsm_wait_seq()
754 	dev_dbg(fsm->dev, "Reading %d bytes from FIFO\n", size);  in stfsm_read_fifo()
766 		remaining -= words;  in stfsm_read_fifo()
768 		readsl(fsm->base + SPI_FAST_SEQ_DATA_REG, buf, words);  in stfsm_read_fifo()
781  * SPI_FAST_SEQ_STA register only reports the number of complete 32-bit words
783  * complete 32-bit words.
787  *     1. Read any complete 32-bit words from the FIFO, as reported by the
792  *        sequence is used to load one byte at a time, until a complete 32-bit
796  *     of bits.  However, since there are no known use-cases that leave
804 	/* 1. Clear any 32-bit words */  in stfsm_clear_fifo()
808 			readl(fsm->base + SPI_FAST_SEQ_DATA_REG);  in stfsm_clear_fifo()
809 		dev_dbg(fsm->dev, "cleared %d words from FIFO\n", words);  in stfsm_clear_fifo()
814 	 *    - Load the FIFO, one byte at a time, until a complete 32-bit word  in stfsm_clear_fifo()
823 	/*    - A single word must be available now */  in stfsm_clear_fifo()
825 		dev_err(fsm->dev, "failed to clear bytes from the data FIFO\n");  in stfsm_clear_fifo()
829 	/*    - Read the 32-bit word */  in stfsm_clear_fifo()
830 	readl(fsm->base + SPI_FAST_SEQ_DATA_REG);  in stfsm_clear_fifo()
832 	dev_dbg(fsm->dev, "cleared %d byte(s) from the data FIFO\n", 4 - i);  in stfsm_clear_fifo()
840 	dev_dbg(fsm->dev, "writing %d bytes to FIFO\n", size);  in stfsm_write_fifo()
844 	writesl(fsm->base + SPI_FAST_SEQ_DATA_REG, buf, words);  in stfsm_write_fifo()
851 	struct stfsm_seq *seq = &fsm->stfsm_seq_en_32bit_addr;  in stfsm_enter_32bit_addr()
854 	seq->seq_opc[0] = (SEQ_OPC_PADS_1 |  in stfsm_enter_32bit_addr()
874 	seq->seq_opc[0] = (SEQ_OPC_PADS_1 |  in stfsm_wait_busy()
896 		if ((fsm->configuration & CFG_S25FL_CHECK_ERROR_FLAGS) &&  in stfsm_wait_busy()
903 			writel(seq->seq_cfg, fsm->base + SPI_FAST_SEQ_CFG);  in stfsm_wait_busy()
908 	dev_err(fsm->dev, "timeout on wait_busy\n");  in stfsm_wait_busy()
921 	dev_dbg(fsm->dev, "read 'status' register [0x%02x], %d byte(s)\n",  in stfsm_read_status()
926 	seq->seq_opc[0] = (SEQ_OPC_PADS_1 | SEQ_OPC_CYCLES(8) |  in stfsm_read_status()
946 	dev_dbg(fsm->dev,  in stfsm_write_status()
948 		" %s wait-busy\n", cmd, bytes, data, wait_busy ? "with" : "no");  in stfsm_write_status()
952 	seq->seq_opc[1] = (SEQ_OPC_PADS_1 | SEQ_OPC_CYCLES(8) |  in stfsm_write_status()
955 	seq->status = (uint32_t)data | STA_PADS_1 | STA_CSDEASSERT;  in stfsm_write_status()
956 	seq->seq[2] = (bytes == 1) ? STFSM_INST_STA_WR1 : STFSM_INST_STA_WR1_2;  in stfsm_write_status()
969  * SoC reset on 'boot-from-spi' systems
972  * for a period of time (e.g. 'Erase Sector', 'Quad Enable', and 'Enter 32-bit
973  * Addr' commands).  On boot-from-spi systems, it is important to consider what
975  * assumes that Flash device is in its default reset state, 24-bit address mode,
977  * on-board logic/controller to force a device POR in response to a SoC-level
983  * other modes of operation (e.g. 32-bit addressing), options are often
991 	if (fsm->reset_signal && fsm->info->flags & FLASH_FLAG_RESET)  in stfsm_can_handle_soc_reset()
994 	/* Board-level logic forces a power-on-reset */  in stfsm_can_handle_soc_reset()
995 	if (fsm->reset_por)  in stfsm_can_handle_soc_reset()
1006 	int addr1_cycles = fsm->info->flags & FLASH_FLAG_32BIT_ADDR ? 16 : 8;  in stfsm_prepare_erasesec_seq()
1008 	seq->addr_cfg = (ADR_CFG_CYCLES_ADD1(addr1_cycles) |  in stfsm_prepare_erasesec_seq()
1021 	int flags = fsm->info->flags;  in stfsm_search_seq_rw_configs()
1023 	for (config = cfgs; config->cmd != 0; config++)  in stfsm_search_seq_rw_configs()
1024 		if ((config->flags & flags) == config->flags)  in stfsm_search_seq_rw_configs()
1041 	seq->seq_opc[i++] = (SEQ_OPC_PADS_1 |  in stfsm_prepare_rw_seq()
1043 			     SEQ_OPC_OPCODE(cfg->cmd));  in stfsm_prepare_rw_seq()
1046 	if (cfg->write)  in stfsm_prepare_rw_seq()
1047 		seq->seq_opc[i++] = (SEQ_OPC_PADS_1 |  in stfsm_prepare_rw_seq()
1052 	/* Address configuration (24 or 32-bit addresses) */  in stfsm_prepare_rw_seq()
1053 	addr1_cycles  = (fsm->info->flags & FLASH_FLAG_32BIT_ADDR) ? 16 : 8;  in stfsm_prepare_rw_seq()
1054 	addr1_cycles /= cfg->addr_pads;  in stfsm_prepare_rw_seq()
1055 	addr2_cycles  = 16 / cfg->addr_pads;  in stfsm_prepare_rw_seq()
1056 	seq->addr_cfg = ((addr1_cycles & 0x3f) << 0 |	/* ADD1 cycles */  in stfsm_prepare_rw_seq()
1057 			 (cfg->addr_pads - 1) << 6 |	/* ADD1 pads */  in stfsm_prepare_rw_seq()
1059 			 ((cfg->addr_pads - 1) << 22));	/* ADD2 pads */  in stfsm_prepare_rw_seq()
1062 	seq->seq_cfg = ((cfg->data_pads - 1) << 16 |  in stfsm_prepare_rw_seq()
1065 	if (!cfg->write)  in stfsm_prepare_rw_seq()
1066 		seq->seq_cfg |= SEQ_CFG_READNOTWRITE;  in stfsm_prepare_rw_seq()
1069 	seq->mode = ((cfg->mode_data & 0xff) << 0 |	/* data */  in stfsm_prepare_rw_seq()
1070 		     (cfg->mode_cycles & 0x3f) << 16 |	/* cycles */  in stfsm_prepare_rw_seq()
1071 		     (cfg->addr_pads - 1) << 22);	/* pads */  in stfsm_prepare_rw_seq()
1074 	seq->dummy = ((cfg->dummy_cycles & 0x3f) << 16 |	/* cycles */  in stfsm_prepare_rw_seq()
1075 		      (cfg->addr_pads - 1) << 22);		/* pads */  in stfsm_prepare_rw_seq()
1080 	if (cfg->write)  in stfsm_prepare_rw_seq()
1081 		seq->seq[i++] = STFSM_INST_CMD2;  in stfsm_prepare_rw_seq()
1083 	seq->seq[i++] = STFSM_INST_CMD1;  in stfsm_prepare_rw_seq()
1085 	seq->seq[i++] = STFSM_INST_ADD1;  in stfsm_prepare_rw_seq()
1086 	seq->seq[i++] = STFSM_INST_ADD2;  in stfsm_prepare_rw_seq()
1088 	if (cfg->mode_cycles)  in stfsm_prepare_rw_seq()
1089 		seq->seq[i++] = STFSM_INST_MODE;  in stfsm_prepare_rw_seq()
1091 	if (cfg->dummy_cycles)  in stfsm_prepare_rw_seq()
1092 		seq->seq[i++] = STFSM_INST_DUMMY;  in stfsm_prepare_rw_seq()
1094 	seq->seq[i++] =  in stfsm_prepare_rw_seq()
1095 		cfg->write ? STFSM_INST_DATA_WRITE : STFSM_INST_DATA_READ;  in stfsm_prepare_rw_seq()
1096 	seq->seq[i++] = STFSM_INST_STOP;  in stfsm_prepare_rw_seq()
1107 		dev_err(fsm->dev, "failed to find suitable config\n");  in stfsm_search_prepare_rw_seq()
1108 		return -EINVAL;  in stfsm_search_prepare_rw_seq()
1119 	uint32_t flags = fsm->info->flags;  in stfsm_prepare_rwe_seqs_default()
1123 	ret = stfsm_search_prepare_rw_seq(fsm, &fsm->stfsm_seq_read,  in stfsm_prepare_rwe_seqs_default()
1126 		dev_err(fsm->dev,  in stfsm_prepare_rwe_seqs_default()
1133 	ret = stfsm_search_prepare_rw_seq(fsm, &fsm->stfsm_seq_write,  in stfsm_prepare_rwe_seqs_default()
1136 		dev_err(fsm->dev,  in stfsm_prepare_rwe_seqs_default()
1150 	uint32_t flags = fsm->info->flags;  in stfsm_mx25_config()
1164 	 * Configure 32-bit Address Support  in stfsm_mx25_config()
1168 		stfsm_mx25_en_32bit_addr_seq(&fsm->stfsm_seq_en_32bit_addr);  in stfsm_mx25_config()
1171 		if (soc_reset || !fsm->booted_from_spi)  in stfsm_mx25_config()
1172 			/* If we can handle SoC resets, we enable 32-bit address  in stfsm_mx25_config()
1177 			/* Else, enable/disable 32-bit addressing before/after  in stfsm_mx25_config()
1179 			fsm->configuration = (CFG_READ_TOGGLE_32BIT_ADDR |  in stfsm_mx25_config()
1186 	data_pads = ((fsm->stfsm_seq_read.seq_cfg >> 16) & 0x3) + 1;  in stfsm_mx25_config()
1208 	uint32_t flags = fsm->info->flags;  in stfsm_n25q_config()
1215 		ret = stfsm_search_prepare_rw_seq(fsm, &fsm->stfsm_seq_read,  in stfsm_n25q_config()
1218 		ret = stfsm_search_prepare_rw_seq(fsm, &fsm->stfsm_seq_read,  in stfsm_n25q_config()
1221 		dev_err(fsm->dev,  in stfsm_n25q_config()
1228 	ret = stfsm_search_prepare_rw_seq(fsm, &fsm->stfsm_seq_write,  in stfsm_n25q_config()
1231 		dev_err(fsm->dev,  in stfsm_n25q_config()
1240 	/* Configure 32-bit address support */  in stfsm_n25q_config()
1242 		stfsm_n25q_en_32bit_addr_seq(&fsm->stfsm_seq_en_32bit_addr);  in stfsm_n25q_config()
1245 		if (soc_reset || !fsm->booted_from_spi) {  in stfsm_n25q_config()
1247 			 * If we can handle SoC resets, we enable 32-bit  in stfsm_n25q_config()
1256 			fsm->configuration = (CFG_WRITE_TOGGLE_32BIT_ADDR |  in stfsm_n25q_config()
1273 	seq->seq_opc[1] = (SEQ_OPC_PADS_1 |  in stfsm_s25fl_prepare_erasesec_seq_32()
1277 	seq->addr_cfg = (ADR_CFG_CYCLES_ADD1(16) |  in stfsm_s25fl_prepare_erasesec_seq_32()
1388 	struct flash_info *info = fsm->info;  in stfsm_s25fl_config()
1389 	uint32_t flags = info->flags;  in stfsm_s25fl_config()
1400 		 * 32-bit address command set  in stfsm_s25fl_config()
1402 		ret = stfsm_search_prepare_rw_seq(fsm, &fsm->stfsm_seq_read,  in stfsm_s25fl_config()
1407 		ret = stfsm_search_prepare_rw_seq(fsm, &fsm->stfsm_seq_write,  in stfsm_s25fl_config()
1415 		/* Use default configurations for 24-bit addressing */  in stfsm_s25fl_config()
1423 	 * unlock sectors if necessary (some variants power-on with sectors  in stfsm_s25fl_config()
1428 		for (offs = 0; offs < info->sector_size * info->n_sectors;) {  in stfsm_s25fl_config()
1434 			if ((offs < info->sector_size * 2) ||  in stfsm_s25fl_config()
1435 			    (offs >= (info->sector_size - info->n_sectors * 4)))  in stfsm_s25fl_config()
1444 	data_pads = ((fsm->stfsm_seq_read.seq_cfg >> 16) & 0x3) + 1;  in stfsm_s25fl_config()
1470 	fsm->configuration |= CFG_S25FL_CHECK_ERROR_FLAGS;  in stfsm_s25fl_config()
1489 	data_pads = ((fsm->stfsm_seq_read.seq_cfg >> 16) & 0x3) + 1;  in stfsm_w25q_config()
1516 	struct stfsm_seq *seq = &fsm->stfsm_seq_read;  in stfsm_read()
1526 	dev_dbg(fsm->dev, "reading %d bytes from 0x%08x\n", size, offset);  in stfsm_read()
1528 	/* Enter 32-bit address mode, if required */  in stfsm_read()
1529 	if (fsm->configuration & CFG_READ_TOGGLE_32BIT_ADDR)  in stfsm_read()
1533 	data_pads = ((seq->seq_cfg >> 16) & 0x3) + 1;  in stfsm_read()
1534 	read_mask = (data_pads << 2) - 1;  in stfsm_read()
1536 	/* Handle non-aligned buf */  in stfsm_read()
1539 	/* Handle non-aligned size */  in stfsm_read()
1544 	seq->data_size = TRANSFER_SIZE(size_ub);  in stfsm_read()
1545 	seq->addr1 = (offset >> 16) & 0xffff;  in stfsm_read()
1546 	seq->addr2 = offset & 0xffff;  in stfsm_read()
1558 	/* Handle non-aligned buf */  in stfsm_read()
1567 	/* Exit 32-bit address mode, if required */  in stfsm_read()
1568 	if (fsm->configuration & CFG_READ_TOGGLE_32BIT_ADDR)  in stfsm_read()
1577 	struct stfsm_seq *seq = &fsm->stfsm_seq_write;  in stfsm_write()
1590 	dev_dbg(fsm->dev, "writing %d bytes to 0x%08x\n", size, offset);  in stfsm_write()
1592 	/* Enter 32-bit address mode, if required */  in stfsm_write()
1593 	if (fsm->configuration & CFG_WRITE_TOGGLE_32BIT_ADDR)  in stfsm_write()
1597 	data_pads = ((seq->seq_cfg >> 16) & 0x3) + 1;  in stfsm_write()
1598 	write_mask = (data_pads << 2) - 1;  in stfsm_write()
1600 	/* Handle non-aligned buf */  in stfsm_write()
1608 	/* Handle non-aligned size */  in stfsm_write()
1613 	seq->data_size = TRANSFER_SIZE(size_ub);  in stfsm_write()
1614 	seq->addr1 = (offset >> 16) & 0xffff;  in stfsm_write()
1615 	seq->addr2 = offset & 0xffff;  in stfsm_write()
1620 	writel(0x00040000, fsm->base + SPI_FAST_SEQ_CFG);  in stfsm_write()
1626 	if (fsm->fifo_dir_delay == 0)  in stfsm_write()
1627 		readl(fsm->base + SPI_FAST_SEQ_CFG);  in stfsm_write()
1629 		udelay(fsm->fifo_dir_delay);  in stfsm_write()
1638 	/* Handle non-aligned size */  in stfsm_write()
1655 	if (ret && fsm->configuration & CFG_S25FL_CHECK_ERROR_FLAGS)  in stfsm_write()
1658 	/* Exit 32-bit address mode, if required */  in stfsm_write()
1659 	if (fsm->configuration & CFG_WRITE_TOGGLE_32BIT_ADDR)  in stfsm_write()
1672 	struct stfsm *fsm = dev_get_drvdata(mtd->dev.parent);  in stfsm_mtd_read()
1675 	dev_dbg(fsm->dev, "%s from 0x%08x, len %zd\n",  in stfsm_mtd_read()
1678 	mutex_lock(&fsm->lock);  in stfsm_mtd_read()
1687 		len -= bytes;  in stfsm_mtd_read()
1692 	mutex_unlock(&fsm->lock);  in stfsm_mtd_read()
1702 	dev_dbg(fsm->dev, "erasing sector at 0x%08x\n", offset);  in stfsm_erase_sector()
1704 	/* Enter 32-bit address mode, if required */  in stfsm_erase_sector()
1705 	if (fsm->configuration & CFG_ERASESEC_TOGGLE_32BIT_ADDR)  in stfsm_erase_sector()
1708 	seq->addr1 = (offset >> 16) & 0xffff;  in stfsm_erase_sector()
1709 	seq->addr2 = offset & 0xffff;  in stfsm_erase_sector()
1717 	if (ret && fsm->configuration & CFG_S25FL_CHECK_ERROR_FLAGS)  in stfsm_erase_sector()
1720 	/* Exit 32-bit address mode, if required */  in stfsm_erase_sector()
1721 	if (fsm->configuration & CFG_ERASESEC_TOGGLE_32BIT_ADDR)  in stfsm_erase_sector()
1731 	dev_dbg(fsm->dev, "erasing chip\n");  in stfsm_erase_chip()
1748 	struct stfsm *fsm = dev_get_drvdata(mtd->dev.parent);  in stfsm_mtd_write()
1755 	dev_dbg(fsm->dev, "%s to 0x%08x, len %zd\n", __func__, (u32)to, len);  in stfsm_mtd_write()
1760 	mutex_lock(&fsm->lock);  in stfsm_mtd_write()
1764 		bytes = min_t(size_t, FLASH_PAGESIZE - page_offs, len);  in stfsm_mtd_write()
1771 		len -= bytes;  in stfsm_mtd_write()
1774 		/* We are now page-aligned */  in stfsm_mtd_write()
1782 	mutex_unlock(&fsm->lock);  in stfsm_mtd_write()
1793 	struct stfsm *fsm = dev_get_drvdata(mtd->dev.parent);  in stfsm_mtd_erase()
1797 	dev_dbg(fsm->dev, "%s at 0x%llx, len %lld\n", __func__,  in stfsm_mtd_erase()
1798 		(long long)instr->addr, (long long)instr->len);  in stfsm_mtd_erase()
1800 	addr = instr->addr;  in stfsm_mtd_erase()
1801 	len = instr->len;  in stfsm_mtd_erase()
1803 	mutex_lock(&fsm->lock);  in stfsm_mtd_erase()
1805 	/* Whole-chip erase? */  in stfsm_mtd_erase()
1806 	if (len == mtd->size) {  in stfsm_mtd_erase()
1816 			addr += mtd->erasesize;  in stfsm_mtd_erase()
1817 			len -= mtd->erasesize;  in stfsm_mtd_erase()
1821 	mutex_unlock(&fsm->lock);  in stfsm_mtd_erase()
1826 	mutex_unlock(&fsm->lock);  in stfsm_mtd_erase()
1857 	 * string for after vendor-specific data, after the three bytes  in stfsm_jedec_probe()
1862 	dev_dbg(fsm->dev, "JEDEC =  0x%08x [%5ph]\n", jedec, id);  in stfsm_jedec_probe()
1864 	for (info = flash_types; info->name; info++) {  in stfsm_jedec_probe()
1865 		if (info->jedec_id == jedec) {  in stfsm_jedec_probe()
1866 			if (info->ext_id && info->ext_id != ext_jedec)  in stfsm_jedec_probe()
1871 	dev_err(fsm->dev, "Unrecognized JEDEC id %06x\n", jedec);  in stfsm_jedec_probe()
1881 	while (--timeout) {  in stfsm_set_mode()
1882 		ret = readl(fsm->base + SPI_STA_MODE_CHANGE);  in stfsm_set_mode()
1889 		return -EBUSY;  in stfsm_set_mode()
1891 	writel(mode, fsm->base + SPI_MODESELECT);  in stfsm_set_mode()
1901 	emi_freq = clk_get_rate(fsm->clk);  in stfsm_set_freq()
1904 	 * Calculate clk_div - values between 2 and 128  in stfsm_set_freq()
1920 		fsm->fifo_dir_delay = 0;  in stfsm_set_freq()
1922 		fsm->fifo_dir_delay = 1;  in stfsm_set_freq()
1924 		fsm->fifo_dir_delay = DIV_ROUND_UP(clk_div, 10);  in stfsm_set_freq()
1926 	dev_dbg(fsm->dev, "emi_clk = %uHZ, spi_freq = %uHZ, clk_div = %u\n",  in stfsm_set_freq()
1929 	writel(clk_div, fsm->base + SPI_CLOCKDIV);  in stfsm_set_freq()
1937 	writel(SEQ_CFG_SWRESET, fsm->base + SPI_FAST_SEQ_CFG);  in stfsm_init()
1939 	writel(0, fsm->base + SPI_FAST_SEQ_CFG);  in stfsm_init()
1954 	       fsm->base + SPI_CONFIGDATA);  in stfsm_init()
1955 	writel(STFSM_DEFAULT_WR_TIME, fsm->base + SPI_STATUS_WR_TIME_REG);  in stfsm_init()
1962 	writel(0x00000001, fsm->base + SPI_PROGRAM_ERASE_TIME);  in stfsm_init()
1973 	struct device_node *np = pdev->dev.of_node;  in stfsm_fetch_platform_configs()
1980 	/* Booting from SPI NOR Flash is the default */  in stfsm_fetch_platform_configs()
1981 	fsm->booted_from_spi = true;  in stfsm_fetch_platform_configs()
1987 	fsm->reset_signal = of_property_read_bool(np, "st,reset-signal");  in stfsm_fetch_platform_configs()
1989 	fsm->reset_por = of_property_read_bool(np, "st,reset-por");  in stfsm_fetch_platform_configs()
1992 	ret = of_property_read_u32(np, "st,boot-device-reg", &boot_device_reg);  in stfsm_fetch_platform_configs()
1996 	/* Boot device value when booted from SPI NOR */  in stfsm_fetch_platform_configs()
1997 	ret = of_property_read_u32(np, "st,boot-device-spi", &boot_device_spi);  in stfsm_fetch_platform_configs()
2006 		fsm->booted_from_spi = false;  in stfsm_fetch_platform_configs()
2011 	dev_warn(&pdev->dev,  in stfsm_fetch_platform_configs()
2012 		 "failed to fetch boot device, assuming boot from SPI\n");  in stfsm_fetch_platform_configs()
2017 	struct device_node *np = pdev->dev.of_node;  in stfsm_probe()
2023 		dev_err(&pdev->dev, "No DT found\n");  in stfsm_probe()
2024 		return -EINVAL;  in stfsm_probe()
2027 	fsm = devm_kzalloc(&pdev->dev, sizeof(*fsm), GFP_KERNEL);  in stfsm_probe()
2029 		return -ENOMEM;  in stfsm_probe()
2031 	fsm->dev = &pdev->dev;  in stfsm_probe()
2035 	fsm->base = devm_platform_ioremap_resource(pdev, 0);  in stfsm_probe()
2036 	if (IS_ERR(fsm->base))  in stfsm_probe()
2037 		return PTR_ERR(fsm->base);  in stfsm_probe()
2039 	fsm->clk = devm_clk_get_enabled(&pdev->dev, NULL);  in stfsm_probe()
2040 	if (IS_ERR(fsm->clk)) {  in stfsm_probe()
2041 		dev_err(fsm->dev, "Couldn't find EMI clock.\n");  in stfsm_probe()
2042 		return PTR_ERR(fsm->clk);  in stfsm_probe()
2045 	mutex_init(&fsm->lock);  in stfsm_probe()
2049 		dev_err(&pdev->dev, "Failed to initialise FSM Controller\n");  in stfsm_probe()
2055 	/* Detect SPI FLASH device */  in stfsm_probe()
2058 		return -ENODEV;  in stfsm_probe()
2059 	fsm->info = info;  in stfsm_probe()
2062 	if (info->sector_size * info->n_sectors > 0x1000000)  in stfsm_probe()
2063 		info->flags |= FLASH_FLAG_32BIT_ADDR;  in stfsm_probe()
2069 	if (info->config)  in stfsm_probe()
2070 		ret = info->config(fsm);  in stfsm_probe()
2076 	fsm->mtd.name		= info->name;  in stfsm_probe()
2077 	fsm->mtd.dev.parent	= &pdev->dev;  in stfsm_probe()
2078 	mtd_set_of_node(&fsm->mtd, np);  in stfsm_probe()
2079 	fsm->mtd.type		= MTD_NORFLASH;  in stfsm_probe()
2080 	fsm->mtd.writesize	= 4;  in stfsm_probe()
2081 	fsm->mtd.writebufsize	= fsm->mtd.writesize;  in stfsm_probe()
2082 	fsm->mtd.flags		= MTD_CAP_NORFLASH;  in stfsm_probe()
2083 	fsm->mtd.size		= info->sector_size * info->n_sectors;  in stfsm_probe()
2084 	fsm->mtd.erasesize	= info->sector_size;  in stfsm_probe()
2086 	fsm->mtd._read  = stfsm_mtd_read;  in stfsm_probe()
2087 	fsm->mtd._write = stfsm_mtd_write;  in stfsm_probe()
2088 	fsm->mtd._erase = stfsm_mtd_erase;  in stfsm_probe()
2090 	dev_info(&pdev->dev,  in stfsm_probe()
2093 		info->name,  in stfsm_probe()
2094 		(long long)fsm->mtd.size, (long long)(fsm->mtd.size >> 20),  in stfsm_probe()
2095 		fsm->mtd.erasesize, (fsm->mtd.erasesize >> 10));  in stfsm_probe()
2097 	return mtd_device_register(&fsm->mtd, NULL, 0);  in stfsm_probe()
2104 	WARN_ON(mtd_device_unregister(&fsm->mtd));  in stfsm_remove()
2112 	clk_disable_unprepare(fsm->clk);  in stfsmfsm_suspend()
2121 	return clk_prepare_enable(fsm->clk);  in stfsmfsm_resume()
2128 	{ .compatible = "st,spi-fsm", },
2137 		.name	= "st-spi-fsm",
2145 MODULE_DESCRIPTION("ST SPI FSM driver");