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/linux/drivers/spi/
H A Dspi-stm32.c1 // SPDX-License-Identifier: GPL-2.0
3 // STMicroelectronics STM32 SPI Controller driver
5 // Copyright (C) 2017, STMicroelectronics - All Rights Reserved
12 #include <linux/dma-mapping.h>
23 #include <linux/spi/spi.h>
27 /* STM32F4/7 SPI registers */
83 /* STM32F4 SPI Baud Rate min/max divisor */
87 /* STM32H7 SPI registers */
162 /* STM32MP25 SPI registers bit fields */
176 /* STM32H7 SPI Master Baud Rate min/max divisor */
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H A Dspi-davinci.c1 // SPDX-License-Identifier: GPL-2.0-or-later
17 #include <linux/dma-mapping.h>
19 #include <linux/spi/spi.h>
20 #include <linux/spi/spi_bitbang.h>
87 /* SPI Controller registers */
111 * struct davinci_spi_platform_data - Platform data for SPI master device on DaVinci
113 * @version: version of the SPI IP. Different DaVinci devices have slightly
115 * @num_chipselect: number of chipselects supported by this SPI master
116 * @intr_line: interrupt line used to connect the SPI IP to the ARM interrupt
119 * @cshold_bug: set this to true if the SPI controller on your chip requires
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H A Dspi-geni-qcom.c1 // SPDX-License-Identifier: GPL-2.0
2 // Copyright (c) 2017-2018, The Linux foundation. All rights reserved.
6 #include <linux/dma-mapping.h>
7 #include <linux/dma/qcom-gpi-dma.h>
16 #include <linux/soc/qcom/geni-se.h>
17 #include <linux/spi/spi.h>
20 /* SPI SE specific registers and respective register fields */
59 /* M_CMD OP codes for SPI */
66 /* M_CMD params for SPI */
109 struct geni_se *se = &mas->se; in spi_slv_setup()
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H A Dspi-imx.c1 // SPDX-License-Identifier: GPL-2.0+
2 // Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
11 #include <linux/dma-mapping.h>
25 #include <linux/spi/spi.h>
30 #include <linux/dma/imx-dma.h>
80 int (*prepare_transfer)(struct spi_imx_data *spi_imx, struct spi_device *spi,
114 void __iomem *base; member
153 return d->devtype_data->devtype == IMX27_CSPI; in is_imx27_cspi()
158 return d->devtype_data->devtype == IMX35_CSPI; in is_imx35_cspi()
163 return d->devtype_data->devtype == IMX51_ECSPI; in is_imx51_ecspi()
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H A Dspi-altera-dfl.c1 // SPDX-License-Identifier: GPL-2.0
3 // DFL bus driver for Altera SPI Master
19 #include <linux/io-64-nonatomic-lo-hi.h>
21 #include <linux/spi/spi.h>
22 #include <linux/spi/altera.h>
52 void __iomem *base = context; in indirect_bus_reg_read() local
56 writeq((reg >> 2) | INDIRECT_RD, base + INDIRECT_ADDR); in indirect_bus_reg_read()
59 while ((readq(base + INDIRECT_ADDR) & INDIRECT_RD) && in indirect_bus_reg_read()
65 return -ETIME; in indirect_bus_reg_read()
68 v = readq(base + INDIRECT_RD_DATA); in indirect_bus_reg_read()
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H A Dspi-meson-spicc.c2 * Driver for Amlogic Meson SPI communication controller (SPICC)
7 * SPDX-License-Identifier: GPL-2.0+
12 #include <linux/clk-provider.h>
19 #include <linux/spi/spi.h>
24 #include <linux/dma-mapping.h>
31 * DMA achieves a transfer with one or more SPI bursts, each SPI burst is made
40 * - 64 bits per word
41 * - The transfer length in word must be multiples of the dma_burst_len, and
43 * into several SPI bursts by this driver
77 #define SPICC_TH_EN BIT(1) /* TX FIFO Half-Full Interrupt */
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H A Dspi-intel-platform.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Intel PCH/PCU SPI flash platform driver.
5 * Copyright (C) 2016 - 2022, Intel Corporation
12 #include "spi-intel.h"
17 void __iomem *base; in intel_spi_platform_probe() local
19 info = dev_get_platdata(&pdev->dev); in intel_spi_platform_probe()
21 return -EINVAL; in intel_spi_platform_probe()
23 base = devm_platform_ioremap_resource(pdev, 0); in intel_spi_platform_probe()
24 if (IS_ERR(base)) in intel_spi_platform_probe()
25 return PTR_ERR(base); in intel_spi_platform_probe()
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H A Dspi-jcore.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * J-Core SPI controller driver
5 * Copyright (C) 2012-2016 Smart Energy Instruments, Inc.
16 #include <linux/spi/spi.h>
37 void __iomem *base; member
52 } while (--timeout); in jcore_spi_wait()
54 return -EBUSY; in jcore_spi_wait()
59 void __iomem *ctrl_reg = hw->base + CTRL_REG; in jcore_spi_program()
62 dev_err(hw->host->dev.parent, in jcore_spi_program()
65 writel(hw->cs_reg | hw->speed_reg, ctrl_reg); in jcore_spi_program()
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H A Dspi-rzv2h-rspi.c1 // SPDX-License-Identifier: GPL-2.0-or-later
22 #include <linux/spi/spi.h>
104 void __iomem *base; member
124 func(buf, rspi->base + RSPI_SPDR); \
131 type buf = func(rspi->base + RSPI_SPDR); \
148 tmp = (readl(rspi->base + reg_offs) & ~bit_mask) | value; in RZV2H_RSPI_TX()
149 writel(tmp, rspi->base + reg_offs); in RZV2H_RSPI_TX()
164 writeb(1, rspi->base + RSPI_SPFCR); in rzv2h_rspi_clear_fifos()
169 writew(RSPI_SPSRC_CLEAR, rspi->base + RSPI_SPSRC); in rzv2h_rspi_clear_all_irqs()
170 rspi->status = 0; in rzv2h_rspi_clear_all_irqs()
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H A Dspi-fsl-lpspi.c1 // SPDX-License-Identifier: GPL-2.0+
13 #include <linux/dma-mapping.h>
23 #include <linux/dma/imx-dma.h>
26 #include <linux/spi/spi.h>
27 #include <linux/spi/spi_bitbang.h>
36 #define FSL_LPSPI_MAX_EDMA_BYTES ((1 << 15) - 1)
111 void __iomem *base; member
160 { .compatible = "fsl,imx7ulp-spi", .data = &imx7ulp_lpspi_devtype_data,},
161 { .compatible = "fsl,imx93-spi", .data = &imx93_lpspi_devtype_data,},
162 { .compatible = "nxp,s32g2-lpspi", .data = &s32g_lpspi_devtype_data,},
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H A Dspi-sn-f-ospi.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Socionext SPI flash controller F_OSPI driver
15 #include <linux/spi/spi.h>
16 #include <linux/spi/spi-mem.h>
111 void __iomem *base; member
119 if (!op->dummy.nbytes) in f_ospi_get_dummy_cycle()
122 return (op->dummy.nbytes * 8) / op->dummy.buswidth; in f_ospi_get_dummy_cycle()
128 ospi->base + OSPI_IRQ); in f_ospi_clear_irq()
135 val = readl(ospi->base + OSPI_IRQ_STAT_EN); in f_ospi_enable_irq_status()
137 writel(val, ospi->base + OSPI_IRQ_STAT_EN); in f_ospi_enable_irq_status()
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H A Dspi-intel.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Intel PCH/PCU SPI flash driver.
5 * Copyright (C) 2016 - 2022, Intel Corporation
13 #include <linux/mtd/spi-nor.h>
15 #include <linux/spi/flash.h>
16 #include <linux/spi/spi.h>
17 #include <linux/spi/spi-mem.h>
19 #include "spi-intel.h"
21 /* Offsets are from @ispi->base */
60 /* Offset is from @ispi->pregs */
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H A Dspi-atcspi200.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Driver for Andes ATCSPI200 SPI Controller
22 #include <linux/spi/spi.h>
23 #include <linux/spi/spi-mem.h>
26 #define ATCSPI_TRANS_FMT 0x10 /* SPI transfer format register */
27 #define ATCSPI_TRANS_CTRL 0x20 /* SPI transfer control register */
28 #define ATCSPI_CMD 0x24 /* SPI command register */
29 #define ATCSPI_ADDR 0x28 /* SPI address register */
30 #define ATCSPI_DATA 0x2C /* SPI data register */
31 #define ATCSPI_CTRL 0x30 /* SPI control register */
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H A Dspi-orion.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Marvell Orion SPI controller driver
6 * Copyright (C) 2007-2008 Marvell Ltd.
14 #include <linux/spi/spi.h>
73 * have both is for managing the armada-370-spi case with old
94 void __iomem *base; member
110 return orion_spi->base + reg; in spi_reg()
135 static int orion_spi_baudrate_set(struct spi_device *spi, unsigned int speed) in orion_spi_baudrate_set() argument
144 orion_spi = spi_controller_get_devdata(spi->controller); in orion_spi_baudrate_set()
145 devdata = orion_spi->devdata; in orion_spi_baudrate_set()
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/linux/Documentation/devicetree/bindings/interrupt-controller/
H A Dmarvell,odmi-controller.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/interrupt-controller/marvell,odmi-controller.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
13 Some Marvell SoCs have an On-Die Message Interrupt (ODMI) controller which can
14 be used by on-board peripherals for MSI interrupts.
18 const: marvell,odmi-controller
23 msi-controller: true
25 marvell,odmi-frames:
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H A Dal,alpine-msix.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/interrupt-controller/al,alpine-msix.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Antoine Tenart <atenart@kernel.org>
14 const: al,alpine-msix
19 interrupt-parent: true
21 msi-controller: true
23 al,msi-base-spi:
24 description: SPI base of the MSI frame
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H A Dsocionext,synquacer-exiu.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/interrupt-controller/socionext,synquacer-exiu.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Ard Biesheuvel <ardb@kernel.org>
15 level-high type GICv3 SPIs.
19 const: socionext,synquacer-exiu
24 '#interrupt-cells':
27 interrupt-controller: true
29 socionext,spi-base:
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/linux/drivers/video/backlight/
H A Dcorgi_lcd.c1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright (c) 2004-2006 Richard Purdie
10 * Converted to SPI device based LCD/Backlight device driver
21 #include <linux/spi/spi.h>
22 #include <linux/spi/corgi_lcd.h>
43 #define POWER1_GVSS_ON 0x02 /* GVSS(-8V) Power Supply ON */
44 #define POWER1_VDD_ON 0x04 /* VDD(8V),SVSS(-4V) Power Supply ON */
47 #define POWER1_GVSS_OFF 0x00 /* GVSS(-8V) Power Supply OFF */
48 #define POWER1_VDD_OFF 0x00 /* VDD(8V),SVSS(-4V) Power Supply OFF */
123 static void lcdtg_i2c_send_start(struct corgi_lcd *lcd, uint8_t base) in lcdtg_i2c_send_start() argument
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/linux/drivers/gpio/
H A Dgpio-spear-spics.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * SPEAr platform SPI chipselect abstraction over gpiolib
21 * Provision is available on some SPEAr SoCs to control ARM PL022 spi cs
22 * through system registers. This register lies outside spi (pl022)
25 * It provides control for spi chip select lines so that any chipselect
31 * struct spear_spics - represents spi chip select control
32 * @base: base address
38 * @use_count: use count of a spi controller cs lines
43 void __iomem *base; member
61 tmp = readl_relaxed(spics->base + spics->perip_cfg); in spics_set_value()
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H A Dgpio-mc33880.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * MC33880 high-side/low-side switch GPIO driver
8 * Freescale MC33880 high-side/low-side switch
13 #include <linux/spi/spi.h>
14 #include <linux/spi/mc33880.h>
40 struct spi_device *spi; member
45 return spi_write(mc->spi, &mc->port_config, sizeof(mc->port_config)); in mc33880_write_config()
52 mc->port_config |= 1 << offset; in __mc33880_set()
54 mc->port_config &= ~(1 << offset); in __mc33880_set()
65 mutex_lock(&mc->lock); in mc33880_set()
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/linux/drivers/gpu/drm/sitronix/
H A Dst7920.c1 // SPDX-License-Identifier: GPL-2.0-only
14 #include <linux/spi/spi.h>
81 struct spi_device *spi; member
92 struct drm_shadow_plane_state base; member
98 struct drm_crtc_state base; member
105 return container_of(state, struct st7920_plane_state, base.base); in to_st7920_plane_state()
110 return container_of(state, struct st7920_crtc_state, base); in to_st7920_crtc_state()
168 static void st7920_spi_write(struct spi_device *spi, int cmd, const void *data, in st7920_spi_write() argument
175 if (err->errno) in st7920_spi_write()
193 ret = spi_write(spi, reg, size); in st7920_spi_write()
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/linux/Documentation/devicetree/bindings/spi/
H A Dspi-lantiq-ssc.txt1 Lantiq Synchronous Serial Controller (SSC) SPI master driver
4 - compatible: "lantiq,ase-spi", "lantiq,falcon-spi", "lantiq,xrx100-spi",
5 "intel,lgm-spi"
6 - #address-cells: see spi-bus.txt
7 - #size-cells: see spi-bus.txt
8 - reg: address and length of the spi master registers
9 - interrupts:
10 For compatible "intel,lgm-ssc" - the common interrupt number for
18 - clocks: spi clock phandle
19 - num-cs: see spi-bus.txt, set to 8 if unset
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/linux/Documentation/devicetree/bindings/net/
H A Dmicrochip,lan8650.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Microchip LAN8650/1 10BASE-T1S MACPHY Ethernet Controllers
10 - Parthiban Veerasooran <parthiban.veerasooran@microchip.com>
14 PHY to enable 10BASE‑T1S networks. The Ethernet Media Access Controller
16 with the IEEE 802.3 standard and a 10BASE-T1S physical layer transceiver
18 the MAC-PHY is specified in the OPEN Alliance 10BASE-T1x MACPHY Serial
22 - $ref: /schemas/net/ethernet-controller.yaml#
23 - $ref: /schemas/spi/spi-peripheral-props.yaml#
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/linux/Documentation/networking/
H A Doa-tc6-framework.rst1 .. SPDX-License-Identifier: GPL-2.0+
4 OPEN Alliance 10BASE-T1x MAC-PHY Serial Interface (TC6) Framework Support
8 ------------
11 single pair of conductors. The 10BASE-T1L (Clause 146) is a long reach
12 PHY supporting full duplex point-to-point operation over 1 km of single
13 balanced pair of conductors. The 10BASE-T1S (Clause 147) is a short reach
14 PHY supporting full / half duplex point-to-point operation over 15 m of
21 works in conjunction with the 10BASE-T1S PHY operating in multidrop mode.
23 The aforementioned PHYs are intended to cover the low-speed / low-cost
29 The MAC-PHY solution integrates an IEEE Clause 4 MAC and a 10BASE-T1x PHY
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/linux/sound/soc/spacemit/
H A Dk1_i2s.c1 // SPDX-License-Identifier: GPL-2.0
11 #define SSCR 0x00 /* SPI/I2S top control register */
12 #define SSFCR 0x04 /* SPI/I2S FIFO control register */
13 #define SSINTEN 0x08 /* SPI/I2S interrupt enable register */
14 #define SSDATR 0x10 /* SPI/I2S data register */
15 #define SSPSP 0x18 /* SPI/I2S programmable serial protocol control register */
16 #define SSRWT 0x24 /* SPI/I2S root control register */
18 /* SPI/I2S Work data size, register bits value 0~31 indicated data size 1~32 bits */
25 #define SSCR_SSE BIT(0) /* SPI/I2S Enable */
49 void __iomem *base; member
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