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/freebsd/sys/contrib/device-tree/Bindings/net/dsa/
H A Dnxp,sja1105.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schema
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/freebsd/sys/contrib/device-tree/Bindings/interrupt-controller/
H A Dmarvell,odmi-controller.txt4 Some Marvell SoCs have an On-Die Message Interrupt (ODMI) controller
5 which can be used by on-board peripheral for MSI interrupts.
9 - compatible : The value here should contain:
11 "marvell,ap806-odmi-controller", "marvell,odmi-controller".
13 - interrupt,controller : Identifies the node as an interrupt controller.
15 - msi-controller : Identifies the node as an MSI controller.
17 - marvell,odmi-frames : Number of ODMI frames available. Each frame
20 - reg : List of register definitions, one for each
23 - marvell,spi-base : List of GIC base SPI interrupts, one for each
24 ODMI frame. Those SPI interrupts are 0-based,
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H A Dal,alpine-msix.txt3 See arm,gic-v3.txt for SPI and MSI definitions.
7 - compatible: should be "al,alpine-msix"
8 - reg: physical base address and size of the registers
9 - interrupt-controller: identifies the node as an interrupt controller
10 - msi-controller: identifies the node as an PCI Message Signaled Interrupt
12 - al,msi-base-spi: SPI base of the MSI frame
13 - al,msi-num-spis: number of SPIs assigned to the MSI frame, relative to SPI0
18 compatible = "al,alpine-msix";
20 interrupt-parent = <&gic>;
21 interrupt-controller;
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H A Dsocionext,synquacer-exiu.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/interrupt-controller/socionext,synquacer-exiu.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Ard Biesheuvel <ardb@kernel.org>
15 level-high type GICv3 SPIs.
19 const: socionext,synquacer-exiu
24 '#interrupt-cells':
27 interrupt-controller: true
29 socionext,spi-base:
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H A Dsocionext,synquacer-exiu.txt5 level-high type GICv3 SPIs.
9 - compatible : Should be "socionext,synquacer-exiu".
10 - reg : Specifies base physical address and size of the
12 - interrupt-controller : Identifies the node as an interrupt controller.
13 - #interrupt-cells : Specifies the number of cells needed to encode an
15 - socionext,spi-base : The SPI number of the first SPI of the 32 adjacent
20 - Only SPIs can use the EXIU as an interrupt parent.
24 exiu: interrupt-controller@510c0000 {
25 compatible = "socionext,synquacer-exiu";
27 interrupt-controller;
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H A Darm,gic.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/interrupt-controller/arm,gic.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Marc Zyngier <marc.zyngier@arm.com>
14 interrupts (PPI), shared processor interrupts (SPI) and software
22 - $ref: /schemas/interrupt-controller.yaml#
27 - items:
28 - enum:
29 - arm,arm11mp-gic
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/freebsd/sys/contrib/device-tree/Bindings/spi/
H A Dspi-lantiq-ssc.txt1 Lantiq Synchronous Serial Controller (SSC) SPI master driver
4 - compatible: "lantiq,ase-spi", "lantiq,falcon-spi", "lantiq,xrx100-spi",
5 "intel,lgm-spi"
6 - #address-cells: see spi-bus.txt
7 - #size-cells: see spi-bus.txt
8 - reg: address and length of the spi master registers
9 - interrupts:
10 For compatible "intel,lgm-ssc" - the common interrupt number for
18 - clocks: spi clock phandle
19 - num-cs: see spi-bus.txt, set to 8 if unset
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H A Dspi-bcm63xx.txt1 Binding for Broadcom BCM6348/BCM6358 SPI controller
4 - compatible: must contain one of "brcm,bcm6348-spi", "brcm,bcm6358-spi".
5 - reg: Base address and size of the controllers memory area.
6 - interrupts: Interrupt for the SPI block.
7 - clocks: phandle of the SPI clock.
8 - clock-names: has to be "spi".
9 - #address-cells: <1>, as required by generic SPI binding.
10 - #size-cells: <0>, also as required by generic SPI binding.
13 - num-cs: some controllers have less than 8 cs signals. Defaults to 8
16 Child nodes as per the generic SPI binding.
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H A Dspi-ath79.txt1 Binding for Qualcomm Atheros AR7xxx/AR9xxx SPI controller
4 - compatible: has to be "qca,<soc-type>-spi", "qca,ar7100-spi" as fallback.
5 - reg: Base address and size of the controllers memory area
6 - clocks: phandle of the AHB clock.
7 - clock-names: has to be "ahb".
8 - #address-cells: <1>, as required by generic SPI binding.
9 - #size-cells: <0>, also as required by generic SPI binding.
11 Child nodes as per the generic SPI binding.
15 spi@1f000000 {
16 compatible = "qca,ar9132-spi", "qca,ar7100-spi";
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H A Dspi-octeon.txt1 Cavium, Inc. OCTEON SOC SPI master controller.
4 - compatible : "cavium,octeon-3010-spi"
5 - reg : The register base for the controller.
6 - interrupts : One interrupt, used by the controller.
7 - #address-cells : <1>, as required by generic SPI binding.
8 - #size-cells : <0>, also as required by generic SPI binding.
10 Child nodes as per the generic SPI binding.
14 spi@1070000001000 {
15 compatible = "cavium,octeon-3010-spi";
18 #address-cells = <1>;
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H A Dadi,axi-spi-engine.txt1 Analog Devices AXI SPI Engine controller Device Tree Bindings
4 - compatible : Must be "adi,axi-spi-engine-1.00.a""
5 - reg : Physical base address and size of the register map.
6 - interrupts : Property with a value describing the interrupt
8 - clock-names : List of input clock names - "s_axi_aclk", "spi_clk"
9 - clocks : Clock phandles and specifiers (See clock bindings for
10 details on clock-names and clocks).
11 - #address-cells : Must be <1>
12 - #size-cells : Must be <0>
15 Subnodes are use to represent the SPI slave devices connected to the SPI
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H A Dspi-bcm63xx-hsspi.txt1 Binding for Broadcom BCM6328 High Speed SPI controller
4 - compatible: must contain of "brcm,bcm6328-hsspi".
5 - reg: Base address and size of the controllers memory area.
6 - interrupts: Interrupt for the SPI block.
7 - clocks: phandles of the SPI clock and the PLL clock.
8 - clock-names: must be "hsspi", "pll".
9 - #address-cells: <1>, as required by generic SPI binding.
10 - #size-cells: <0>, also as required by generic SPI binding.
13 - num-cs: some controllers have less than 8 cs signals. Defaults to 8
16 Child nodes as per the generic SPI binding.
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H A Dspi-xilinx.txt1 Xilinx SPI controller Device Tree Bindings
2 -------------------------------------------------
5 - compatible : Should be "xlnx,xps-spi-2.00.a", "xlnx,xps-spi-2.00.b" or "xlnx,axi-quad-spi-1.00.a"
6 - reg : Physical base address and size of SPI registers map.
7 - interrupts : Property with a value describing the interrupt
11 - xlnx,num-ss-bits : Number of chip selects used.
12 - xlnx,num-transfer-bits : Number of bits per transfer. This will be 8 if not specified
16 compatible = "xlnx,xps-spi-2.00.a";
17 interrupt-parent = <&intc>;
20 xlnx,num-ss-bits = <0x1>;
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H A Dspi-mtk-nor.txt4 - compatible: For mt8173, compatible should be "mediatek,mt8173-nor",
6 For every other SoC, should contain both the SoC-specific compatible
7 string and "mediatek,mt8173-nor".
9 "mediatek,mt2701-nor", "mediatek,mt8173-nor"
10 "mediatek,mt2712-nor", "mediatek,mt8173-nor"
11 "mediatek,mt7622-nor", "mediatek,mt8173-nor"
12 "mediatek,mt7623-nor", "mediatek,mt8173-nor"
13 "mediatek,mt7629-nor", "mediatek,mt8173-nor"
14 "mediatek,mt8173-nor"
15 - reg: physical base address and length of the controller's register
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H A Dspi-armada-3700.txt1 * Marvell Armada 3700 SPI Controller
5 - compatible: should be "marvell,armada-3700-spi"
6 - reg: physical base address of the controller and length of memory mapped
8 - interrupts: The interrupt number. The interrupt specifier format depends on
10 - clocks: Must contain the clock source, usually from the North Bridge clocks.
11 - num-cs: The number of chip selects that is supported by this SPI Controller
12 - #address-cells: should be 1.
13 - #size-cells: should be 0.
17 spi0: spi@10600 {
18 compatible = "marvell,armada-3700-spi";
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H A Dqcom,spi-qup.txt1 Qualcomm Universal Peripheral (QUP) Serial Peripheral Interface (SPI)
4 and an input FIFO) for serial peripheral interface (SPI) mini-core.
6 SPI in master mode supports up to 50MHz, up to four chip selects, programmable
10 - compatible: Should contain:
11 "qcom,spi-qup-v1.1.1" for 8660, 8960 and 8064.
12 "qcom,spi-qup-v2.1.1" for 8974 and later
13 "qcom,spi-qup-v2.2.1" for 8974 v2 and later.
15 - reg: Should contain base register location and length
16 - interrupts: Interrupt number used by this controller
18 - clocks: Should contain the core clock and the AHB clock.
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H A Dspi-cadence.txt1 Cadence SPI controller Device Tree Bindings
2 -------------------------------------------
5 - compatible : Should be "cdns,spi-r1p6" or "xlnx,zynq-spi-r1p6".
6 - reg : Physical base address and size of SPI registers map.
7 - interrupts : Property with a value describing the interrupt
9 - clock-names : List of input clock names - "ref_clk", "pclk"
11 - clocks : Clock phandles (see clock bindings for details).
14 - num-cs : Number of chip selects used.
17 - is-decoded-cs : Flag to indicate whether decoder is used or not.
21 spi@e0007000 {
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H A Dspi-samsung.txt1 * Samsung SPI Controller
3 The Samsung SPI controller is used to interface with various devices such as flash
4 and display controllers using the SPI communication interface.
8 - compatible: should be one of the following.
9 - samsung,s3c2443-spi: for s3c2443, s3c2416 and s3c2450 platforms
10 - samsung,s3c6410-spi: for s3c6410 platforms
11 - samsung,s5pv210-spi: for s5pv210 and s5pc110 platforms
12 - samsung,exynos5433-spi: for exynos5433 compatible controllers
13 - samsung,exynos7-spi: for exynos7 platforms <DEPRECATED>
15 - reg: physical base address of the controller and length of memory mapped
[all …]
/freebsd/sys/contrib/device-tree/Bindings/net/
H A Dadi,adin1110.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: ADI ADIN1110 MAC-PHY
10 - Alexandru Tachici <alexandru.tachici@analog.com>
13 The ADIN1110 is a low power single port 10BASE-T1L MAC-
18 The ADIN2111 is a low power, low complexity, two-Ethernet ports
19 switch with integrated 10BASE-T1L PHYs and one serial peripheral
20 interface (SPI) port. The device is designed for industrial Ethernet
22 with the IEEE 802.3cg-2019 Ethernet standard for long reach
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/freebsd/sys/contrib/device-tree/Bindings/soc/mediatek/
H A Dpwrap.txt5 On MediaTek SoCs the PMIC is connected via SPI. The SPI master interface
8 optionally be encrypted. Also a non standard Dual IO SPI mode can be
14 The signals of these pins are routed over the SPI bus using the pwrap
20 - compatible:
21 "mediatek,mt2701-pwrap" for MT2701/7623 SoCs
22 "mediatek,mt6765-pwrap" for MT6765 SoCs
23 "mediatek,mt6779-pwrap" for MT6779 SoCs
24 "mediatek,mt6797-pwrap" for MT6797 SoCs
25 "mediatek,mt6873-pwrap" for MT6873/8192 SoCs
26 "mediatek,mt7622-pwrap" for MT7622 SoCs
[all …]
/freebsd/sys/contrib/device-tree/Bindings/dma/
H A Dstericsson,dma40.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: ST-Ericsso
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/freebsd/sys/contrib/device-tree/src/arm64/mediatek/
H A Dmt7986b-rfb.dts1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
7 /dts-v1/;
12 chassis-type = "embedded";
13 compatible = "mediatek,mt7986b-rfb", "mediatek,mt7986b";
20 stdout-path = "serial0:115200n8";
37 compatible = "mediatek,eth-mac";
39 phy-mode = "2500base-x";
41 fixed-link {
43 full-duplex;
48 mdio: mdio-bus {
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/freebsd/sys/contrib/device-tree/Bindings/clock/
H A Dlpc1850-cgu.txt5 a base clock and itself is one of the inputs to the two Clock
13 corresponds to one of the base clocks for the LPC18xx.
15 - Above text taken from NXP LPC1850 User Manual.
19 Documentation/devicetree/bindings/clock/clock-bindings.txt
22 - compatible:
23 Should be "nxp,lpc1850-cgu"
24 - reg:
25 Shall define the base and range of the address space
27 - #clock-cells:
28 Shall have value <1>. The permitted clock-specifier values
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/freebsd/sys/contrib/device-tree/src/arm64/broadcom/northstar2/
H A Dns2.dtsi35 #include <dt-bindings/interrupt-controller/arm-gic.h>
36 #include <dt-bindings/clock/bcm-ns2.h>
40 interrupt-parent = <&gic>;
41 #address-cells = <2>;
42 #size-cells = <2>;
45 #address-cells = <2>;
46 #size-cell
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/freebsd/sys/contrib/device-tree/src/arm64/marvell/
H A Darmada-ap80x.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
9 #include <dt-bindings/thermal/thermal.h>
11 /dts-v1/;
14 #address-cells = <2>;
15 #size-cell
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