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Searched full:speedbin (Results 1 – 6 of 6) sorted by relevance

/linux/drivers/cpufreq/
H A Dsun50i-cpufreq-nvmem.c31 u32 (*efuse_xlate)(u32 speedbin);
34 static u32 sun50i_h6_efuse_xlate(u32 speedbin) in sun50i_h6_efuse_xlate() argument
38 efuse_value = (speedbin >> NVMEM_SHIFT) & NVMEM_MASK; in sun50i_h6_efuse_xlate()
51 static u32 sun50i_a100_efuse_xlate(u32 speedbin) in sun50i_a100_efuse_xlate() argument
55 efuse_value = (speedbin >> SUN50I_A100_NVMEM_SHIFT) & in sun50i_a100_efuse_xlate()
79 * returned speedbin index is 4 -> 0/2 -> 3 -> 1, from worst to best.
82 static u32 sun50i_h616_efuse_xlate(u32 speedbin) in sun50i_h616_efuse_xlate() argument
87 switch (speedbin & 0xffff) { in sun50i_h616_efuse_xlate()
119 speedbin & 0xffff); in sun50i_h616_efuse_xlate()
198 u32 speedbin = 0; in sun50i_cpufreq_get_efuse() local
[all …]
/linux/Documentation/devicetree/bindings/opp/
H A Dopp-v2-kryo-cpu.yaml20 defines the voltage and frequency value based on the speedbin blown in
37 speedbin that is used to select the right frequency/voltage
58 0: MSM8996, speedbin 0
59 1: MSM8996, speedbin 1
60 2: MSM8996, speedbin 2
61 3: MSM8996, speedbin 3
64 Bitmap for MSM8996SG format (speedbin shifted of 4 left):
66 4: MSM8996SG, speedbin 0
67 5: MSM8996SG, speedbin 1
68 6: MSM8996SG, speedbin 2
[all …]
/linux/drivers/nvmem/
H A Dmtk-efuse.c54 * On some SoCs, the GPU speedbin is not read as bitmask but as in mtk_efuse_fixup_dt_cell_info()
59 strncmp(cell->name, "gpu-speedbin", min(sz, strlen("gpu-speedbin"))) == 0) in mtk_efuse_fixup_dt_cell_info()
/linux/drivers/gpu/drm/msm/adreno/
H A Da6xx_gpu.c2586 return BIT(info->speedbins[i].speedbin); in a6xx_set_supported_hw()
2592 const struct adreno_info *info, u32 *speedbin) in a6xx_set_supported_hw()
2596 /* Use speedbin fuse if present. Otherwise, fallback to softfuse */ in a6xx_set_supported_hw()
2597 ret = adreno_read_speedbin(dev, speedbin); in a6xx_set_supported_hw()
2602 *speedbin = a6xx_cx_misc_read(a6xx_gpu, REG_A8XX_CX_MISC_SW_FUSE_FREQ_LIMIT_STATUS); in a6xx_set_supported_hw()
2603 *speedbin = A8XX_CX_MISC_SW_FUSE_FREQ_LIMIT_STATUS_FINALFREQLIMIT(*speedbin); in a6xx_set_supported_hw()
2614 u32 speedbin; in a6xx_aqe_is_enabled()
2617 ret = a6xx_read_speedbin(dev, a6xx_gpu, info, &speedbin);
2619 * -ENOENT means that the platform doesn't support speedbin whic in a6xx_gpu_init()
2553 a6xx_read_speedbin(struct device * dev,struct a6xx_gpu * a6xx_gpu,const struct adreno_info * info,u32 * speedbin) a6xx_read_speedbin() argument
2575 u32 speedbin; a6xx_set_supported_hw() local
2628 u32 speedbin; a6xx_gpu_init() local
[all...]
H A Dadreno_gpu.c387 *value |= ((uint64_t) adreno_gpu->speedbin) << 32; in adreno_get_param()
1180 int adreno_read_speedbin(struct device *dev, u32 *speedbin)
1182 return nvmem_cell_read_variable_le_u32(dev, "speed_bin", speedbin); in adreno_read_speedbin()
1181 adreno_read_speedbin(struct device * dev,u32 * speedbin) adreno_read_speedbin() argument
H A Da6xx_catalog.c1089 { 172, 2 }, /* Called speedbin 1 downstream, but let's not break things! */