11802d0beSThomas Gleixner // SPDX-License-Identifier: GPL-2.0-only
24c7e4fe3SAndrew-CT Chen /*
34c7e4fe3SAndrew-CT Chen * Copyright (c) 2015 MediaTek Inc.
44c7e4fe3SAndrew-CT Chen * Author: Andrew-CT Chen <andrew-ct.chen@mediatek.com>
54c7e4fe3SAndrew-CT Chen */
64c7e4fe3SAndrew-CT Chen
74c7e4fe3SAndrew-CT Chen #include <linux/device.h>
84c7e4fe3SAndrew-CT Chen #include <linux/module.h>
9ac316725SRandy Dunlap #include <linux/mod_devicetable.h>
10ba360fd0SSrinivas Kandagatla #include <linux/io.h>
114c7e4fe3SAndrew-CT Chen #include <linux/nvmem-provider.h>
124c7e4fe3SAndrew-CT Chen #include <linux/platform_device.h>
13de6e0509SAngeloGioacchino Del Regno #include <linux/property.h>
14de6e0509SAngeloGioacchino Del Regno
15de6e0509SAngeloGioacchino Del Regno struct mtk_efuse_pdata {
16de6e0509SAngeloGioacchino Del Regno bool uses_post_processing;
17de6e0509SAngeloGioacchino Del Regno };
184c7e4fe3SAndrew-CT Chen
19a48f1fffSMasahiro Yamada struct mtk_efuse_priv {
20a48f1fffSMasahiro Yamada void __iomem *base;
21a48f1fffSMasahiro Yamada };
22a48f1fffSMasahiro Yamada
mtk_reg_read(void * context,unsigned int reg,void * _val,size_t bytes)23ba360fd0SSrinivas Kandagatla static int mtk_reg_read(void *context,
24ba360fd0SSrinivas Kandagatla unsigned int reg, void *_val, size_t bytes)
25ba360fd0SSrinivas Kandagatla {
26a48f1fffSMasahiro Yamada struct mtk_efuse_priv *priv = context;
2798e2c4efSChunfeng Yun void __iomem *addr = priv->base + reg;
2898e2c4efSChunfeng Yun u8 *val = _val;
2998e2c4efSChunfeng Yun int i;
30ba360fd0SSrinivas Kandagatla
3198e2c4efSChunfeng Yun for (i = 0; i < bytes; i++, val++)
3298e2c4efSChunfeng Yun *val = readb(addr + i);
33ba360fd0SSrinivas Kandagatla
34ba360fd0SSrinivas Kandagatla return 0;
35ba360fd0SSrinivas Kandagatla }
36ba360fd0SSrinivas Kandagatla
mtk_efuse_gpu_speedbin_pp(void * context,const char * id,int index,unsigned int offset,void * data,size_t bytes)37de6e0509SAngeloGioacchino Del Regno static int mtk_efuse_gpu_speedbin_pp(void *context, const char *id, int index,
38de6e0509SAngeloGioacchino Del Regno unsigned int offset, void *data, size_t bytes)
39de6e0509SAngeloGioacchino Del Regno {
40de6e0509SAngeloGioacchino Del Regno u8 *val = data;
41de6e0509SAngeloGioacchino Del Regno
42de6e0509SAngeloGioacchino Del Regno if (val[0] < 8)
43de6e0509SAngeloGioacchino Del Regno val[0] = BIT(val[0]);
44de6e0509SAngeloGioacchino Del Regno
45de6e0509SAngeloGioacchino Del Regno return 0;
46de6e0509SAngeloGioacchino Del Regno }
47de6e0509SAngeloGioacchino Del Regno
mtk_efuse_fixup_dt_cell_info(struct nvmem_device * nvmem,struct nvmem_cell_info * cell)481172460eSMiquel Raynal static void mtk_efuse_fixup_dt_cell_info(struct nvmem_device *nvmem,
49de6e0509SAngeloGioacchino Del Regno struct nvmem_cell_info *cell)
50de6e0509SAngeloGioacchino Del Regno {
51de6e0509SAngeloGioacchino Del Regno size_t sz = strlen(cell->name);
52de6e0509SAngeloGioacchino Del Regno
53de6e0509SAngeloGioacchino Del Regno /*
54de6e0509SAngeloGioacchino Del Regno * On some SoCs, the GPU speedbin is not read as bitmask but as
55de6e0509SAngeloGioacchino Del Regno * a number with range [0-7] (max 3 bits): post process to use
56de6e0509SAngeloGioacchino Del Regno * it in OPP tables to describe supported-hw.
57de6e0509SAngeloGioacchino Del Regno */
58de6e0509SAngeloGioacchino Del Regno if (cell->nbits <= 3 &&
59de6e0509SAngeloGioacchino Del Regno strncmp(cell->name, "gpu-speedbin", min(sz, strlen("gpu-speedbin"))) == 0)
60de6e0509SAngeloGioacchino Del Regno cell->read_post_process = mtk_efuse_gpu_speedbin_pp;
61de6e0509SAngeloGioacchino Del Regno }
62de6e0509SAngeloGioacchino Del Regno
mtk_efuse_probe(struct platform_device * pdev)634c7e4fe3SAndrew-CT Chen static int mtk_efuse_probe(struct platform_device *pdev)
644c7e4fe3SAndrew-CT Chen {
654c7e4fe3SAndrew-CT Chen struct device *dev = &pdev->dev;
664c7e4fe3SAndrew-CT Chen struct resource *res;
674c7e4fe3SAndrew-CT Chen struct nvmem_device *nvmem;
684dd5f60eSMasahiro Yamada struct nvmem_config econfig = {};
69a48f1fffSMasahiro Yamada struct mtk_efuse_priv *priv;
70de6e0509SAngeloGioacchino Del Regno const struct mtk_efuse_pdata *pdata;
71*998f0633SWilliam-tw Lin struct platform_device *socinfo;
72a48f1fffSMasahiro Yamada
73a48f1fffSMasahiro Yamada priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
74a48f1fffSMasahiro Yamada if (!priv)
75a48f1fffSMasahiro Yamada return -ENOMEM;
764c7e4fe3SAndrew-CT Chen
77f5c97da8SAngeloGioacchino Del Regno priv->base = devm_platform_get_and_ioremap_resource(pdev, 0, &res);
78a48f1fffSMasahiro Yamada if (IS_ERR(priv->base))
79a48f1fffSMasahiro Yamada return PTR_ERR(priv->base);
804c7e4fe3SAndrew-CT Chen
81de6e0509SAngeloGioacchino Del Regno pdata = device_get_match_data(dev);
822cc3b37fSRafał Miłecki econfig.add_legacy_fixed_of_cells = true;
8398e2c4efSChunfeng Yun econfig.stride = 1;
8498e2c4efSChunfeng Yun econfig.word_size = 1;
854dd5f60eSMasahiro Yamada econfig.reg_read = mtk_reg_read;
864dd5f60eSMasahiro Yamada econfig.size = resource_size(res);
87a48f1fffSMasahiro Yamada econfig.priv = priv;
884dd5f60eSMasahiro Yamada econfig.dev = dev;
89de6e0509SAngeloGioacchino Del Regno if (pdata->uses_post_processing)
901172460eSMiquel Raynal econfig.fixup_dt_cell_info = &mtk_efuse_fixup_dt_cell_info;
917e68a645SAndrey Smirnov nvmem = devm_nvmem_register(dev, &econfig);
92*998f0633SWilliam-tw Lin if (IS_ERR(nvmem))
93*998f0633SWilliam-tw Lin return PTR_ERR(nvmem);
944c7e4fe3SAndrew-CT Chen
95*998f0633SWilliam-tw Lin socinfo = platform_device_register_data(&pdev->dev, "mtk-socinfo",
96*998f0633SWilliam-tw Lin PLATFORM_DEVID_AUTO, NULL, 0);
97*998f0633SWilliam-tw Lin if (IS_ERR(socinfo))
98*998f0633SWilliam-tw Lin dev_info(dev, "MediaTek SoC Information will be unavailable\n");
99*998f0633SWilliam-tw Lin
100*998f0633SWilliam-tw Lin platform_set_drvdata(pdev, socinfo);
101*998f0633SWilliam-tw Lin return 0;
1024c7e4fe3SAndrew-CT Chen }
1034c7e4fe3SAndrew-CT Chen
104de6e0509SAngeloGioacchino Del Regno static const struct mtk_efuse_pdata mtk_mt8186_efuse_pdata = {
105de6e0509SAngeloGioacchino Del Regno .uses_post_processing = true,
106de6e0509SAngeloGioacchino Del Regno };
107de6e0509SAngeloGioacchino Del Regno
108de6e0509SAngeloGioacchino Del Regno static const struct mtk_efuse_pdata mtk_efuse_pdata = {
109de6e0509SAngeloGioacchino Del Regno .uses_post_processing = false,
110de6e0509SAngeloGioacchino Del Regno };
111de6e0509SAngeloGioacchino Del Regno
1124c7e4fe3SAndrew-CT Chen static const struct of_device_id mtk_efuse_of_match[] = {
113de6e0509SAngeloGioacchino Del Regno { .compatible = "mediatek,mt8173-efuse", .data = &mtk_efuse_pdata },
114de6e0509SAngeloGioacchino Del Regno { .compatible = "mediatek,mt8186-efuse", .data = &mtk_mt8186_efuse_pdata },
115de6e0509SAngeloGioacchino Del Regno { .compatible = "mediatek,efuse", .data = &mtk_efuse_pdata },
1164c7e4fe3SAndrew-CT Chen {/* sentinel */},
1174c7e4fe3SAndrew-CT Chen };
1184c7e4fe3SAndrew-CT Chen MODULE_DEVICE_TABLE(of, mtk_efuse_of_match);
1194c7e4fe3SAndrew-CT Chen
mtk_efuse_remove(struct platform_device * pdev)120*998f0633SWilliam-tw Lin static void mtk_efuse_remove(struct platform_device *pdev)
121*998f0633SWilliam-tw Lin {
122*998f0633SWilliam-tw Lin struct platform_device *socinfo = platform_get_drvdata(pdev);
123*998f0633SWilliam-tw Lin
124*998f0633SWilliam-tw Lin if (!IS_ERR_OR_NULL(socinfo))
125*998f0633SWilliam-tw Lin platform_device_unregister(socinfo);
126*998f0633SWilliam-tw Lin }
127*998f0633SWilliam-tw Lin
1284c7e4fe3SAndrew-CT Chen static struct platform_driver mtk_efuse_driver = {
1294c7e4fe3SAndrew-CT Chen .probe = mtk_efuse_probe,
130*998f0633SWilliam-tw Lin .remove_new = mtk_efuse_remove,
1314c7e4fe3SAndrew-CT Chen .driver = {
1324c7e4fe3SAndrew-CT Chen .name = "mediatek,efuse",
1334c7e4fe3SAndrew-CT Chen .of_match_table = mtk_efuse_of_match,
1344c7e4fe3SAndrew-CT Chen },
1354c7e4fe3SAndrew-CT Chen };
136564e7f87SAndrew-CT Chen
mtk_efuse_init(void)137564e7f87SAndrew-CT Chen static int __init mtk_efuse_init(void)
138564e7f87SAndrew-CT Chen {
139564e7f87SAndrew-CT Chen int ret;
140564e7f87SAndrew-CT Chen
141564e7f87SAndrew-CT Chen ret = platform_driver_register(&mtk_efuse_driver);
142564e7f87SAndrew-CT Chen if (ret) {
143564e7f87SAndrew-CT Chen pr_err("Failed to register efuse driver\n");
144564e7f87SAndrew-CT Chen return ret;
145564e7f87SAndrew-CT Chen }
146564e7f87SAndrew-CT Chen
147564e7f87SAndrew-CT Chen return 0;
148564e7f87SAndrew-CT Chen }
149564e7f87SAndrew-CT Chen
mtk_efuse_exit(void)150564e7f87SAndrew-CT Chen static void __exit mtk_efuse_exit(void)
151564e7f87SAndrew-CT Chen {
152564e7f87SAndrew-CT Chen return platform_driver_unregister(&mtk_efuse_driver);
153564e7f87SAndrew-CT Chen }
154564e7f87SAndrew-CT Chen
155564e7f87SAndrew-CT Chen subsys_initcall(mtk_efuse_init);
156564e7f87SAndrew-CT Chen module_exit(mtk_efuse_exit);
157564e7f87SAndrew-CT Chen
1584c7e4fe3SAndrew-CT Chen MODULE_AUTHOR("Andrew-CT Chen <andrew-ct.chen@mediatek.com>");
1594c7e4fe3SAndrew-CT Chen MODULE_DESCRIPTION("Mediatek EFUSE driver");
1604c7e4fe3SAndrew-CT Chen MODULE_LICENSE("GPL v2");
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