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/freebsd/sys/contrib/device-tree/Bindings/perf/
H A Dspe-pmu.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/perf/spe-pmu.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: ARMv8.2 Statistical Profiling Extension (SPE) Performance Monitor Units (PMU)
10 - Will Deacon <will@kernel.org>
14 performance sample data using an in-memory trace buffer.
18 const: arm,statistical-profiling-extension-v1
23 The PPI to signal SPE events. For heterogeneous systems where SPE is only
24 supported on a subset of the CPUs, please consult the arm,gic-v3 binding
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/freebsd/sys/contrib/device-tree/Bindings/arm/
H A Dspe-pmu.txt1 * ARMv8.2 Statistical Profiling Extension (SPE) Performance Monitor Units (PMU)
4 performance sample data using an in-memory trace buffer.
6 ** SPE Required properties:
8 - compatible : should be one of:
9 "arm,statistical-profiling-extension-v1"
11 - interrupts : Exactly 1 PPI must be listed. For heterogeneous systems where
12 SPE is only supported on a subset of the CPUs, please consult
13 the arm,gic-v3 binding for details on describing a PPI partition.
17 spe-pmu {
18 compatible = "arm,statistical-profiling-extension-v1";
/freebsd/sys/contrib/device-tree/src/arm64/arm/
H A Dfoundation-v8.dtsi1 // SPDX-License-Identifier: GPL-2.0
8 /dts-v1/;
10 #include <dt-bindings/interrupt-controller/arm-gic.h>
15 model = "Foundation-v8A";
16 compatible = "arm,foundation-aarch64", "arm,vexpress";
17 interrupt-parent = <&gic>;
18 #address-cells = <2>;
19 #size-cells = <2>;
22 stdout-path = "serial0:115200n8";
33 #address-cells = <2>;
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H A Dfvp-base-revc.dts1 // SPDX-License-Identifier: GPL-2.0
5 * Architecture Envelope Model (AEM) ARMv8-A
11 /dts-v1/;
13 #include <dt-bindings/interrupt-controller/arm-gic.h>
17 #include "rtsm_ve-motherboard.dtsi"
18 #include "rtsm_ve-motherboard-rs2.dtsi"
22 compatible = "arm,fvp-base-revc", "arm,vexpress";
23 interrupt-parent = <&gic>;
24 #address-cells = <2>;
25 #size-cells = <2>;
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/freebsd/sys/conf/
H A Dfiles.powerpc5 # The long compile-with and dependency lines are required because of
6 # limitations in config: backslash-newline doesn't work in strings, and
14 contrib/openzfs/module/icp/asm-ppc64/blake3/b3_ppc64le_sse2.S optional zfs compile-with "${ZFS_S}"
15 contrib/openzfs/module/icp/asm-ppc64/blake3/b3_ppc64le_sse41.S optional zfs compile-with "${ZFS_S}"
18 contrib/openzfs/module/icp/asm-ppc64/sha2/sha256-p8.S optional zfs compile-with "${ZFS_S}"
19 contrib/openzfs/module/icp/asm-ppc6
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/freebsd/sys/contrib/dev/acpica/common/
H A Ddmtbinfo2.c3 * Module Name: dmtbinfo2 - Table info for non-AML tables
11 * Some or all of this work - Copyright (c) 1999 - 2024, Intel Corp.
28 * 2.3. Intel grants Licensee a non-exclusive and non-transferable patent
104 * re-exports any such software from a foreign destination, Licensee shall
105 * ensure that the distribution and export/re-export of the software is in
108 * any of its subsidiaries will export/re-export any technical data, process,
130 * 3. Neither the names of the above-listed copyright holders nor the names
157 /* This module used for application-level code only */
165 * - Add the C table definition to the actbl1.h or actbl2.h header.
166 * - Add ACPI_xxxx_OFFSET macro(s) for the table (and subtables) to list below.
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/freebsd/sys/contrib/device-tree/src/arm64/nvidia/
H A Dtegra194.dtsi1 // SPDX-License-Identifier: GPL-2.0
2 #include <dt-bindings/clock/tegra194-clock.h>
3 #include <dt-bindings/gpio/tegra194-gpio.h>
4 #include <dt-bindings/interrupt-controller/arm-gi
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H A Dtegra234.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 #include <dt-bindings/clock/tegra234-clock.h>
4 #include <dt-bindings/gpio/tegra234-gpio.h>
5 #include <dt-bindings/interrupt-controller/arm-gic.h>
6 #include <dt-bindings/mailbox/tegra186-hsp.h>
7 #include <dt-bindings/memory/tegra234-mc.h>
8 #include <dt-bindings/pinctrl/pinctrl-tegra-io-pad.h>
9 #include <dt-bindings/power/tegra234-powergate.h>
10 #include <dt-bindings/reset/tegra234-reset.h>
11 #include <dt-bindings/thermal/tegra234-bpmp-thermal.h>
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/freebsd/sys/arm64/arm64/
H A Didentcpu.c1 /*-
88 * The default implementation of I-cache sync assumes we have an
103 if ((req->flags & SCTL_MASK32) != 0 && adaptive_machine_arch) in sysctl_hw_machine()
122 * Per-CPU affinity as provided in MPIDR_EL1
128 * Aff1 - Cluster number
129 * Aff0 - CPU number in Aff1 cluster
177 return (&cpu_desc[cpu - 1]); in get_cpu_desc()
198 * Per-implementer table of (PartNum, CPU Name) pairs.
203 { CPU_PART_FOUNDATION, "Foundation-Model" },
204 { CPU_PART_CORTEX_A34, "Cortex-A34" },
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/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64SystemOperands.td1 //===- AArch64SystemOperands.td ----------------------------*- tablegen -*-===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
12 //===----------------------------------------------------------------------===//
16 //===----------------------------------------------------------------------===//
18 //===----------------------------------------------------------------------===//
20 def HasCCPP : Predicate<"Subtarget->hasCCPP()">,
23 def HasPAN : Predicate<"Subtarget->hasPAN()">,
25 "ARM v8.1 Privileged Access-Never extension">;
27 def HasPsUAO : Predicate<"Subtarget->hasPsUAO()">,
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