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/linux/drivers/media/platform/mediatek/vcodec/decoder/
H A Dmtk_vcodec_dec_hw.h1 /* SPDX-License-Identifier: GPL-2.0 */
24 * enum mtk_vdec_hw_reg_idx - subdev hardware register base index
25 * @VDEC_HW_SYS : vdec soc register index
26 * @VDEC_HW_MISC: vdec misc register index
27 * @VDEC_HW_MAX : vdec supported max register index
36 * struct mtk_vdec_hw_dev - vdec hardware driver data
H A Dmtk_vcodec_dec_hw.c1 // SPDX-License-Identifier: GPL-2.0
22 .compatible = "mediatek,mtk-vcodec-lat",
26 .compatible = "mediatek,mtk-vcodec-core",
30 .compatible = "mediatek,mtk-vcodec-lat-soc",
39 struct platform_device *pdev = vdec_dev->plat_dev; in mtk_vdec_hw_prob_done()
48 of_id->compatible); in mtk_vdec_hw_prob_done()
54 hw_idx = (enum mtk_vdec_hw_id)(uintptr_t)of_id->data; in mtk_vdec_hw_prob_done()
55 if (!test_bit(hw_idx, vdec_dev->subdev_bitmap)) { in mtk_vdec_hw_prob_done()
56 dev_err(&pdev->dev, "vdec %d is not ready", hw_idx); in mtk_vdec_hw_prob_done()
57 return -EAGAIN; in mtk_vdec_hw_prob_done()
[all …]
/linux/drivers/clk/mediatek/
H A Dclk-mt8196-vdec.c1 // SPDX-License-Identifier: GPL-2.0-only
8 #include <dt-bindings/clock/mediatek,mt8196-clock.h>
10 #include <linux/clk-provider.h>
15 #include "clk-gate.h"
16 #include "clk-mtk.h"
90 GATE_HWV_VDE20(CLK_VDE2_VDEC_CKEN, "vde2_vdec_cken", "vdec", 0),
91 GATE_HWV_VDE20(CLK_VDE2_VDEC_ACTIVE, "vde2_vdec_active", "vdec", 4),
92 GATE_HWV_VDE20(CLK_VDE2_VDEC_CKEN_ENG, "vde2_vdec_cken_eng", "vdec", 8),
94 GATE_HWV_VDE21(CLK_VDE2_LAT_CKEN, "vde2_lat_cken", "vdec", 0),
95 GATE_HWV_VDE21(CLK_VDE2_LAT_ACTIVE, "vde2_lat_active", "vdec", 4),
[all …]
H A Dclk-mt8188-vdec.c1 // SPDX-License-Identifier: GPL-2.0-only
7 #include <dt-bindings/clock/mediatek,mt8188-clk.h>
8 #include <linux/clk-provider.h>
11 #include "clk-gate.h"
12 #include "clk-mtk.h"
76 { .compatible = "mediatek,mt8188-vdecsys-soc", .data = &vdec1_desc },
77 { .compatible = "mediatek,mt8188-vdecsys", .data = &vdec2_desc },
86 .name = "clk-mt8188-vdec",
H A DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
5 menu "Clock driver for MediaTek SoC"
134 MediaTek MT6735 SoC.
141 on the MediaTek MT6735 SoC.
148 by mfgcfg on the MediaTek MT6735 SoC.
155 by vdecsys on the MediaTek MT6735 SoC.
162 on the MediaTek MT6735 SoC.
390 required on MediaTek MT7622 SoC.
397 to PCI-E and USB.
420 required on MediaTek MT7629 SoC.
[all …]
/linux/drivers/pmdomain/mediatek/
H A Dmtk-scpsys.c1 // SPDX-License-Identifier: GPL-2.0-only
14 #include <linux/soc/mediatek/infracfg.h>
16 #include <dt-bindings/power/mt2701-power.h>
17 #include <dt-bindings/power/mt2712-power.h>
18 #include <dt-bindings/power/mt6797-power.h>
19 #include <dt-bindings/power/mt7622-power.h>
20 #include <dt-bindings/power/mt7623a-power.h>
21 #include <dt-bindings/power/mt8173-power.h>
28 #define MTK_SCPD_CAPS(_scpd, _x) ((_scpd)->data->caps & (_x))
102 "vdec",
[all …]
/linux/Documentation/admin-guide/perf/
H A Dmeson-ddr-pmu.rst1 .. SPDX-License-Identifier: GPL-2.0
4 Amlogic SoC DDR Bandwidth Performance Monitoring Unit (PMU)
7 The Amlogic Meson G12 SoC contains a bandwidth monitor inside DRAM controller.
20 meson_ddr_bw/chan_{1,2,3,4}_rw_bytes/ events are channel-specific events.
22 individual IP module in SoC.
26 + arm - from CPU
27 + vpu_read1 - from OSD + VPP read
28 + gpu - from 3D GPU
29 + pcie - from PCIe controller
30 + hdcp - from HDCP controller
[all …]
/linux/drivers/media/platform/verisilicon/
H A DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
22 will be called hantro-vpu.
41 bool "Hantro VDEC SAMA5D4 support"
62 Enable support for H6 SoC.
/linux/arch/arm64/boot/dts/mediatek/
H A Dmt8167.dtsi1 // SPDX-License-Identifier: GPL-2.0
8 #include <dt-bindings/clock/mt8167-clk.h>
9 #include <dt-bindings/memory/mt8167-larb-port.h>
10 #include <dt-bindings/power/mt8167-power.h>
12 #include "mt8167-pinfunc.h"
19 soc {
21 compatible = "mediatek,mt8167-topckgen", "syscon";
23 #clock-cells = <1>;
27 compatible = "mediatek,mt8167-infracfg", "syscon";
29 #clock-cells = <1>;
[all …]
H A Dmt8192.dtsi1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
7 /dts-v1/;
8 #include <dt-bindings/clock/mt8192-clk.h>
9 #include <dt-bindings/gce/mt8192-gce.h>
10 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 #include <dt-bindings/interrupt-controller/irq.h>
12 #include <dt-bindings/memory/mt8192-larb-port.h>
13 #include <dt-bindings/pinctrl/mt8192-pinfunc.h>
14 #include <dt-bindings/phy/phy.h>
15 #include <dt-bindings/power/mt8192-power.h>
[all …]
/linux/arch/arm64/boot/dts/amlogic/
H A Dmeson-gxbb.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 #include "meson-gx.dtsi"
7 #include "meson-gx-mali450.dtsi"
8 #include <dt-bindings/gpio/meson-gxbb-gpio.h>
9 #include <dt-bindings/reset/amlogic,meson-gxbb-reset.h>
10 #include <dt-bindings/clock/gxbb-clkc.h>
11 #include <dt-bindings/clock/gxbb-aoclkc.h>
12 #include <dt-bindings/reset/gxbb-aoclkc.h>
15 compatible = "amlogic,meson-gxbb";
17 soc {
[all …]
H A Dmeson-gxl.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
7 #include "meson-gx.dtsi"
8 #include <dt-bindings/clock/gxbb-clkc.h>
9 #include <dt-bindings/clock/gxbb-aoclkc.h>
10 #include <dt-bindings/gpio/meson-gxl-gpio.h>
11 #include <dt-bindings/reset/amlogic,meson-gxbb-reset.h>
14 compatible = "amlogic,meson-gxl";
16 soc {
18 compatible = "amlogic,meson-gxl-usb-ctrl";
21 #address-cells = <2>;
[all …]
H A Dmeson-g12-common.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 #include <dt-bindings/phy/phy.h>
7 #include <dt-bindings/gpio/gpio.h>
8 #include <dt-bindings/clock/g12a-clkc.h>
9 #include <dt-bindings/clock/g12a-aoclkc.h>
10 #include <dt-bindings/interrupt-controller/irq.h>
11 #include <dt-bindings/interrupt-controller/arm-gic.h>
12 #include <dt-bindings/interrupt-controller/amlogic,meson-g12a-gpio-intc.h>
13 #include <dt-bindings/reset/amlogic,meson-g12a-reset.h>
14 #include <dt-bindings/thermal/thermal.h>
[all …]
/linux/include/dt-bindings/memory/
H A Dmediatek,mt8188-memory-port.h1 /* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
9 #include <dt-bindings/memory/mtk-memory-port.h>
51 * This is the suggested mapping in this SoC:
53 * modules dma-address-region larbs-ports
61 * This SoC have two MM IOMMU HWs, this is the connected information:
62 * iommu-vdo: larb0/2/5/9/10/11A/11C/13/16B/17B/19/21
63 * iommu-vpp: larb1/3/4/6/7/11B/12/14/15/16A/17A/23/27
69 /* LARB 0 -- VDO-0 */
78 /* LARB 1 -- VD0-0 */
87 /* LARB 2 -- VDO-1 */
[all …]
H A Dmt8186-memory-port.h1 /* SPDX-License-Identifier: GPL-2.0-only */
11 #include <dt-bindings/memory/mtk-memory-port.h>
20 * This is the suggested mapping in this SoC:
22 * modules dma-address-region larbs-ports
32 /* LARB 0 -- MMSYS */
38 /* LARB 1 -- MMSYS */
45 /* LARB 2 -- MMSYS */
52 /* LARB 4 -- VDEC */
68 /* LARB 7 -- VENC */
83 /* LARB 8 -- WPE */
[all …]
/linux/Documentation/devicetree/bindings/soc/tegra/
H A Dnvidia,tegra20-pmc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/soc/tegra/nvidia,tegra20-pmc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Jonathan Hunter <jonathanh@nvidia.com>
16 - nvidia,tegra20-pmc
17 - nvidia,tegra30-pmc
18 - nvidia,tegra114-pmc
19 - nvidia,tegra124-pmc
[all …]
/linux/drivers/soc/amlogic/
H A Dmeson-clk-measure.c1 // SPDX-License-Identifier: GPL-2.0+
134 CLK_MSR_ID(32, "vdec"),
283 CLK_MSR_ID(32, "vdec"),
400 CLK_MSR_ID(32, "vdec"),
695 CLK_MSR_ID(93, "vdec"),
793 struct meson_msr *priv = clk_msr_id->priv; in meson_measure_id()
794 const struct msr_reg_offset *reg = priv->data.reg; in meson_measure_id()
802 regmap_write(priv->regmap, reg->freq_ctrl, 0); in meson_measure_id()
805 regmap_update_bits(priv->regmap, reg->freq_ctrl, MSR_DURATION, in meson_measure_id()
806 FIELD_PREP(MSR_DURATION, duration - 1)); in meson_measure_id()
[all …]
/linux/drivers/soc/tegra/
H A Dpmc.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * drivers/soc/tegra/pmc.c
6 * Copyright (c) 2018-2024, NVIDIA CORPORATION. All rights reserved.
12 #define pr_fmt(fmt) "tegra-pmc: " fmt
14 #include <linux/arm-smccc.h>
16 #include <linux/clk-provider.h>
18 #include <linux/clk/clk-conf.h>
37 #include <linux/pinctrl/pinconf-generic.h>
53 #include <soc/tegra/common.h>
54 #include <soc/tegra/fuse.h>
[all …]
/linux/arch/arm/boot/dts/microchip/
H A Dsama5d4.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * sama5d4.dtsi - Device Tree Include file for SAMA5D4 family SoC
9 #include <dt-bindings/clock/at91.h>
10 #include <dt-bindings/dma/at91.h>
11 #include <dt-bindings/mfd/at91-usart.h>
12 #include <dt-bindings/pinctrl/at91.h>
13 #include <dt-bindings/interrupt-controller/irq.h>
14 #include <dt-bindings/gpio/gpio.h>
17 #address-cells = <1>;
18 #size-cells = <1>;
[all …]
/linux/arch/arm64/boot/dts/apple/
H A Ds5l8960x-pmgr.dtsi1 // SPDX-License-Identifier: GPL-2.0+ OR MIT
3 * PMGR Power domains for the Apple S5L8960X "A7" SoC
9 ps_cpu0: power-controller@20000 {
10 compatible = "apple,s5l8960x-pmgr-pwrstate", "apple,pmgr-pwrstate";
12 #power-domain-cells = <0>;
13 #reset-cells = <0>;
15 apple,always-on; /* Core device */
18 ps_cpu1: power-controller@20008 {
19 compatible = "apple,s5l8960x-pmgr-pwrstate", "apple,pmgr-pwrstate";
21 #power-domain-cells = <0>;
[all …]
H A Dt7001-pmgr.dtsi1 // SPDX-License-Identifier: GPL-2.0+ OR MIT
3 * PMGR Power domains for the Apple T7001 "A8X" SoC
9 ps_cpu0: power-controller@20000 {
10 compatible = "apple,t7000-pmgr-pwrstate", "apple,pmgr-pwrstate";
12 #power-domain-cells = <0>;
13 #reset-cells = <0>;
15 apple,always-on; /* Core device */
18 ps_cpu1: power-controller@20008 {
19 compatible = "apple,t7000-pmgr-pwrstate", "apple,pmgr-pwrstate";
21 #power-domain-cells = <0>;
[all …]
H A Dt7000-pmgr.dtsi1 // SPDX-License-Identifier: GPL-2.0+ OR MIT
3 * PMGR Power domains for the Apple T7000 "A8" SoC
8 ps_cpu0: power-controller@20000 {
9 compatible = "apple,t7000-pmgr-pwrstate", "apple,pmgr-pwrstate";
11 #power-domain-cells = <0>;
12 #reset-cells = <0>;
14 apple,always-on; /* Core device */
17 ps_cpu1: power-controller@20008 {
18 compatible = "apple,t7000-pmgr-pwrstate", "apple,pmgr-pwrstate";
20 #power-domain-cells = <0>;
[all …]
H A Ds8001-pmgr.dtsi1 // SPDX-License-Identifier: GPL-2.0+ OR MIT
3 * PMGR Power domains for the Apple S8001 "A9X" SoC
9 ps_cpu0: power-controller@80000 {
10 compatible = "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate";
12 #power-domain-cells = <0>;
13 #reset-cells = <0>;
15 apple,always-on; /* Core device */
18 ps_cpu1: power-controller@80008 {
19 compatible = "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate";
21 #power-domain-cells = <0>;
[all …]
H A Ds800-0-3-pmgr.dtsi1 // SPDX-License-Identifier: GPL-2.0+ OR MIT
3 * PMGR Power domains for the Apple S8000/3 "A9" SoC
9 ps_cpu0: power-controller@80000 {
10 compatible = "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate";
12 #power-domain-cells = <0>;
13 #reset-cells = <0>;
15 apple,always-on; /* Core device */
18 ps_cpu1: power-controller@80008 {
19 compatible = "apple,s8000-pmgr-pwrstate", "apple,pmgr-pwrstate";
21 #power-domain-cells = <0>;
[all …]
/linux/arch/arm/boot/dts/nvidia/
H A Dtegra30.dtsi1 // SPDX-License-Identifier: GPL-2.0
2 #include <dt-bindings/clock/tegra30-car.h>
3 #include <dt-bindings/gpio/tegra-gpio.h>
4 #include <dt-bindings/memory/tegra30-mc.h>
5 #include <dt-bindings/pinctrl/pinctrl-tegra.h>
6 #include <dt-bindings/interrupt-controller/arm-gic.h>
7 #include <dt-bindings/soc/tegra-pmc.h>
8 #include <dt-bindings/thermal/thermal.h>
10 #include "tegra30-peripherals-opp.dtsi"
14 interrupt-parent = <&lic>;
[all …]

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