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/linux/drivers/crypto/intel/qat/qat_common/
H A Dadf_gen4_tl.h59 * @ath_slices: array of Authentication slices utilization registers
60 * @cph_slices: array of Cipher slices utilization registers
61 * @cpr_slices: array of Compression slices utilization registers
62 * @xlt_slices: array of Translator slices utilization registers
63 * @dcpr_slices: array of Decompression slices utilization registers
64 * @pke_slices: array of PKE slices utilization registers
65 * @ucs_slices: array of UCS slices utilization registers
66 * @wat_slices: array of Wireless Authentication slices utilization registers
67 * @wcp_slices: array of Wireless Cipher slices utilization registers
/linux/Documentation/devicetree/bindings/timestamp/
H A Dnvidia,tegra194-hte.yaml17 a bitmap array arranged in 32bit slices where each bit represent signal/line
45 nvidia,slices:
52 GTE instances for both Tegra194 and Tegra234 has 3 slices. The Tegra194
53 LIC instance has 11 slices and Tegra234 LIC has 17 slices.
86 nvidia,slices:
97 nvidia,slices:
108 nvidia,slices:
131 nvidia,slices: false
/linux/drivers/hte/
H A Dhte-tegra194.c121 u32 slices;
417 .slices = 3, in tegra_hte_line_xlate()
428 .slices = 3, in tegra_hte_line_xlate()
439 .slices = 4, in tegra_hte_line_xlate()
448 .slices = 11, in tegra_hte_line_xlate()
457 .slices = 17, in tegra_hte_en_dis_common()
466 .slices = 10, in tegra_hte_en_dis_common()
812 u32 i, slices, val = 0; in tegra_hte_probe()
832 ret = of_property_read_u32(dev->of_node, "nvidia,slices", &slices); in tegra_hte_resume_early()
120 u32 slices; global() member
689 u32 i, slices, val = 0; tegra_hte_probe() local
819 u32 slices = gs->chip->nlines / NV_LINES_IN_SLICE; tegra_hte_resume_early() local
840 u32 slices = gs->chip->nlines / NV_LINES_IN_SLICE; tegra_hte_suspend_late() local
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/linux/drivers/gpu/drm/xe/
H A Dxe_gt_ccs_mode.c33 * Loop over all available slices and assign each a user engine. in __xe_gt_apply_ccs_mode()
34 * For example, if there are four compute slices available, the in __xe_gt_apply_ccs_mode()
35 * assignment of compute slices to compute engines would be, in __xe_gt_apply_ccs_mode()
133 * exact multiple of engines for slices. in ccs_mode_store()
137 xe_gt_dbg(gt, "Invalid compute config, %d engines %d slices\n", in ccs_mode_store()
197 * number of compute hardware engines to which the available compute slices in xe_gt_ccs_mode_sysfs_init()
200 * The number of available compute slices is exposed to user through a per-gt in xe_gt_ccs_mode_sysfs_init()
/linux/block/partitions/
H A Dsysv68.c51 int i, slices; in sysv68_partition() local
67 slices = be16_to_cpu(b->dk_ios.ios_slccnt); in sysv68_partition()
75 slices -= 1; /* last slice is the whole disk */ in sysv68_partition()
76 seq_buf_printf(&state->pp_buf, "sysV68: %s(s%u)", state->name, slices); in sysv68_partition()
78 for (i = 0; i < slices; i++, slice++) { in sysv68_partition()
/linux/drivers/phy/lantiq/
H A Dphy-lantiq-vrx200-pcie.c202 static const struct reg_default slices[] = { in ltq_vrx200_pcie_phy_apply_workarounds() local
218 for (i = 0; i < ARRAY_SIZE(slices); i++) { in ltq_vrx200_pcie_phy_apply_workarounds()
220 regmap_update_bits(priv->phy_regmap, slices[i].reg, in ltq_vrx200_pcie_phy_apply_workarounds()
221 slices[i].def, slices[i].def); in ltq_vrx200_pcie_phy_apply_workarounds()
226 regmap_update_bits(priv->phy_regmap, slices[i].reg, in ltq_vrx200_pcie_phy_apply_workarounds()
227 slices[i].def, 0x0); in ltq_vrx200_pcie_phy_apply_workarounds()
/linux/drivers/gpu/drm/v3d/
H A Dv3d_perfmon.c30 {"QPU", "QPU-total-instr-cache-hit", "[QPU] Total instruction cache hits for all slices"},
31 {"QPU", "QPU-total-instr-cache-miss", "[QPU] Total instruction cache misses for all slices"},
32 {"QPU", "QPU-total-uniform-cache-hit", "[QPU] Total uniforms cache hits for all slices"},
33 {"QPU", "QPU-total-uniform-cache-miss", "[QPU] Total uniforms cache misses for all slices"},
118 {"QPU", "QPU-total-instr-cache-hit", "[QPU] Total instruction cache hits for all slices"},
119 {"QPU", "QPU-total-instr-cache-miss", "[QPU] Total instruction cache misses for all slices"},
120 {"QPU", "QPU-total-uniform-cache-hit", "[QPU] Total uniforms cache hits for all slices"},
121 {"QPU", "QPU-total-uniform-cache-miss", "[QPU] Total uniforms cache misses for all slices"},
148 {"L2T", "L2T-SLC-read-hits", "[L2T] SLC read hits (all slices)"},
149 {"L2T", "L2T-SLC-read-miss", "[L2T] SLC read misses (all slices)"},
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/linux/drivers/gpu/drm/i915/gt/
H A Dintel_sseu.h19 * Maximum number of slices on older platforms. Slices no longer exist
87 * For Xe_HP and beyond, the hardware no longer has traditional slices
/linux/drivers/net/dsa/
H A Dbcm_sf2_regs.h470 /* IPv4 slices, 3 of them */
478 /* IPv6 slices */
481 /* IPv6 chained slices */
484 /* Number of slices for IPv4, IPv6 and non-IP */
488 /* Spacing between different slices */
H A Dbcm_sf2_cfp.c29 u8 slices[UDFS_PER_SLICE]; member
40 /* UDF slices layout for a TCPv4/UDPv4 specification */
44 .slices = {
65 /* UDF slices layout for a TCPv6/UDPv6 specification */
69 .slices = {
93 .slices = {
149 if (memcmp(slice_layout->slices, zero_slice, in bcm_sf2_get_slice_number()
165 core_writel(priv, layout->udfs[slice_num].slices[i], in bcm_sf2_cfp_udf_set()
410 num_udf = bcm_sf2_get_num_udf_slices(layout->udfs[slice_num].slices); in bcm_sf2_cfp_ipv4_rule_set()
668 num_udf = bcm_sf2_get_num_udf_slices(layout->udfs[slice_num].slices); in bcm_sf2_cfp_ipv6_rule_set()
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/linux/Documentation/admin-guide/perf/
H A Dqcom_l3_pmu.rst6 Centriq SoCs. The L3 cache on these SOCs is composed of multiple slices, shared
9 for aggregating across slices.
/linux/drivers/gpu/drm/i915/display/
H A Dskl_watermark.c45 u8 slices[I915_MAX_PIPES];
459 * Per plane DDB entry can in a really worst case be on multiple slices in skl_ddb_dbuf_slice_mask()
511 if (dbuf_state->slices[pipe] != dbuf_state->slices[for_pipe]) in intel_crtc_dbuf_weights()
547 dbuf_slice_mask = new_dbuf_state->slices[pipe]; in skl_crtc_allocate_ddb()
564 if (old_dbuf_state->slices[pipe] == new_dbuf_state->slices[pipe] && in skl_crtc_allocate_ddb()
585 "[CRTC:%d:%s] dbuf slices 0x%x -> 0x%x, ddb (%d - %d) -> (%d - %d), active pipes 0x%x -> 0x%x\n", in skl_crtc_allocate_ddb()
587 old_dbuf_state->slices[pipe], new_dbuf_state->slices[pip in skl_crtc_allocate_ddb()
44 u8 slices[I915_MAX_PIPES]; global() member
3044 u8 slices; skl_wm_get_hw_state() local
3773 u8 slices; skl_dbuf_is_misconfigured() local
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/linux/Documentation/scheduler/
H A Dsched-eevdf.rst21 allows latency-sensitive tasks with shorter time slices to be prioritized,
31 can request specific time slices using the new sched_setattr() system call,
H A Dschedutil.rst15 individual tasks to task-group slices to CPU runqueues. As the basis for this
31 Note that blocked tasks still contribute to the aggregates (task-group slices
/linux/tools/testing/selftests/bpf/progs/
H A Ddynptr_fail.c965 /* Test that slices are invalidated on reinitializing a dynptr. */
984 /* Invalidation of dynptr slices on destruction of dynptr should not miss
1004 /* Destruction of dynptr should also any slices obtained from it */ in dynptr_invalidate_slice_failure()
1030 /* Invalidation of slices should be scoped and should not prevent dereferencing in dynptr_invalidate_slice_success()
1031 * slices of another dynptr after destroying unrelated dynptr in dynptr_invalidate_slice_success()
1597 * slices should be invalidated as well. in clone_invalidate5()
1795 /* Invalidating a dynptr should invalidate any data slices
1821 /* Invalidating a dynptr should invalidate any data slices
1847 /* Invalidating a dynptr should invalidate any data slices
1877 /* A skb clone's data slices shoul
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/linux/include/uapi/drm/
H A Dqaic_accel.h240 * struct qaic_attach_slice_hdr - Defines metadata for a set of BO slices.
241 * @count: In. Number of slices for this BO.
256 * struct qaic_attach_slice - Defines a set of BO slices.
257 * @hdr: In. Metadata of the set of slices.
/linux/tools/perf/Documentation/
H A Dperf-data.txt63 Select the first and second 10% time slices:
67 Select from 0% to 10% and 30% to 40% slices:
/linux/drivers/net/ethernet/myricom/myri10ge/
H A Dmyri10ge_mcp.h128 * data2 = slice number if multiple slices are used
140 /* data0 = slice number if multiple slices are used */
215 * If multiple slices are used, data2 contains both the size of the
239 /* data0 = number of slices n (0, 1, ..., n-1) to enable
/linux/drivers/accel/qaic/
H A Dqaic.h235 /* Head in list of slices of this BO */
236 struct list_head slices; member
237 /* Total nents, for all slices of this BO */
310 /* Node in list of slices maintained by parent BO */
/linux/drivers/gpu/drm/i915/gem/selftests/
H A Di915_gem_context.c1138 __check_rpcs(const char *name, u32 rpcs, int slices, unsigned int expected, in __check_rpcs() argument
1141 if (slices == expected) in __check_rpcs()
1144 if (slices < 0) { in __check_rpcs()
1146 name, prefix, slices, suffix); in __check_rpcs()
1147 return slices; in __check_rpcs()
1151 name, prefix, slices, expected, suffix); in __check_rpcs()
1154 rpcs, slices, in __check_rpcs()
1170 unsigned int slices = hweight32(ce->engine->sseu.slice_mask); in __sseu_finish() local
1187 ret = __check_rpcs(name, rpcs, ret, slices, "Kernel context", "!"); in __sseu_finish()
1280 * half enabled sub-slices. in __igt_ctx_sseu()
/linux/drivers/gpu/drm/amd/display/dc/
H A Ddc_hw_types.h395 * amount, it is split into multiple slices.
420 * 2D tiling modes rotate banks for successive Z slices
421 * 3D tiling modes rotate pipes and banks for Z slices
880 uint32_t num_slices_h; /* Number of DSC slices - horizontal */
881 uint32_t num_slices_v; /* Number of DSC slices - vertical */
/linux/fs/bfs/
H A DKconfig13 to "UnixWare slices support", below. More information about the BFS
/linux/drivers/net/ethernet/broadcom/bnxt/
H A Dbnxt_hwrm.c144 * hwrm_req_alloc_flags() - Sets GFP allocation flags for slices.
149 * whenever it is used to allocate backing memory for slices. Note that
185 * ensure that the lifetime of new_req is least as long as req. Any slices
204 /* free any existing slices */ in hwrm_req_replace()
320 * request object, any slices, and its associated response are no
/linux/drivers/gpu/nova-core/gsp/
H A Dcmdq.rs280 // thus the created slices are valid.
284 // - The caller holds a reference to `self` for as long as the returned slices are live,
286 // remains exclusive to the CPU for the duration of the slices.
287 // - The created slices point to non-overlapping sub-ranges of `data` in all
338 // thus the created slices are valid.
342 // - The caller holds a reference to `self` for as long as the returned slices are live, in gsp_read_ptr()
344 // remains exclusive to the CPU for the duration of the slices.
456 // Writable slices to the contents of the command. The second slice is zero unless the command
467 // Slices to the contents of the message. The second slice is zero unless the message loops in send_command()
523 /// A message is made of several parts, so `it` is an iterator over byte slices representin
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/linux/arch/arm64/kvm/
H A Dguest.c400 * Number of register slices required to cover each whole SVE register.
596 const unsigned int slices = vcpu_sve_slices(vcpu); in num_sve_regs() local
604 return slices * (SVE_NUM_PREGS + SVE_NUM_ZREGS + 1 /* FFR */) in num_sve_regs()
611 const unsigned int slices = vcpu_sve_slices(vcpu); in copy_sve_reg_indices() local
631 for (i = 0; i < slices; i++) { in copy_sve_reg_indices()

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