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/linux/drivers/crypto/intel/qat/qat_common/
H A Dadf_gen4_tl.h59 * @ath_slices: array of Authentication slices utilization registers
60 * @cph_slices: array of Cipher slices utilization registers
61 * @cpr_slices: array of Compression slices utilization registers
62 * @xlt_slices: array of Translator slices utilization registers
63 * @dcpr_slices: array of Decompression slices utilization registers
64 * @pke_slices: array of PKE slices utilization registers
65 * @ucs_slices: array of UCS slices utilization registers
66 * @wat_slices: array of Wireless Authentication slices utilization registers
67 * @wcp_slices: array of Wireless Cipher slices utilization registers
/linux/Documentation/devicetree/bindings/timestamp/
H A Dnvidia,tegra194-hte.yaml17 a bitmap array arranged in 32bit slices where each bit represent signal/line
43 nvidia,slices:
50 GTE instances for both Tegra194 and Tegra234 has 3 slices. The Tegra194
51 LIC instance has 11 slices and Tegra234 LIC has 17 slices.
84 nvidia,slices:
95 nvidia,slices:
106 nvidia,slices:
/linux/drivers/hte/
H A Dhte-tegra194.c120 u32 slices; member
326 .slices = 3,
335 .slices = 3,
342 .slices = 11,
349 .slices = 17,
689 u32 i, slices, val = 0; in tegra_hte_probe() local
709 ret = of_property_read_u32(dev->of_node, "nvidia,slices", &slices); in tegra_hte_probe()
711 slices = hte_dev->prov_data->slices; in tegra_hte_probe()
713 dev_dbg(dev, "slices:%d\n", slices); in tegra_hte_probe()
714 nlines = slices << 5; in tegra_hte_probe()
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/linux/drivers/gpu/drm/xe/
H A Dxe_gt_ccs_mode.c31 * Loop over all available slices and assign each a user engine. in __xe_gt_apply_ccs_mode()
32 * For example, if there are four compute slices available, the in __xe_gt_apply_ccs_mode()
33 * assignment of compute slices to compute engines would be, in __xe_gt_apply_ccs_mode()
132 * exact multiple of engines for slices. in ccs_mode_store()
136 xe_gt_dbg(gt, "Invalid compute config, %d engines %d slices\n", in ccs_mode_store()
181 * number of compute hardware engines to which the available compute slices
184 * The number of available compute slices is exposed to user through a per-gt
/linux/block/partitions/
H A Dsysv68.c51 int i, slices; in sysv68_partition() local
68 slices = be16_to_cpu(b->dk_ios.ios_slccnt); in sysv68_partition()
76 slices -= 1; /* last slice is the whole disk */ in sysv68_partition()
77 snprintf(tmp, sizeof(tmp), "sysV68: %s(s%u)", state->name, slices); in sysv68_partition()
80 for (i = 0; i < slices; i++, slice++) { in sysv68_partition()
/linux/drivers/gpu/drm/amd/display/dc/dsc/
H A Ddc_dsc.c793 // Get next bigger num slices available in common caps in inc_num_slices()
801 // No available slices found in inc_num_slices()
806 // Numbers of slices found - get the next bigger number in inc_num_slices()
814 if (new_num_slices == num_slices) // No bigger number of slices found in inc_num_slices()
824 // Get next bigger num slices available in common caps in dec_num_slices()
832 // No numbers of slices found in dec_num_slices()
837 // Numbers of slices found - get the next smaller number in dec_num_slices()
846 // No smaller number of slices found in dec_num_slices()
856 // Choose next bigger number of slices if the requested number of slices is not available
859 // Get next bigger num slices available in common caps in fit_num_slices_up()
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/linux/drivers/gpu/drm/i915/gt/
H A Dintel_sseu.c269 * Although gen12 architecture supported multiple slices, TGL, RKL, in gen12_sseu_info_init()
306 * Although gen11 architecture supported multiple slices, ICL and in gen11_sseu_info_init()
396 * to each of the enabled slices. in gen9_sseu_info_init()
403 * Iterate through enabled slices and subslices to in gen9_sseu_info_init()
498 * to each of the enabled slices. in bdw_sseu_info_init()
515 * Iterate through enabled slices and subslices to in bdw_sseu_info_init()
578 * There isn't a register to tell us how many slices/subslices. We in hsw_sseu_info_init()
662 u8 slices, subslices; in intel_sseu_make_rpcs() local
679 slices = hweight8(req_sseu->slice_mask); in intel_sseu_make_rpcs()
694 * If enabled subslice count is greater than four, two whole slices must in intel_sseu_make_rpcs()
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H A Dintel_sseu.h19 * Maximum number of slices on older platforms. Slices no longer exist
87 * For Xe_HP and beyond, the hardware no longer has traditional slices
/linux/drivers/phy/lantiq/
H A Dphy-lantiq-vrx200-pcie.c202 static const struct reg_default slices[] = { in ltq_vrx200_pcie_phy_apply_workarounds() local
218 for (i = 0; i < ARRAY_SIZE(slices); i++) { in ltq_vrx200_pcie_phy_apply_workarounds()
220 regmap_update_bits(priv->phy_regmap, slices[i].reg, in ltq_vrx200_pcie_phy_apply_workarounds()
221 slices[i].def, slices[i].def); in ltq_vrx200_pcie_phy_apply_workarounds()
226 regmap_update_bits(priv->phy_regmap, slices[i].reg, in ltq_vrx200_pcie_phy_apply_workarounds()
227 slices[i].def, 0x0); in ltq_vrx200_pcie_phy_apply_workarounds()
/linux/drivers/gpu/drm/amd/display/dc/inc/
H A Dresource.h318 * Update ODM slice count by acquiring or releasing pipes. If new slices need
320 * slices need to be removed, it is going to remove them from the last ODM
323 * return - true if ODM slices are updated and required pipes are acquired. All
340 * Update MPC slice count by acquiring or releasing DPP pipes. If new slices
342 * slices need to be removed, it is going to remove them from the last MPC
347 * return - true if MPC slices are updated and required pipes are acquired. All
429 * Get the number of MPC slices associated with the pipe.
436 * Get the number of ODM slices associated with the pipe.
/linux/drivers/gpu/drm/msm/
H A Dmsm_dsc_helper.h16 * msm_dsc_get_slices_per_intf() - calculate number of slices per interface
19 * Returns: Integer representing the number of slices for the given interface
/linux/drivers/gpu/drm/v3d/
H A Dv3d_perfmon.c33 {"QPU", "QPU-total-instr-cache-hit", "[QPU] Total instruction cache hits for all slices"},
34 {"QPU", "QPU-total-instr-cache-miss", "[QPU] Total instruction cache misses for all slices"},
35 {"QPU", "QPU-total-uniform-cache-hit", "[QPU] Total uniforms cache hits for all slices"},
36 {"QPU", "QPU-total-uniform-cache-miss", "[QPU] Total uniforms cache misses for all slices"},
121 {"QPU", "QPU-total-instr-cache-hit", "[QPU] Total instruction cache hits for all slices"},
122 {"QPU", "QPU-total-instr-cache-miss", "[QPU] Total instruction cache misses for all slices"},
123 {"QPU", "QPU-total-uniform-cache-hit", "[QPU] Total uniforms cache hits for all slices"},
124 {"QPU", "QPU-total-uniform-cache-miss", "[QPU] Total uniforms cache misses for all slices"},
151 {"L2T", "L2T-SLC-read-hits", "[L2T] SLC read hits (all slices)"},
152 {"L2T", "L2T-SLC-read-miss", "[L2T] SLC read misses (all slices)"},
/linux/Documentation/admin-guide/perf/
H A Dqcom_l3_pmu.rst6 Centriq SoCs. The L3 cache on these SOCs is composed of multiple slices, shared
9 for aggregating across slices.
/linux/drivers/net/dsa/
H A Dbcm_sf2_regs.h470 /* IPv4 slices, 3 of them */
478 /* IPv6 slices */
481 /* IPv6 chained slices */
484 /* Number of slices for IPv4, IPv6 and non-IP */
488 /* Spacing between different slices */
/linux/Documentation/scheduler/
H A Dsched-eevdf.rst21 allows latency-sensitive tasks with shorter time slices to be prioritized,
31 can request specific time slices using the new sched_setattr() system call,
H A Dschedutil.rst15 individual tasks to task-group slices to CPU runqueues. As the basis for this
31 Note that blocked tasks still contribute to the aggregates (task-group slices
/linux/drivers/accel/qaic/
H A Dqaic.h188 /* Head in list of slices of this BO */
189 struct list_head slices; member
190 /* Total nents, for all slices of this BO */
265 /* Node in list of slices maintained by parent BO */
/linux/drivers/gpu/drm/i915/display/
H A Dskl_watermark.c586 * Per plane DDB entry can in a really worst case be on multiple slices in skl_ddb_dbuf_slice_mask()
639 if (dbuf_state->slices[pipe] != dbuf_state->slices[for_pipe]) in intel_crtc_dbuf_weights()
675 dbuf_slice_mask = new_dbuf_state->slices[pipe]; in skl_crtc_allocate_ddb()
692 if (old_dbuf_state->slices[pipe] == new_dbuf_state->slices[pipe] && in skl_crtc_allocate_ddb()
713 … "[CRTC:%d:%s] dbuf slices 0x%x -> 0x%x, ddb (%d - %d) -> (%d - %d), active pipes 0x%x -> 0x%x\n", in skl_crtc_allocate_ddb()
715 old_dbuf_state->slices[pipe], new_dbuf_state->slices[pipe], in skl_crtc_allocate_ddb()
872 * For more DBuf slices algorithm can get even more messy
935 * For more DBuf slices algorithm can get even more messy
1336 * if one or two slices can be used for single pipe configurations in icl_compute_dbuf_slices()
2555 enabled_slices |= dbuf_state->slices[pipe]; in intel_dbuf_enabled_slices()
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/linux/tools/testing/selftests/bpf/progs/
H A Ddynptr_fail.c945 /* Test that slices are invalidated on reinitializing a dynptr. */
964 /* Invalidation of dynptr slices on destruction of dynptr should not miss
984 /* Destruction of dynptr should also any slices obtained from it */
1010 /* Invalidation of slices should be scoped and should not prevent dereferencing
1011 * slices of another dynptr after destroying unrelated dynptr
1362 * slices should be invalidated as well.
1560 /* Invalidating a dynptr should invalidate any data slices
1586 /* Invalidating a dynptr should invalidate any data slices
1612 /* Invalidating a dynptr should invalidate any data slices
1642 /* A skb clone's data slices should be invalid anytime packet data changes */
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/linux/include/uapi/drm/
H A Dqaic_accel.h240 * struct qaic_attach_slice_hdr - Defines metadata for a set of BO slices.
241 * @count: In. Number of slices for this BO.
256 * struct qaic_attach_slice - Defines a set of BO slices.
257 * @hdr: In. Metadata of the set of slices.
/linux/drivers/net/ethernet/myricom/myri10ge/
H A Dmyri10ge_mcp.h128 * data2 = slice number if multiple slices are used
140 /* data0 = slice number if multiple slices are used */
215 * If multiple slices are used, data2 contains both the size of the
239 /* data0 = number of slices n (0, 1, ..., n-1) to enable
/linux/drivers/gpu/drm/amd/display/dc/dml2/dml21/inc/
H A Ddml_top_types.h124 * A plane is divided into vertical slices of mcaches,
128 * three slices of equal width, the boundary array would contain
175 * Generally, plane0/1 slices must use a disjoint set of caches
351 …unsigned int NumberOfDSCSlices[DML2_MAX_PLANES]; /// <brief Indicate how many slices needed to sup…
/linux/drivers/gpu/drm/amd/display/dc/dsc/dcn20/
H A Ddcn20_dsc.c91 /* This returns the capabilities for a single DSC encoder engine. Number of slices and total throug…
116 …/* Maximum total throughput with all the slices combined. This is different from how DP spec speci… in dsc2_get_enc_caps()
117 * Our decoder's total throughput in Pix/s is equal to DISPCLK. This is then shared between slices. in dsc2_get_enc_caps()
124 * throughput and number of slices, but also introduces a lower limit of 2 slices in dsc2_get_enc_caps()
133 * throughput and number of slices in dsc2_get_enc_caps()
/linux/drivers/gpu/drm/i915/gt/uc/
H A Dguc_capture_fwif.h180 * (slices or dual-sub-slices) and thus depends on HW fuses discovered at startup
/linux/drivers/gpu/drm/amd/display/dc/
H A Ddc_hw_types.h386 * amount, it is split into multiple slices.
411 * 2D tiling modes rotate banks for successive Z slices
412 * 3D tiling modes rotate pipes and banks for Z slices
859 uint32_t num_slices_h; /* Number of DSC slices - horizontal */
860 uint32_t num_slices_v; /* Number of DSC slices - vertical */

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