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/linux/drivers/media/dvb-frontends/drx39xyj/
H A Ddrx_dap_fasi.h2 Copyright (c), 2004-2005,2007-2010 Trident Microsystems, Inc.
48 /*-------- compilation control switches --------------------------------------*/
53 /*-------- Required includes -------------------------------------------------*/
57 /*-------- Defines, configuring the API --------------------------------------*/
98 #error At least one of short- or long-addressing format must be allowed.
103 * Single/master multi master setting
106 * Comments about SINGLE MASTER/MULTI MASTER modes:
108 * Consider the two sides:1) the master and 2)the slave.
110 * Master:
111 * Single/multimaster operation set via DRXDAP_SINGLE_MASTER compile switch
[all …]
/linux/Documentation/devicetree/bindings/iommu/
H A Diommu.txt2 master(s).
13 Example: 32-bit DMA to 64-bit physical addresses
15 * Implement scatter-gather at page level granularity so that the device does
29 IOMMUs can be single-master or multiple-master. Single-master IOMMU devices
30 typically have a fixed association to the master device, whereas multiple-
31 master IOMMU devices can translate accesses from more than one master.
34 "dma-ranges" property that describes how the physical address space of the
35 IOMMU maps to memory. An empty "dma-ranges" property means that there is a
39 --------------------
40 - #iommu-cells: The number of cells in an IOMMU specifier needed to encode an
[all …]
/linux/Documentation/devicetree/bindings/fsi/
H A Dfsi.txt4 The FSI bus is probe-able, so the OS is able to enumerate FSI slaves, and
6 nodes to probed engines. This allows for fsi engines to expose non-probeable
8 that is an I2C master - the I2C bus can be described by the device tree under
11 FSI masters may require their own DT nodes (to describe the master HW itself);
12 that requirement is defined by the master's implementation, and is described by
13 the fsi-master-* binding specifications.
18 fsi-master {
19 /* top-level of FSI bus topology, bound to an FSI master driver and
22 fsi-slave@<link,id> {
26 fsi-slave-engine@<addr> {
[all …]
/linux/Documentation/networking/dsa/
H A Dconfiguration.rst1 .. SPDX-License-Identifier: GPL-2.0
10 .. _dsa-config-showcases:
13 -----------------------
18 *single port*
42 - when a DSA user interface is brought up, the conduit interface is
44 - when the conduit interface is brought down, all DSA user interfaces are
70 *single port*
71 * lan1: 192.0.2.1/30 (192.0.2.0 - 192.0.2.3)
72 * lan2: 192.0.2.5/30 (192.0.2.4 - 192.0.2.7)
73 * lan3: 192.0.2.9/30 (192.0.2.8 - 192.0.2.11)
[all …]
H A Db53.rst1 .. SPDX-License-Identifier: GPL-2.0
20 The switch is, if possible, configured to enable a Broadcom specific 4-bytes
30 configuration described in the :ref:`dsa-config-showcases`.
33 ----------------------------------
38 See :ref:`dsa-tagged-configuration`.
41 -------------------------------------
48 The configuration slightly differ from the :ref:`dsa-vlan-configuration`.
54 In difference to the configuration described in :ref:`dsa-vlan-configuration`
56 single port and gateway configuration, while there is no need to add an extra
59 single port
[all …]
/linux/arch/arm/boot/dts/intel/pxa/
H A Dpxa300-raumfeld-speaker-one.dts1 // SPDX-License-Identifier: GPL-2.0
3 /dts-v1/;
5 #include "pxa300-raumfeld-common.dtsi"
9 compatible = "raumfeld,raumfeld-speaker-one-pxa303", "marvell,pxa300";
13 #sound-dai-cells = <0>;
14 Vdd-supply = <&reg_3v3>;
15 Vdda-supply = <&reg_va_5v0>;
18 xo_11mhz: oscillator-11mhz {
19 compatible = "fixed-clock";
20 #clock-cells = <0>;
[all …]
H A Dpxa300-raumfeld-tuneable-clock.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 #include <dt-bindings/clock/maxim,max9485.h>
6 xo_27mhz: oscillator-27mhz {
7 compatible = "fixed-clock";
8 #clock-cells = <0>;
9 clock-frequency = <27000000>;
10 clock-accuracy = <100>;
14 compatible = "simple-audio-card";
15 simple-audio-card,name = "Raumfeld Speaker";
16 #address-cells = <1>;
[all …]
/linux/Documentation/scsi/
H A Dadvansys.rst1 .. SPDX-License-Identifier: GPL-2.0
8 RISC-based, Bus-Mastering, Fast (10 Mhz) and Ultra (20 Mhz) Narrow
9 (8-bit transfer) SCSI Host Adapters for the ISA, EISA, VL, and PCI
10 buses and RISC-based, Bus-Mastering, Ultra (20 Mhz) Wide (16-bit
15 cache and board LRAM. A CDB is a single SCSI command. The driver
21 - ABP-480 - Bus-Master CardBus (16 CDB)
24 - ABP510/5150 - Bus-Master ISA (240 CDB)
25 - ABP5140 - Bus-Master ISA PnP (16 CDB)
26 - ABP5142 - Bus-Master ISA PnP with floppy (16 CDB)
27 - ABP902/3902 - Bus-Master PCI (16 CDB)
[all …]
/linux/drivers/power/supply/
H A Dbq27xxx_battery_hdq.c1 // SPDX-License-Identifier: GPL-2.0
3 * BQ27xxx battery monitor HDQ/1-wire driver
5 * Copyright (C) 2007-2017 Texas Instruments Incorporated - https://www.ti.com/
26 MODULE_PARM_DESC(F_ID, "1-wire slave FID for BQ27xxx device");
32 mutex_lock(&sl->master->bus_mutex); in w1_bq27000_read()
33 w1_write_8(sl->master, HDQ_CMD_READ | reg); in w1_bq27000_read()
34 val = w1_read_8(sl->master); in w1_bq27000_read()
35 mutex_unlock(&sl->master->bus_mutex); in w1_bq27000_read()
41 bool single) in bq27xxx_battery_hdq_read() argument
43 struct w1_slave *sl = dev_to_w1_slave(di->dev); in bq27xxx_battery_hdq_read()
[all …]
/linux/Documentation/devicetree/bindings/soc/qcom/
H A Dqcom,rpm-master-stats.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/soc/qcom/qcom,rpm-master-stats.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm Technologies, Inc. (QTI) RPM Master Stats
10 - Konrad Dybcio <konradybcio@kernel.org>
15 spanning a single subsystem (e.g. APSS, ADSP, CDSP). All of the RPM decisions
16 (particularly around entering hardware-driven low power modes: XO shutdown
17 and total system-wide power collapse) are first made at Master-level, and
20 The Master Stats provide a few useful bits that can be used to assess whether
[all …]
/linux/drivers/mtd/parsers/
H A Dredboot.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Parse RedBoot-style Flash Image System (FIS) tables and
7 * Copyright © 2001-2010 David Woodhouse <dwmw2@infradead.org>
26 unsigned char _pad[256 - (16 + 7 * sizeof(u32))];
45 static void parse_redboot_of(struct mtd_info *master) in parse_redboot_of() argument
52 np = mtd_get_of_node(master); in parse_redboot_of()
60 ret = of_property_read_u32(npart, "fis-index-block", &dirblock); in parse_redboot_of()
72 static int parse_redboot_partitions(struct mtd_info *master, in parse_redboot_partitions() argument
92 parse_redboot_of(master); in parse_redboot_partitions()
95 offset = master->size + directory * master->erasesize; in parse_redboot_partitions()
[all …]
/linux/arch/arm/boot/dts/ti/omap/
H A Dmotorola-mapphone-common.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
2 /dts-v1/;
4 #include <dt-bindings/input/input.h>
6 #include "motorola-cpcap-mapphone.dtsi"
10 * We seem to have only 1021 MB accessible, 1021 - 1022 is locked,
11 * then 1023 - 1024 seems to contain mbm.
19 gpio-poweroff {
20 compatible = "gpio-poweroff";
21 pinctrl-0 = <&poweroff_gpio>;
22 pinctrl-names = "default";
[all …]
H A Dam3517-evm-ui.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2018 Logic PD, Inc - https://www.logicpd.com/
6 #include <dt-bindings/input/input.h>
10 compatible = "simple-audio-card";
11 simple-audio-card,name = "tlv320aic23-hifi";
13 simple-audio-card,widgets =
18 simple-audio-card,routing =
25 simple-audio-card,format = "i2s";
26 simple-audio-card,bitclock-master = <&sound_master>;
27 simple-audio-card,frame-master = <&sound_master>;
[all …]
H A Dam335x-wega.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
8 model = "Phytec AM335x phyBOARD-WEGA";
9 compatible = "phytec,am335x-wega", "phytec,am335x-phycore-som", "ti,am33xx";
12 compatible = "simple-audio-card";
13 simple-audio-card,name = "snd-wega";
14 simple-audio-card,format = "i2s";
15 simple-audio-card,bitclock-master = <&sound_iface_main>;
16 simple-audio-card,frame-master = <&sound_iface_main>;
17 simple-audio-card,mclk-fs = <512>;
18 simple-audio-card,widgets =
[all …]
H A Dam335x-boneblack-hdmi.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2012 Texas Instruments Incorporated - https://www.ti.com/
6 #include <dt-bindings/display/tda998x.h>
7 #include <dt-bindings/interrupt-controller/irq.h>
10 nxp_hdmi_bonelt_pins: nxp-hdmi-bonelt-pins {
11 pinctrl-single,pins = <
36 nxp_hdmi_bonelt_off_pins: nxp-hdmi-bonelt-off-pins {
37 pinctrl-single,pins = <
42 mcasp0_pins: mcasp0-pins {
43 pinctrl-single,pins = <
[all …]
/linux/arch/parisc/include/asm/
H A Ddma.h1 /* SPDX-License-Identifier: GPL-2.0 */
20 ** DMA_CHUNK_SIZE is used by the SCSI mid-layer to break up
34 ** We don't have DMA channels... well V-class does but the
36 ** Note: this is not relevant right now for PA-RISC, but we cannot
38 ** won't compile :-(
41 #define DMA_MODE_READ 0x44 /* I/O to memory, no autoinit, increment, single mode */
42 #define DMA_MODE_WRITE 0x48 /* memory to I/O, no autoinit, increment, single mode */
43 #define DMA_MODE_CASCADE 0xC0 /* pass thru DREQ->HRQ, DACK<-HLDA only */
49 #define IO_DMA2_BASE 0xC0 /* 16 bit master DMA, ch 4(=slave input)..7 */
55 #define DMA1_MASK_REG 0x0A /* single-channel mask (w) */
[all …]
/linux/drivers/net/wireless/ti/wl12xx/
H A Dconf.h1 /* SPDX-License-Identifier: GPL-2.0-only */
39 * in WLAN / BT master basic rate
41 * Range: 0 - 255 (ms)
50 * Range: 0 - 255 (ms)
57 * in WLAN / BT master EDR
59 * Range: 0 - 255 (ms)
68 * Range: 0 - 255 (ms)
75 * in WLAN PSM / BT master/slave BR
77 * Range: 0 - 255 (ms)
84 * in WLAN PSM / BT master/slave EDR
[all …]
/linux/drivers/gpu/drm/
H A Ddrm_lease.c1 // SPDX-License-Identifier: GPL-2.0-or-later
21 * DRM leases provide information about whether a DRM master may control a DRM
25 * The original DRM master of a device 'owns' the available drm resources. It
27 * to the new DRM master. This gives the new DRM master control over the
28 * leased resources until the owner revokes the lease, or the new DRM master
31 * - An 'owner' is a &struct drm_master that is not leasing objects from
35 * - A 'lessor' is a &struct drm_master which is leasing objects to one or more
37 * create sub-leases, hence the lessor is the same as the owner.
39 * - A 'lessee' is a &struct drm_master which is leasing objects from some
40 * other &struct drm_master. Each lessee only leases resources from a single
[all …]
/linux/arch/arm/boot/dts/ti/keystone/
H A Dkeystone-k2g-evm.dts1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (C) 2016-2017 Texas Instruments Incorporated - https://www.ti.com/
7 /dts-v1/;
9 #include "keystone-k2g.dtsi"
12 compatible = "ti,k2g-evm", "ti,k2g", "ti,keystone";
20 reserved-memory {
21 #address-cells = <2>;
22 #size-cells = <2>;
25 dsp_common_memory: dsp-common-memory@81f800000 {
26 compatible = "shared-dma-pool";
[all …]
/linux/drivers/net/wan/
H A Dhd64570.h1 /* SPDX-License-Identifier: GPL-2.0 */
5 /* SCA HD64570 register definitions - all addresses for mode 0 (8086 MPU)
24 #define DMER 0x09 /* DMA Master Enable */
42 /* MSCI channel (port) 0 registers - offset 0x20
43 MSCI channel (port) 1 registers - offset 0x40 */
77 /* Timer channel 0 (port 0 RX) registers - offset 0x60
78 Timer channel 1 (port 0 TX) registers - offset 0x68
79 Timer channel 2 (port 1 RX) registers - offset 0x70
80 Timer channel 3 (port 1 TX) registers - offset 0x78
88 #define TCNTL 0x00 /* Up-counter L */
[all …]
/linux/Documentation/driver-api/nvdimm/
H A Dsecurity.rst6 ---------------
16 ------------------
28 update <old_keyid> <new_keyid> - enable or update passphrase.
29 disable <keyid> - disable enabled security and remove key.
30 freeze - freeze changing of security states.
31 erase <keyid> - delete existing user encryption key.
32 overwrite <keyid> - wipe the entire nvdimm.
33 master_update <keyid> <new_keyid> - enable or update master passphrase.
34 master_erase <keyid> - delete existing user encryption key.
37 -----------------
[all …]
/linux/Documentation/i2c/
H A Dsmbus-protocol.rst24 single data byte, the functions using SMBus protocol operation names execute
60 This sends a single bit to the device, at the place of the Rd/Wr bit::
72 This reads a single byte from a device, without specifying a device
87 This operation is the reverse of Receive Byte: it sends a single byte
102 This reads a single byte from a device, from a designated register.
133 This writes a single byte to a device, to a designated register. The
207 SMBus Block Write - Block Read Process Call
210 SMBus Block Write - Block Read Process Call was introduced in
225 This command is sent from a SMBus device acting as a master to the
241 client->irq assigned to a Host Notify IRQ if no one else specified another.
[all …]
/linux/Documentation/w1/masters/
H A Domap-hdq.rst2 Kernel driver for omap HDQ/1-wire module
7 HDQ/1-wire controller on the TI OMAP 2430/3430 platforms.
15 The HDQ/1-Wire module of TI OMAP2430/3430 platforms implement the hardware
16 protocol of the master functions of the Benchmark HDQ and the Dallas
17 Semiconductor 1-Wire protocols. These protocols use a single wire for
18 communication between the master (HDQ/1-Wire controller) and the slave
19 (HDQ/1-Wire external compliant device).
21 A typical application of the HDQ/1-Wire module is the communication with battery
24 The controller supports operation in both HDQ and 1-wire mode. The essential
25 difference between the HDQ and 1-wire mode is how the slave device responds to
[all …]
/linux/arch/x86/include/asm/
H A Ddma.h1 /* SPDX-License-Identifier: GPL-2.0 */
26 * controller 1: channels 0-3, byte operations, ports 00-1F
27 * controller 2: channels 4-7, word operations, ports C0-DF
29 * - ALL registers are 8 bits only, regardless of transfer size
30 * - channel 4 is not used - cascades 1 into 2.
31 * - channels 0-3 are byte - addresses/counts are for physical bytes
32 * - channels 5-7 are word - addresses/counts are for physical words
33 * - transfers must not cross physical 64K (0-3) or 128K (5-7) boundaries
34 * - transfer count loaded to registers is 1 less than actual count
35 * - controller 2 offsets are all even (2x offsets for controller 1)
[all …]
/linux/arch/mips/include/asm/
H A Ddma.h1 /* SPDX-License-Identifier: GPL-2.0 */
32 * controller 1: channels 0-3, byte operations, ports 00-1F
33 * controller 2: channels 4-7, word operations, ports C0-DF
35 * - ALL registers are 8 bits only, regardless of transfer size
36 * - channel 4 is not used - cascades 1 into 2.
37 * - channels 0-3 are byte - addresses/counts are for physical bytes
38 * - channels 5-7 are word - addresses/counts are for physical words
39 * - transfers must not cross physical 64K (0-3) or 128K (5-7) boundaries
40 * - transfer count loaded to registers is 1 less than actual count
41 * - controller 2 offsets are all even (2x offsets for controller 1)
[all …]

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