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Searched +full:sifive +full:- +full:fu540 +full:- +full:prci (Results 1 – 8 of 8) sorted by relevance

/linux/arch/riscv/boot/dts/sifive/
H A Dfu540-c000.dtsi1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
2 /* Copyright (c) 2018-2019 SiFive, Inc */
4 /dts-v1/;
6 #include <dt-bindings/clock/sifive-fu540-prci.h>
9 #address-cells = <2>;
10 #size-cells = <2>;
11 compatible = "sifive,fu540-c000", "sifive,fu540";
23 #address-cells = <1>;
24 #size-cells = <0>;
26 compatible = "sifive,e51", "sifive,rocket0", "riscv";
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H A Dfu740-c000.dtsi1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
2 /* Copyright (c) 2020 SiFive, Inc */
4 /dts-v1/;
6 #include <dt-bindings/clock/sifive-fu740-prci.h>
9 #address-cells = <2>;
10 #size-cells = <2>;
11 compatible = "sifive,fu740-c000", "sifive,fu740";
23 #address-cells = <1>;
24 #size-cells = <0>;
26 compatible = "sifive,bullet0", "riscv";
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/linux/Documentation/devicetree/bindings/clock/sifive/
H A Dfu540-prci.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2 # Copyright (C) 2020 SiFive, Inc.
4 ---
5 $id: http://devicetree.org/schemas/clock/sifive/fu540-prci.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: SiFive FU540 Power Reset Clock Interrupt Controller (PRCI)
11 - Paul Walmsley <paul.walmsley@sifive.com>
14 On the FU540 family of SoCs, most system-wide clock and reset integration
15 is via the PRCI IP block.
17 macros defined in include/dt-bindings/clock/sifive-fu540-prci.h.
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/linux/drivers/clk/sifive/
H A Dfu540-prci.h1 /* SPDX-License-Identifier: GPL-2.0 */
3 * Copyright (C) 2018-2021 SiFive, Inc.
4 * Copyright (C) 2018-2019 Wesley Terpstra
5 * Copyright (C) 2018-2019 Paul Walmsley
6 * Copyright (C) 2020-2021 Zong Li
8 * The FU540 PRCI implements clock and reset control for the SiFive
9 * FU540-C000 chip. This driver assumes that it has sole control
10 * over all PRCI resources.
12 * This driver is based on the PRCI driver written by Wesley Terpstra:
13 * https://github.com/riscv/riscv-linux/commit/999529edf517ed75b56659d456d221b2ee56bb60
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H A DKconfig1 # SPDX-License-Identifier: GPL-2.0
4 bool "SiFive SoC driver support"
8 SoC drivers for SiFive Linux-capable SoCs.
13 tristate "PRCI driver for SiFive SoCs"
19 Supports the Power Reset Clock interface (PRCI) IP block found in
20 FU540/FU740 SoCs. If this kernel is meant to run on a SiFive FU540/
H A Dsifive-prci.c1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 2020 SiFive, Inc.
11 #include "sifive-prci.h"
12 #include "fu540-prci.h"
13 #include "fu740-prci.h"
20 * __prci_readl() - read from a PRCI register
21 * @pd: PRCI context
22 * @offs: register offset to read from (in bytes, from PRCI base address)
25 * address of the PRCI register target described by @pd, and return
34 return readl_relaxed(pd->va + offs); in __prci_readl()
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/linux/Documentation/devicetree/bindings/serial/
H A Dsifive-serial.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/serial/sifive-serial.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: SiFive asynchronous serial interface (UART)
10 - Pragnesh Patel <pragnesh.patel@sifive.com>
11 - Paul Walmsley <paul.walmsley@sifive.com>
12 - Palmer Dabbelt <palmer@sifive.com>
15 - $ref: serial.yaml#
20 - enum:
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/linux/Documentation/devicetree/bindings/gpio/
H A Dsifive,gpio.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/gpio/sifive,gpio.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: SiFive GPIO controller
10 - Paul Walmsley <paul.walmsley@sifive.com>
15 - enum:
16 - sifive,fu540-c000-gpio
17 - sifive,fu740-c000-gpio
18 - canaan,k210-gpiohs
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