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/linux/tools/perf/pmu-events/arch/arm64/ampere/ampereonex/
H A D	mmu.json	45 "PublicDescrition": "Data-side S1 page walk cache lookup", 48 "BriefDescription": "Data-side S1 page walk cache lookup" 51 "PublicDescrition": "Data-side S1 page walk cache refill", 54 "BriefDescription": "Data-side S1 page walk cache refill" 57 "PublicDescrition": "Data-side S2 page walk cache lookup", 60 "BriefDescription": "Data-side S2 page walk cache lookup" 63 "PublicDescrition": "Data-side S2 page walk cache refill", 66 "BriefDescription": "Data-side S2 page walk cache refill" 69 "PublicDescription": "Data-side S1 table walk fault", 72 "BriefDescription": "Data-side S1 table walk fault" [all …]
/linux/tools/perf/pmu-events/arch/powerpc/power8/
H A D	translation.json	29 …r chip's L2 or L3 on a different Node or Group (Distant), as this chip due to a data side request", 35 …r chip's L2 or L3 on a different Node or Group (Distant), as this chip due to a data side request", 41 …ion": "A Page Table Entry was loaded into the TLB from local core's L2 due to a data side request", 47 …was loaded into the TLB from a location other than the local core's L2 due to a data side request", 53 …TLB from local core's L2 hit without dispatch conflicts on Mepf state. due to a data side request", 59 …le Entry was loaded into the TLB from local core's L2 without conflict due to a data side request", 65 …ion": "A Page Table Entry was loaded into the TLB from local core's L3 due to a data side request", 71 …ry was loaded into the TLB from local core's L3 with dispatch conflict due to a data side request", 77 …TLB from local core's L3 without dispatch conflicts hit on Mepf state. due to a data side request", 83 …le Entry was loaded into the TLB from local core's L3 without conflict due to a data side request", [all …]
H A D	marked.json	365 …s L2 or L3 on a different Node or Group (Distant), as this chip due to a marked data side request", 371 …s L2 or L3 on a different Node or Group (Distant), as this chip due to a marked data side request", 377 …B from another chip's L4 on a different Node or Group (Distant) due to a marked data side request", 383 … from another chip's memory on the same Node or Group (Distant) due to a marked data side request", 389 …A Page Table Entry was loaded into the TLB from local core's L2 due to a marked data side request", 395 …ded into the TLB from a location other than the local core's L2 due to a marked data side request", 401 …m local core's L2 hit without dispatch conflicts on Mepf state. due to a marked data side request", 407 …y was loaded into the TLB from local core's L2 without conflict due to a marked data side request", 413 …A Page Table Entry was loaded into the TLB from local core's L3 due to a marked data side request", 419 …ded into the TLB from a location other than the local core's L3 due to a marked data side request", [all …]
H A D	frontend.json	293 …s L2 or L3 on a different Node or Group (Distant), as this chip due to a instruction side request", 299 …s L2 or L3 on a different Node or Group (Distant), as this chip due to a instruction side request", 305 …B from another chip's L4 on a different Node or Group (Distant) due to a instruction side request", 311 … from another chip's memory on the same Node or Group (Distant) due to a instruction side request", 317 …A Page Table Entry was loaded into the TLB from local core's L2 due to a instruction side request", 323 …ded into the TLB from a location other than the local core's L2 due to a instruction side request", 329 …m local core's L2 hit without dispatch conflicts on Mepf state. due to a instruction side request", 335 …y was loaded into the TLB from local core's L2 without conflict due to a instruction side request", 341 …A Page Table Entry was loaded into the TLB from local core's L3 due to a instruction side request", 347 …ded into the TLB from a location other than the local core's L3 due to a instruction side request", [all …]
/linux/drivers/char/hw_random/
H A D	Kconfig	28 This driver provides kernel-side support for a generic Random 43 This driver provides kernel-side support for the Random Number 57 This driver provides kernel-side support for the Random Number 70 This driver provides kernel-side support for the True Random Number 83 This driver provides kernel-side support for the Random Number 95 This driver provides kernel-side support for the Random Number 107 This driver provides kernel-side support for the Random Number 120 This driver provides kernel-side support for the Random Number 133 This driver provides kernel-side support for the RNG200 147 This driver provides kernel-side support for the Random Number [all …]
/linux/Documentation/usb/
H A D	gadget_serial.rst	57 side driver. It runs on a Linux system that has USB device side 66 \| Host-Side CDC ACM USB Host \| 78 \| Device-Side \| Gadget \| Controller \| \| 84 On the device-side Linux system, the gadget serial driver looks 87 On the host-side system, the gadget serial device looks like a 92 The host side driver can potentially be any ACM compliant driver 98 With the gadget serial driver and the host side ACM or generic 100 the host and the gadget side systems as if they were connected by a 111 side kernel for "Support for USB Gadgets", for a "USB Peripheral 128 side Linux system. You can add this to the start up scripts, if [all …]
/linux/Documentation/devicetree/bindings/memory-controllers/
H A D	rockchip,rk3399-dmc.yaml	132 the ODT on the DRAM side and controller side are both disabled. 138 When the DRAM type is DDR3, this parameter defines the DRAM side drive 146 When the DRAM type is DDR3, this parameter defines the DRAM side ODT 154 When the DRAM type is DDR3, this parameter defines the phy side CA line 162 When the DRAM type is DDR3, this parameter defines the PHY side DQ line 170 When the DRAM type is DDR3, this parameter defines the PHY side ODT 180 ODT on the DRAM side and controller side are both disabled. 186 When the DRAM type is LPDDR3, this parameter defines the DRAM side drive 194 When the DRAM type is LPDDR3, this parameter defines the DRAM side ODT 202 When the DRAM type is LPDDR3, this parameter defines the PHY side CA line [all …]
/linux/tools/perf/pmu-events/arch/x86/silvermont/
H A D	virtual-memory.json	13 "BriefDescription": "Total cycles for all the page walks. (I-side and D-side)", 22 "BriefDescription": "Duration of D-side page-walks in core cycles", 26 …"PublicDescription": "This event counts every cycle when a D-side (walks due to a load) page walk … 31 "BriefDescription": "D-side page-walks", 41 "BriefDescription": "Duration of I-side page-walks in core cycles", 45 …"PublicDescription": "This event counts every cycle when a I-side (walks due to an instruction fet… 50 "BriefDescription": "I-side page-walks", 60 "BriefDescription": "Total page walks that are completed (I-side and D-side)",
/linux/Documentation/RCU/
H A D	checklist.rst	18 tool for the job. Yes, RCU does reduce read-side overhead by 19 increasing write-side overhead, which is exactly why normal uses 28 read-side primitives is critically important. 59 2. Do the RCU read-side critical sections make proper use of 63 under your read-side code, which can greatly increase the 68 rcu_read_lock_sched(), or by the appropriate update-side lock. 72 spinlock also enters an RCU read-side critical section. 78 Letting RCU-protected pointers "leak" out of an RCU read-side 82 before letting them out of the RCU read-side critical section. 159 perfectly legal (if redundant) for update-side code to [all …]
H A D	lockdep.rst	8 aware of when each task enters and leaves any flavor of RCU read-side 33 Check for RCU read-side critical section. 35 Check for RCU-bh read-side critical section. 37 Check for RCU-sched read-side critical section. 39 Check for SRCU read-side critical section. 83 1. An RCU read-side critical section (implicit), or 88 RCU read-side critical sections, in case (2) the ->file_lock prevents 99 complain even if this was used in an RCU read-side critical section unless 107 traversal primitives check for being called from within an RCU read-side 111 false and they are called from outside any RCU read-side critical section. [all …]
H A D	whatisRCU.rst	103 b. Wait for all previous readers to complete their RCU read-side 166 reclaimer that the reader is entering an RCU read-side critical 167 section. It is illegal to block while in an RCU read-side 169 can preempt RCU read-side critical sections. Any RCU-protected 170 data structure accessed during an RCU read-side critical section 176 or interrupts also enters an RCU read-side critical section. 177 Acquiring a spinlock also enters an RCU read-side critical 180 Sleeplocks do not enter RCU read-side critical sections. 187 reclaimer that the reader is exiting an RCU read-side critical 189 or interrupts also exits an RCU read-side critical section. [all …]
/linux/sound/pci/hda/
H A D	Kconfig	98 tristate "KUnit test for Cirrus side-codec library" if !KUNIT_ALL_TESTS 104 This builds KUnit tests for the cirrus side-codec library. 123 tristate "Build CS35L41 HD-audio side codec support for I2C Bus" 133 Say Y or M here to include CS35L41 I2C HD-audio side codec support 136 comment "Set to Y if you want auto-loading the side codec driver" 150 Say Y or M here to include CS35L41 SPI HD-audio side codec support 153 comment "Set to Y if you want auto-loading the side codec driver" 160 tristate "Build CS35L56 HD-audio side codec support for I2C Bus" 177 tristate "Build CS35L56 HD-audio side codec support for SPI Bus" 194 tristate "Build TAS2781 HD-audio side codec support for I2C Bus" [all …]
/linux/tools/perf/pmu-events/arch/x86/knightslanding/
H A D	virtual-memory.json	22 …"BriefDescription": "Counts the total number of core cycles for all the D-side page walks. The cyc… 30 …"BriefDescription": "Counts the total D-side page walks that are completed or started. The page wa… 39 …"BriefDescription": "Counts the total number of core cycles for all the I-side page walks. The cyc… 43 …"PublicDescription": "This event counts every cycle when an I-side (walks due to an instruction fe… 48 "BriefDescription": "Counts the total I-side page walks that are completed.", 57 "BriefDescription": "Counts the total page walks that are completed (I-side and D-side)",
/linux/Documentation/RCU/Design/Requirements/
H A D	Requirements.rst	20 updaters do not block readers, which means that RCU's read-side 74 of all pre-existing RCU read-side critical sections. An RCU read-side 77 RCU treats a nested set as one big RCU read-side critical section. 131 \| Second, even when using synchronize_rcu(), the other update-side \| 173 The RCU read-side critical section in do_something_dlm() works with 190 In order to avoid fatal problems such as deadlocks, an RCU read-side 192 Similarly, an RCU read-side critical section must not contain anything 198 be good to be able to use RCU to coordinate read-side access to linked 370 outermost RCU read-side critical section containing that 387 #. Wait for all pre-existing RCU read-side critical sections to complete [all …]
/linux/tools/perf/pmu-events/arch/powerpc/power9/
H A D	translation.json	25 …m another chip's memory on the same Node or Group (Distant) due to a data side request. When using… 35 …chip's L2 or L3 on the same Node or Group (Remote), as this chip due to a instruction side request" 60 … or L3 on a different Node or Group (Distant), as this chip due to a data side request. When using… 75 …ared or modified data from another core's L2/L3 on the same chip due to a instruction side request" 100 …e TLB from another chip's L4 on the same Node or Group ( Remote) due to a instruction side request" 145 …from a memory location including L4 from local remote or distant due to a instruction side request" 150 …rom another core's L2/L3 on a different chip (remote or distant) due to a instruction side request" 165 … or L3 on a different Node or Group (Distant), as this chip due to a data side request. When using… 185 …om another chip's L4 on a different Node or Group (Distant) due to a data side request. When using… 210 …chip's L2 or L3 on the same Node or Group (Remote), as this chip due to a instruction side request" [all …]
H A D	pipeline.json	35 …her chip's L4 on a different Node or Group (Distant) due to a marked data side request. When using… 40 …s loaded into the TLB from local core's L2 without conflict due to a data side request. When using… 80 …ied (M) data from another core's L2 on the same chip due to a marked data side request. When using… 95 …h Modified (M) data from another core's L2 on the same chip due to a data side request. When using… 115 …e's L3 without dispatch conflicts hit on Mepf state. due to a marked data side request. When using… 160 …core's L2/L3 on a different chip (remote or distant) due to a marked data side request. When using… 175 …ed into the TLB from local core's L3 with dispatch conflict due to a data side request. When using… 180 …d into the TLB from local core's L2 without conflict due to a marked data side request. When using… 225 …d into the TLB from local core's L3 without conflict due to a marked data side request. When using… 250 …s L2 or L3 on the same Node or Group (Remote), as this chip due to a data side request. When using… [all …]
H A D	pmc.json	20 …on a different Node or Group (Distant), as this chip due to a marked data side request. When using… 30 …into the TLB from a location other than the local core's L3 due to a data side request. When using… 40 …e TLB from a location other than the local core's L2 due to a marked data side request.. When usin… 90 …a memory location including L4 from local remote or distant due to a data side request. When using… 95 … the TLB from local core's L3 with dispatch conflict due to a marked data side request. When using… 100 …e Entry was loaded into the TLB from local core's L3 due to a marked data side request. When using… 110 …ntry was loaded into the TLB from the local chip's L4 cache due to a data side request. When using…
H A D	marked.json	20 …ith Shared (S) data from another core's L3 on the same chip due to a data side request. When using… 60 …s loaded into the TLB from the local chip's L4 cache due to a marked data side request.. When usin… 70 …(S) data from another core's ECO L3 on the same chip due to a marked data side request. When using… 95 …(M) data from another core's ECO L3 on the same chip due to a marked data side request. When using… 100 …Shared (S) data from another core's ECO L3 on the same chip due to a data side request. When using… 140 …aded into the TLB from a location other than the local core's L2 due to a instruction side request" 170 …om local core's L2 hit without dispatch conflicts on Mepf state. due to a instruction side request" 210 …was loaded into the TLB from the local chip's Memory due to a marked data side request. When using… 220 …e TLB from a location other than the local core's L3 due to a marked data side request. When using… 290 … Entry was loaded into the TLB from the local chip's Memory due to a data side request. When using… [all …]
H A D	other.json	50 …dified (M) data from another core's ECO L3 on the same chip due to a data side request. When using… 455 "BriefDescription": "D-side L2 MRU touch commands sent to the L2" 510 …red (S) data from another core's L2 on the same chip due to a marked data side request. When using… 660 …"BriefDescription": "All D-side-Ld or I-side-instruction-fetch dispatch attempts for this thread t… 705 …"BriefDescription": "All successful D-side-Ld/St or I-side-instruction-fetch dispatches for this t… 825 …"BriefDescription": "All successful D-side-Ld or I-side-instruction-fetch dispatches for this thre… 845 …"BriefDescription": "All D-side-Ld or I-side-instruction-fetch dispatch attempts for this thread t… 1055 …nother core's L2/L3 on a different chip (remote or distant) due to a data side request. When using… 1125 …ble Entry was loaded into the TLB from the local chip's L4 cache due to a instruction side request" 1160 …"BriefDescription": "All I-side-instruction-fetch dispatch attempts for this thread that failed du… [all …]
/linux/tools/perf/pmu-events/arch/arm64/ampere/ampereone/
H A D	core-imp-def.json	513 "PublicDescription": "L2 refill from I-side miss", 516 "BriefDescription": "L2 refill from I-side miss" 519 "PublicDescription": "L2 refill from D-side miss", 522 "BriefDescription": "L2 refill from D-side miss" 537 "PublicDescription": "D-side Stage1 tablewalk fault", 540 "BriefDescription": "D-side Stage1 tablewalk fault" 543 "PublicDescription": "D-side Stage2 tablewalk fault", 546 "BriefDescription": "D-side Stage2 tablewalk fault" 549 "PublicDescription": "D-side Tablewalk steps or descriptor fetches", 552 "BriefDescription": "D-side Tablewalk steps or descriptor fetches" [all …]
/linux/drivers/char/ipmi/
H A D	Kconfig	`118 The driver implements the BMC side of the KCS contorller, it 119 provides the access of KCS IO space for BMC side. 130 The driver implements the BMC side of the KCS contorller, it 131 provides the access of KCS IO space for BMC side. 140 Provides a BMC-side character device implementing IPMI 171 implements the BMC side of the BT interface. 178 management (BMC) side. 180 The driver implements the BMC side of the SMBus system`
/linux/tools/perf/pmu-events/arch/x86/ivytown/
H A D	uncore-cache.json	224 …side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise rin… 234 …side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise rin… 244 …side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise rin… 254 …side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise rin… 264 …side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise rin… 274 …side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise rin… 284 …side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise rin… 294 …side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise rin… 304 …side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise rin… 314 …side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise rin… [all …]
/linux/drivers/media/platform/mediatek/vcodec/encoder/venc/
H A D	venc_h264_if.c	101 * @vpua: VPU side memory addr which is used by RC_CODE 114 * This structure is allocated in VPU side and shared to AP side. 116 * @work_bufs: working buffer information in VPU side 117 * The work_bufs here is for storing the 'size' info shared to AP side. 119 * in AP side. The AP driver will copy the 'size' from here to the one in 122 * register setting in VPU side. 175 * @vpua: VPU side memory addr which is used by RC_CODE 188 * @work_bufs: working buffer information in VPU side 206 * @vsi: driver structure allocated by VPU side and shared to AP side for 208 * @vsi_34: driver structure allocated by VPU side and shared to AP side for [all …]
/linux/drivers/block/rnbd/
H A D	README	`12 on the client side as local block devices. 26 Server side: 29 Client side: 39 mapped from the server side. After the session to the server machine is 40 established, the mapped device will appear on the client side under 51 to the block device on the server side by concatenating dev_search_path 73 information: side, max_hw_sectors, etc.`
/linux/arch/arm/mm/
H A D	pmsa-v7.c	52 /* Data-side / unified region attributes / 76 / Optional instruction-side region attributes / 78 / I-side Region access control register / 84 / I-side Region size register / 90 / I-side Region base address register / 108 / Data-side / unified region attributes / 137 / ARMv7-M only supports a unified MPU, so I-side operations are nop / 316 We don't support a different number of I/D side regions so if we in __mpu_max_regions() 318 * whichever side has a smaller number of supported regions. in __mpu_max_regions() 326 /* Check for separate d-side and i-side memory maps */ in __mpu_max_regions() [all …]

12 3 4 5 6 7 8 9 10 >>...76