| /linux/tools/perf/pmu-events/arch/arm64/ampere/ampereonex/ |
| H A D | mmu.json | 45 "PublicDescrition": "Data-side S1 page walk cache lookup",
48 "BriefDescription": "Data-side S1 page walk cache lookup"
51 "PublicDescrition": "Data-side S1 page walk cache refill",
54 "BriefDescription": "Data-side S1 page walk cache refill"
57 "PublicDescrition": "Data-side S2 page walk cache lookup",
60 "BriefDescription": "Data-side S2 page walk cache lookup"
63 "PublicDescrition": "Data-side S2 page walk cache refill",
66 "BriefDescription": "Data-side S2 page walk cache refill"
69 "PublicDescription": "Data-side S1 table walk fault",
72 "BriefDescription": "Data-side S1 table walk fault"
[all …]
|
| /linux/sound/hda/codecs/side-codecs/ |
| H A D | Kconfig | 5 tristate "KUnit test for Cirrus side-codec library" if !KUNIT_ALL_TESTS
9 This builds KUnit tests for the cirrus side-codec library.
25 tristate "Build CS35L41 HD-audio side codec support for I2C Bus"
34 Say Y or M here to include CS35L41 I2C HD-audio side codec support
37 comment "Set to Y if you want auto-loading the side codec driver"
50 Say Y or M here to include CS35L41 SPI HD-audio side codec support
53 comment "Set to Y if you want auto-loading the side codec driver"
60 tristate "Build CS35L56 HD-audio side codec support for I2C Bus"
76 tristate "Build CS35L56 HD-audio side codec support for SPI Bus"
111 tristate "Build TAS2781 HD-audio side code
[all...] |
| /linux/tools/perf/pmu-events/arch/powerpc/power8/ |
| H A D | translation.json | 29 …r chip's L2 or L3 on a different Node or Group (Distant), as this chip due to a data side request",
35 …r chip's L2 or L3 on a different Node or Group (Distant), as this chip due to a data side request",
41 …ion": "A Page Table Entry was loaded into the TLB from local core's L2 due to a data side request",
47 …was loaded into the TLB from a location other than the local core's L2 due to a data side request",
53 …TLB from local core's L2 hit without dispatch conflicts on Mepf state. due to a data side request",
59 …le Entry was loaded into the TLB from local core's L2 without conflict due to a data side request",
65 …ion": "A Page Table Entry was loaded into the TLB from local core's L3 due to a data side request",
71 …ry was loaded into the TLB from local core's L3 with dispatch conflict due to a data side request",
77 …TLB from local core's L3 without dispatch conflicts hit on Mepf state. due to a data side request",
83 …le Entry was loaded into the TLB from local core's L3 without conflict due to a data side request",
[all …]
|
| H A D | marked.json | 365 …s L2 or L3 on a different Node or Group (Distant), as this chip due to a marked data side request",
371 …s L2 or L3 on a different Node or Group (Distant), as this chip due to a marked data side request",
377 …B from another chip's L4 on a different Node or Group (Distant) due to a marked data side request",
383 … from another chip's memory on the same Node or Group (Distant) due to a marked data side request",
389 …A Page Table Entry was loaded into the TLB from local core's L2 due to a marked data side request",
395 …ded into the TLB from a location other than the local core's L2 due to a marked data side request",
401 …m local core's L2 hit without dispatch conflicts on Mepf state. due to a marked data side request",
407 …y was loaded into the TLB from local core's L2 without conflict due to a marked data side request",
413 …A Page Table Entry was loaded into the TLB from local core's L3 due to a marked data side request",
419 …ded into the TLB from a location other than the local core's L3 due to a marked data side request",
[all …]
|
| H A D | frontend.json | 293 …s L2 or L3 on a different Node or Group (Distant), as this chip due to a instruction side request",
299 …s L2 or L3 on a different Node or Group (Distant), as this chip due to a instruction side request",
305 …B from another chip's L4 on a different Node or Group (Distant) due to a instruction side request",
311 … from another chip's memory on the same Node or Group (Distant) due to a instruction side request",
317 …A Page Table Entry was loaded into the TLB from local core's L2 due to a instruction side request",
323 …ded into the TLB from a location other than the local core's L2 due to a instruction side request",
329 …m local core's L2 hit without dispatch conflicts on Mepf state. due to a instruction side request",
335 …y was loaded into the TLB from local core's L2 without conflict due to a instruction side request",
341 …A Page Table Entry was loaded into the TLB from local core's L3 due to a instruction side request",
347 …ded into the TLB from a location other than the local core's L3 due to a instruction side request",
[all …]
|
| /linux/Documentation/usb/ |
| H A D | gadget_serial.rst | 57 side driver. It runs on a Linux system that has USB device side
66 | Host-Side CDC ACM USB Host |
78 | Device-Side | Gadget | Controller | |
84 On the device-side Linux system, the gadget serial driver looks
87 On the host-side system, the gadget serial device looks like a
92 The host side driver can potentially be any ACM compliant driver
98 With the gadget serial driver and the host side ACM or generic
100 the host and the gadget side systems as if they were connected by a
111 side kernel for "Support for USB Gadgets", for a "USB Peripheral
128 side Linux system. You can add this to the start up scripts, if
[all …]
|
| /linux/tools/perf/pmu-events/arch/x86/silvermont/ |
| H A D | virtual-memory.json | 13 "BriefDescription": "Total cycles for all the page walks. (I-side and D-side)",
22 "BriefDescription": "Duration of D-side page-walks in core cycles",
26 …"PublicDescription": "This event counts every cycle when a D-side (walks due to a load) page walk …
31 "BriefDescription": "D-side page-walks",
41 "BriefDescription": "Duration of I-side page-walks in core cycles",
45 …"PublicDescription": "This event counts every cycle when a I-side (walks due to an instruction fet…
50 "BriefDescription": "I-side page-walks",
60 "BriefDescription": "Total page walks that are completed (I-side and D-side)",
|
| /linux/Documentation/devicetree/bindings/memory-controllers/ |
| H A D | rockchip,rk3399-dmc.yaml | 132 the ODT on the DRAM side and controller side are both disabled.
138 When the DRAM type is DDR3, this parameter defines the DRAM side drive
146 When the DRAM type is DDR3, this parameter defines the DRAM side ODT
154 When the DRAM type is DDR3, this parameter defines the phy side CA line
162 When the DRAM type is DDR3, this parameter defines the PHY side DQ line
170 When the DRAM type is DDR3, this parameter defines the PHY side ODT
180 ODT on the DRAM side and controller side are both disabled.
186 When the DRAM type is LPDDR3, this parameter defines the DRAM side drive
194 When the DRAM type is LPDDR3, this parameter defines the DRAM side ODT
202 When the DRAM type is LPDDR3, this parameter defines the PHY side CA line
[all …]
|
| /linux/Documentation/RCU/ |
| H A D | checklist.rst | 18 tool for the job. Yes, RCU does reduce read-side overhead by
19 increasing write-side overhead, which is exactly why normal uses
28 read-side primitives is critically important.
59 2. Do the RCU read-side critical sections make proper use of
63 under your read-side code, which can greatly increase the
68 rcu_read_lock_sched(), or by the appropriate update-side lock.
72 raw spinlock also enters an RCU read-side critical section.
76 respectively, as the RCU read-side critical section. Use of
84 Letting RCU-protected pointers "leak" out of an RCU read-side
88 *before* letting them out of the RCU read-side critical section.
[all …]
|
| H A D | whatisRCU.rst | 106 b. Wait for all previous readers to complete their RCU read-side
169 reclaimer that the reader is entering an RCU read-side critical
170 section. It is illegal to block while in an RCU read-side
172 can preempt RCU read-side critical sections. Any RCU-protected
173 data structure accessed during an RCU read-side critical section
179 or interrupts also enters an RCU read-side critical section.
180 Acquiring a spinlock also enters an RCU read-side critical
183 Sleeplocks do *not* enter RCU read-side critical sections.
190 reclaimer that the reader is exiting an RCU read-side critical
192 or interrupts also exits an RCU read-side critical section.
[all …]
|
| /linux/tools/perf/pmu-events/arch/x86/knightslanding/ |
| H A D | virtual-memory.json | 22 …"BriefDescription": "Counts the total number of core cycles for all the D-side page walks. The cyc…
30 …"BriefDescription": "Counts the total D-side page walks that are completed or started. The page wa…
39 …"BriefDescription": "Counts the total number of core cycles for all the I-side page walks. The cyc…
43 …"PublicDescription": "This event counts every cycle when an I-side (walks due to an instruction fe…
48 "BriefDescription": "Counts the total I-side page walks that are completed.",
57 "BriefDescription": "Counts the total page walks that are completed (I-side and D-side)",
|
| /linux/include/linux/ |
| H A D | srcu.h | 154 * srcu_read_lock_held - might we be in SRCU read-side critical section?
158 * read-side critical section. In absence of CONFIG_DEBUG_LOCK_ALLOC,
159 * this assumes we are in an SRCU read-side critical section unless it can
180 * srcu_lock_sync(), which is basically an empty *write*-side critical section,
228 * really are in an SRCU read-side critical section.
229 * @c: condition to check for update-side use
231 * If PROVE_RCU is enabled, invoking this outside of an RCU read-side
250 * really are in an SRCU read-side critical section.
253 * is enabled, invoking this outside of an RCU read-side critical
262 * really are in an SRCU read-side critica
[all...] |
| H A D | seqlock.h | 95 * that the write side critical section is properly serialized.
98 * preemption protection is enforced in the write side function.
113 * that the write side critical section is properly serialized.
483 * write_seqcount_begin() - start a seqcount_t write side critical section
486 * Context: sequence counter write side sections must be serialized and
508 * write_seqcount_end() - end a seqcount_t write side critical section
583 * side operations
586 * After write_seqcount_invalidate, no seqcount_t read side operations
605 * typically NMIs, to safely interrupt the write side critical section.
830 * read_seqbegin() - start a seqlock_t read side critica
[all...] |
| /linux/tools/perf/pmu-events/arch/powerpc/power9/ |
| H A D | translation.json | 25 …m another chip's memory on the same Node or Group (Distant) due to a data side request. When using…
35 …chip's L2 or L3 on the same Node or Group (Remote), as this chip due to a instruction side request"
60 … or L3 on a different Node or Group (Distant), as this chip due to a data side request. When using…
75 …ared or modified data from another core's L2/L3 on the same chip due to a instruction side request"
100 …e TLB from another chip's L4 on the same Node or Group ( Remote) due to a instruction side request"
145 …from a memory location including L4 from local remote or distant due to a instruction side request"
150 …rom another core's L2/L3 on a different chip (remote or distant) due to a instruction side request"
165 … or L3 on a different Node or Group (Distant), as this chip due to a data side request. When using…
185 …om another chip's L4 on a different Node or Group (Distant) due to a data side request. When using…
210 …chip's L2 or L3 on the same Node or Group (Remote), as this chip due to a instruction side request"
[all …]
|
| H A D | pipeline.json | 35 …her chip's L4 on a different Node or Group (Distant) due to a marked data side request. When using…
40 …s loaded into the TLB from local core's L2 without conflict due to a data side request. When using…
80 …ied (M) data from another core's L2 on the same chip due to a marked data side request. When using…
95 …h Modified (M) data from another core's L2 on the same chip due to a data side request. When using…
115 …e's L3 without dispatch conflicts hit on Mepf state. due to a marked data side request. When using…
160 …core's L2/L3 on a different chip (remote or distant) due to a marked data side request. When using…
175 …ed into the TLB from local core's L3 with dispatch conflict due to a data side request. When using…
180 …d into the TLB from local core's L2 without conflict due to a marked data side request. When using…
225 …d into the TLB from local core's L3 without conflict due to a marked data side request. When using…
250 …s L2 or L3 on the same Node or Group (Remote), as this chip due to a data side request. When using…
[all …]
|
| H A D | pmc.json | 20 …on a different Node or Group (Distant), as this chip due to a marked data side request. When using…
30 …into the TLB from a location other than the local core's L3 due to a data side request. When using…
40 …e TLB from a location other than the local core's L2 due to a marked data side request.. When usin…
90 …a memory location including L4 from local remote or distant due to a data side request. When using…
95 … the TLB from local core's L3 with dispatch conflict due to a marked data side request. When using…
100 …e Entry was loaded into the TLB from local core's L3 due to a marked data side request. When using…
110 …ntry was loaded into the TLB from the local chip's L4 cache due to a data side request. When using…
|
| H A D | marked.json | 20 …ith Shared (S) data from another core's L3 on the same chip due to a data side request. When using…
60 …s loaded into the TLB from the local chip's L4 cache due to a marked data side request.. When usin…
70 …(S) data from another core's ECO L3 on the same chip due to a marked data side request. When using…
95 …(M) data from another core's ECO L3 on the same chip due to a marked data side request. When using…
100 …Shared (S) data from another core's ECO L3 on the same chip due to a data side request. When using…
140 …aded into the TLB from a location other than the local core's L2 due to a instruction side request"
170 …om local core's L2 hit without dispatch conflicts on Mepf state. due to a instruction side request"
210 …was loaded into the TLB from the local chip's Memory due to a marked data side request. When using…
220 …e TLB from a location other than the local core's L3 due to a marked data side request. When using…
290 … Entry was loaded into the TLB from the local chip's Memory due to a data side request. When using…
[all …]
|
| /linux/tools/perf/pmu-events/arch/arm64/ampere/ampereone/ |
| H A D | core-imp-def.json | 513 "PublicDescription": "L2 refill from I-side miss",
516 "BriefDescription": "L2 refill from I-side miss"
519 "PublicDescription": "L2 refill from D-side miss",
522 "BriefDescription": "L2 refill from D-side miss"
537 "PublicDescription": "D-side Stage1 tablewalk fault",
540 "BriefDescription": "D-side Stage1 tablewalk fault"
543 "PublicDescription": "D-side Stage2 tablewalk fault",
546 "BriefDescription": "D-side Stage2 tablewalk fault"
549 "PublicDescription": "D-side Tablewalk steps or descriptor fetches",
552 "BriefDescription": "D-side Tablewalk steps or descriptor fetches"
[all …]
|
| /linux/drivers/nvme/target/ |
| H A D | Kconfig | 11 This enabled target side support for the NVMe protocol, that is
34 This enables target side NVMe passthru controller support for the
37 side, including executing Vendor Unique Commands.
48 to test NVMe host and target side features.
111 bool "NVMe over Fabrics In-band Authentication in target side"
116 target side.
|
| /linux/drivers/block/rnbd/ |
| H A D | README | 12 on the client side as local block devices.
26 Server side:
29 Client side:
39 mapped from the server side. After the session to the server machine is
40 established, the mapped device will appear on the client side under
51 to the block device on the server side by concatenating dev_search_path
73 information: side, max_hw_sectors, etc.
|
| /linux/tools/perf/pmu-events/arch/x86/ivytown/ |
| H A D | uncore-cache.json | 224 …side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise rin…
234 …side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise rin…
244 …side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise rin…
254 …side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise rin…
264 …side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise rin…
274 …side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise rin…
284 …side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise rin…
294 …side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise rin…
304 …side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise rin…
314 …side of the ring, the UP direction is on the clockwise ring and DN is on the counter-clockwise rin…
[all …]
|
| /linux/arch/arm/mm/ |
| H A D | pmsa-v7.c | 52 /* Data-side / unified region attributes */
76 /* Optional instruction-side region attributes */
78 /* I-side Region access control register */
84 /* I-side Region size register */
90 /* I-side Region base address register */
108 /* Data-side / unified region attributes */
137 /* ARMv7-M only supports a unified MPU, so I-side operations are nop */
316 * We don't support a different number of I/D side regions so if we in __mpu_max_regions()
318 * whichever side has a smaller number of supported regions. in __mpu_max_regions()
326 /* Check for separate d-side and i-side memory maps */ in __mpu_max_regions()
[all …]
|
| /linux/tools/testing/selftests/drivers/net/bonding/ |
| H A D | bond_passive_lacp.sh | 66 # 1. The passive side shouldn't send LACPDU.
71 # 2. The passive side should not have the 'active' flag.
76 # 3. The active side should have the 'active' flag.
87 # After testing, disconnect one port on each side to check the state.
97 # 5. The active side should keep sending LACPDU.
101 # 6. The passive side shouldn't send LACPDU anymore.
|
| /linux/tools/perf/pmu-events/arch/arm64/arm/cortex-a73/ |
| H A D | pipeline.json | 3 "PublicDescription": "A linefill caused an instruction side stall",
6 "BriefDescription": "A linefill caused an instruction side stall"
9 "PublicDescription": "A translation table walk caused an instruction side stall",
12 "BriefDescription": "A translation table walk caused an instruction side stall"
|
| /linux/drivers/media/platform/mediatek/vcodec/encoder/venc/ |
| H A D | venc_vp8_if.c | 81 * @vpua: VPU side memory addr which is used by RC_CODE
94 * This structure is allocated in VPU side and shared to AP side.
96 * @work_bufs: working buffer information in VPU side
97 * The work_bufs here is for storing the 'size' info shared to AP side.
99 * in AP side. The AP driver will copy the 'size' from here to the one in
102 * register setting in VPU side.
119 * @vsi: driver structure allocated by VPU side and shared to AP side for
161 * This 'wb' structure is set by VPU side and shared to AP for in vp8_enc_alloc_work_buf()
165 * RC_CODEx buffers, they are pre-allocated in the VPU side in vp8_enc_alloc_work_buf()
179 * virtual addr in 'iova' field for reg setting in VPU side. in vp8_enc_alloc_work_buf()
|