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/linux/arch/mips/include/asm/
H A Dmips-gic.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
8 # error Please include asm/mips-cps.h rather than asm/mips-gic.h
29 /* For read-only shared registers */
34 /* For read-write shared registers */
39 /* For read-only local registers */
44 /* For read-write local registers */
49 /* For read-only shared per-interrupt registers */
62 /* For read-write shared per-interrupt registers */
81 /* For read-only local per-interrupt registers */
88 /* For read-write local per-interrupt registers */
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/linux/drivers/net/ipa/
H A Dipa_uc.c1 // SPDX-License-Identifier: GPL-2.0
3 /* Copyright (c) 2012-2018, The Linux Foundation. All rights reserved.
4 * Copyright (C) 2018-2024 Linaro Ltd.
26 * The microcontroller can generate two interrupts to the AP. One interrupt
29 * addition, the AP can interrupt the microcontroller by writing a register.
33 * AP and the IPA microcontroller. Each side writes data to the shared area
35 * to the interrupt. Some information found in the shared area is currently
36 * unused. All remaining space in the shared area is reserved, and must not
45 * struct ipa_uc_mem_area - AP/microcontroller shared memory area
46 * @command: command code (AP->microcontroller)
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/linux/Documentation/devicetree/bindings/interrupt-controller/
H A Dfsl,ls-msi.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/interrupt-controller/fsl,ls-msi.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 This interrupt controller hardware is a second level interrupt controller that
11 is hooked to a parent interrupt controller: e.g: ARM GIC for ARM-based
12 platforms. If interrupt-parent is not provided, the default parent interrupt
15 Each PCIe node needs to have property msi-parent that points to
19 - Frank Li <Frank.Li@nxp.com>
24 - fsl,ls1012a-msi
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H A Dst,spear300-shirq.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/interrupt-controller/st,spear300-shirq.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: SPEAr3xx Shared IRQ controller
10 - Viresh Kumar <vireshk@kernel.org>
11 - Shiraz Hashim <shiraz.linux.kernel@gmail.com>
14 SPEAr3xx architecture includes shared/multiplexed irqs for certain set of
15 devices. The multiplexor provides a single interrupt to parent interrupt
24 A single node in the device tree is used to describe the shared interrupt
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H A Dfsl,mpic-msi.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/interrupt-controller/fsl,mpic-msi.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Freescale MSI interrupt controller
10 The Freescale hypervisor and msi-address-64
11 -------------------------------------------
39 this. The address specified in the msi-address-64 property is the PCI
44 - J. Neuschäfer <j.ne@posteo.net>
49 - enum:
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/linux/Documentation/devicetree/bindings/mailbox/
H A Dnvidia,tegra186-hsp.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/mailbox/nvidia,tegra186-hsp.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Jon Hunter <jonathanh@nvidia.com>
21 The features that HSP supported are shared mailboxes, shared
29 For shared mailboxes, the first cell composed of two fields:
30 - bits 15..8:
31 A bit mask of flags that further specifies the type of shared
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/linux/arch/arm/mach-omap2/
H A Dprcm-common.h1 /* SPDX-License-Identifier: GPL-2.0-only */
8 * Copyright (C) 2007-2009, 2011 Texas Instruments, Inc.
9 * Copyright (C) 2007-2009 Nokia Corporation
30 /* Chip-specific module offsets */
37 #define OMAP3430_IVA2_MOD -0x800
66 /* 24XX register bits shared between CM & PRM registers */
68 /* CM_FCLKEN1_CORE, CM_ICLKEN1_CORE, PM_WKEN1_CORE shared bits */
108 /* CM_FCLKEN2_CORE, CM_ICLKEN2_CORE, PM_WKEN2_CORE shared bits */
122 /* CM_ICLKEN2_CORE, PM_WKEN2_CORE shared bits */
130 /* CM_IDLEST1_CORE, PM_WKST1_CORE shared bits */
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/linux/Documentation/devicetree/bindings/display/ti/
H A Dti,j721e-dss.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/display/ti/ti,j721e-dss.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - Jyri Sarha <jsarha@ti.com>
12 - Tomi Valkeinen <tomi.valkeinen@ti.com>
22 const: ti,j721e-dss
26 - description: common_m DSS Master common
27 - description: common_s0 DSS Shared common 0
28 - description: common_s1 DSS Shared common 1
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/linux/drivers/net/ethernet/aquantia/atlantic/hw_atl2/
H A Dhw_atl2_llh.h1 /* SPDX-License-Identifier: GPL-2.0-only */
13 /* Set TX Interrupt Moderation Control Register */
41 /* set tx random TC-queue mapping enable bit */
72 /* get data from firmware shared input buffer */
76 /* set data into firmware shared input buffer */
80 /* get data from firmware shared output buffer */
84 /* set host finished write shared buffer indication */
87 /* get mcp finished read shared buffer indication */
96 /* get host interrupt request */
99 /* clear host interrupt request */
/linux/Documentation/power/
H A Dsuspend-and-interrupts.rst10 -----------------------------------
12 Device interrupt request lines (IRQs) are generally disabled during system
14 ->prepare, ->suspend and ->suspend_late callbacks have been executed for all
21 interrupt handlers for shared IRQs that device drivers implementing them were
29 Device IRQs are re-enabled during system resume, right before the "early" phase
30 of resuming devices (that is, before starting to execute ->resume_early
35 ------------------------
38 suspend-resume cycle, including the "noirq" phases of suspending and resuming
41 but also to IPIs and to some other special-purpose interrupts.
44 requesting a special-purpose interrupt. It causes suspend_device_irqs() to
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/linux/Documentation/devicetree/bindings/soc/qcom/
H A Dqcom,smsm.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm Shared Memory State Machine
10 - Andy Gross <agross@kernel.org>
11 - Bjorn Andersson <bjorn.andersson@linaro.org>
12 - Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
15 The Shared Memory State Machine facilitates broadcasting of single bit state
25 '#address-cells':
28 qcom,local-host:
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/linux/arch/arm/boot/dts/st/
H A Dstm32mp15xx-osd32.dtsi1 /* SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-3-Clause) */
3 * Copyright (C) 2020 STMicroelectronics - All Rights Reserved
7 #include "stm32mp15-pinctrl.dtsi"
9 #include <dt-bindings/mfd/st,stpmic1.h>
12 reserved-memory {
13 #address-cells = <1>;
14 #size-cells = <1>;
18 compatible = "shared-dma-pool";
20 no-map;
24 compatible = "shared-dma-pool";
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H A Dstm32mp157c-odyssey-som.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
6 /dts-v1/;
10 #include "stm32mp15-pinctrl.dtsi"
11 #include "stm32mp15xxac-pinctrl.dtsi"
12 #include <dt-bindings/gpio/gpio.h>
13 #include <dt-bindings/leds/common.h>
14 #include <dt-bindings/mfd/st,stpmic1.h>
17 model = "Seeed Studio Odyssey-STM32MP157C SOM";
18 compatible = "seeed,stm32mp157c-odyssey-som", "st,stm32mp157";
25 reserved-memory {
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H A Dstm32mp15xx-dhcor-som.dtsi1 // SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause)
3 * Copyright (C) Linaro Ltd 2019 - All Rights Reserved
8 #include "stm32mp15-pinctrl.dtsi"
9 #include "stm32mp15xxac-pinctrl.dtsi"
10 #include <dt-bindings/gpio/gpio.h>
11 #include <dt-bindings/mfd/st,stpmic1.h>
23 reserved-memory {
24 #address-cells = <1>;
25 #size-cells = <1>;
29 compatible = "shared-dma-pool";
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H A Dste-href-tvk1281618-r2.dtsi1 // SPDX-License-Identifier: GPL-2.0-or-later
6 #include <dt-bindings/interrupt-controller/irq.h>
7 #include <dt-bindings/input/input.h>
11 compatible = "gpio-keys";
12 #address-cells = <1>;
13 #size-cells = <0>;
14 vdd-supply = <&ab8500_ldo_aux1_reg>;
15 pinctrl-names = "default";
16 pinctrl-0 = <&prox_tvk_mode>, <&hall_tvk_mode>;
37 interrupt-parent = <&gpio6>;
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/linux/arch/arm/mach-shmobile/
H A Dregulator-quirk-rcar-gen2.c1 // SPDX-License-Identifier: GPL-2.0
3 * R-Car Generation 2 da9063(L)/da9210 regulator quirk
6 * regulators. All of these regulators have their interrupt request lines
7 * tied to the same interrupt pin (IRQ2) on the SoC.
9 * After cold boot or da9063-induced restart, both the da9063 and da9210 seem
10 * to assert their interrupt request lines. Hence as soon as one driver
11 * requests this irq, it gets stuck in an interrupt storm, as it only manages
12 * to deassert its own interrupt request line, and the other driver hasn't
13 * installed an interrupt handler yet.
46 bool shared; /* IRQ line is shared */ member
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/linux/Documentation/devicetree/bindings/gpio/
H A Dsprd,gpio.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 ---
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - Orson Zhai <orsonzhai@gmail.com>
12 - Baolin Wang <baolin.wang7@gmail.com>
13 - Chunyan Zhang <zhang.lyra@gmail.com>
16 The controller's registers are organized as sets of sixteen 16-bit
18 interrupt is shared for all of the banks handled by the controller.
23 - const: sprd,sc9860-gpio
24 - items:
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H A Dfsl-imx-gpio.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/gpio/fsl-imx-gpio.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Shawn Guo <shawnguo@kernel.org>
11 - Sascha Hauer <s.hauer@pengutronix.de>
12 - Fabio Estevam <festevam@gmail.com>
17 - enum:
18 - fsl,imx1-gpio
19 - fsl,imx21-gpio
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/linux/Documentation/devicetree/bindings/net/
H A Dcavium-mix.txt4 - compatible: "cavium,octeon-5750-mix"
9 - reg: The base addresses of four separate register banks. The first
11 AGL registers. The third bank are the AGL registers shared by all
12 MIX devices present. The fourth bank is the AGL_PRT_CTL shared by
15 - cell-index: A single cell specifying which portion of the shared
18 - interrupts: Two interrupt specifiers. The first is the MIX
19 interrupt routing and the second the routing for the AGL interrupts.
21 - phy-handle: Optional, see ethernet.txt file in the same directory.
25 compatible = "cavium,octeon-5750-mix";
30 cell-index = <1>;
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/linux/drivers/soc/qcom/
H A Dsmsm.c1 // SPDX-License-Identifier: GPL-2.0-only
4 * Copyright (c) 2012-2013, The Linux Foundation. All rights reserved.
7 #include <linux/interrupt.h>
19 * This driver implements the Qualcomm Shared Memory State Machine, a mechanism
22 * The implementation is based on two sections of shared memory; the first
27 * read-write, while the rest should be considered read-only.
34 * The subscription matrix is laid out in entry-major order:
40 * A third, optional, shared memory region might contain information regarding
46 * Shared memory identifiers, used to acquire handles to respective memory
63 * struct qcom_smsm - smsm driver context
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/linux/drivers/irqchip/
H A Dspear-shirq.c2 * SPEAr platform shared irq layer source file
4 * Copyright (C) 2009-2012 ST Microelectronics
18 #include <linux/interrupt.h>
29 * struct spear_shirq: shared irq structure
32 * status_reg: Status register offset for chained interrupt handler
35 * virq_base: Base virtual interrupt number
37 * offset: Bit offset of the first interrupt
38 * irq_chip: Interrupt controller chip used for this instance,
52 /* spear300 shared irq registers offsets and masks */
61 u32 val, shift = d->irq - shirq->virq_base + shirq->offset; in shirq_irq_mask()
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/linux/Documentation/driver-api/
H A Dntb.rst5 NTB (Non-Transparent Bridge) is a type of PCI-Express bridge chip that connects
6 the separate memory systems of two or more computers to the same PCI-Express
9 scratchpad and message registers. Scratchpad registers are read-and-writable
14 peer. Doorbell registers provide a way for peers to send interrupt events.
36 ----------------------------------------
50 | dma-mapped |-ntb_mw_set_trans(addr) |
52 | (addr) |<======| MW xlat addr |<====| MW base addr |<== memory-mapped IO
53 |------------| |--------------| | |--------------|
58 maps corresponding outbound memory window so to have access to the shared
61 The second type of interface, that implies the shared windows being
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/linux/kernel/irq/
H A Dmanage.c1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 1992, 1998-2006 Linus Torvalds, Ingo Molnar
4 * Copyright (C) 2005-2006 Thomas Gleixner
15 #include <linux/interrupt.h>
50 while (irqd_irq_inprogress(&desc->irq_data)) in __synchronize_hardirq()
53 /* Ok, that indicated we're done: double-check carefully. */ in __synchronize_hardirq()
54 guard(raw_spinlock_irqsave)(&desc->lock); in __synchronize_hardirq()
55 inprogress = irqd_irq_inprogress(&desc->irq_data); in __synchronize_hardirq()
75 * synchronize_hardirq - wait for pending hard IRQ handlers (on other CPUs)
76 * @irq: interrupt number to wait for
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/linux/arch/mips/cavium-octeon/
H A DKconfig1 # SPDX-License-Identifier: GPL-2.0
11 non-CN63XXP1 hardware, so it is recommended to select "n"
51 bool "Lock the interrupt handler in L2"
55 Lock the low level interrupt handler into L2.
58 bool "Lock the 2nd level interrupt handler in L2"
62 Lock the 2nd level interrupt handler in L2.
72 int "Memory to reserve for user processes shared region (MB)"
76 Reserve a shared memory region for user processes to use for hardware
84 tristate "Module to measure interrupt latency using Octeon CIU Timer"
86 This driver is a module to measure interrupt latency using the
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/linux/Documentation/locking/
H A Dspinlocks.rst20 there is only one thread-of-control within the region(s) protected by that
26 Documentation/memory-barriers.txt
33 spinlock for most things - using more than one spinlock can make things a
41 shared data structures **everywhere** they are used. The spinlocks are most
45 NOTE! The spin-lock is safe only when you **also** use the lock itself
47 touches a shared variable has to agree about the spinlock they want
50 ----
52 Lesson 2: reader-writer spinlocks.
56 to mostly read from the shared variables, the reader-writer locks
61 NOTE! reader-writer locks require more atomic memory operations than
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