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/linux/drivers/net/ethernet/qualcomm/emac/
H A Demac-sgmii.c1 // SPDX-License-Identifier: GPL-2.0-only
2 /* Copyright (c) 2015-2016, The Linux Foundation. All rights reserved.
5 /* Qualcomm Technologies, Inc. EMAC SGMII Controller driver.
15 #include "emac-mac.h"
16 #include "emac-sgmii.h"
52 if (!(adpt->phy.sgmii_ops && adpt->phy.sgmii_ops->init)) in emac_sgmii_init()
55 return adpt->phy.sgmii_ops->init(adpt); in emac_sgmii_init()
60 if (!(adpt->phy.sgmii_ops && adpt->phy.sgmii_ops->open)) in emac_sgmii_open()
63 return adpt->phy.sgmii_ops->open(adpt); in emac_sgmii_open()
68 if (!(adpt->phy.sgmii_ops && adpt->phy.sgmii_ops->close)) in emac_sgmii_close()
[all …]
H A Demac-sgmii-qdf2400.c1 // SPDX-License-Identifier: GPL-2.0-only
2 /* Copyright (c) 2015-2016, The Linux Foundation. All rights reserved.
5 /* Qualcomm Technologies, Inc. QDF2400 EMAC SGMII Controller driver.
19 /* SGMII digital lane registers */
46 /* SGMII digital lane register values */
122 writel(itr->val, base + itr->offset); in emac_reg_write_all()
175 struct emac_sgmii *phy = &adpt->phy; in emac_sgmii_init_qdf2400() local
176 void __iomem *phy_regs = phy->base; in emac_sgmii_init_qdf2400()
177 void __iomem *laned = phy->digital; in emac_sgmii_init_qdf2400()
181 /* PCS lane-x init */ in emac_sgmii_init_qdf2400()
[all …]
H A Demac-sgmii-qdf2432.c1 // SPDX-License-Identifier: GPL-2.0-only
2 /* Copyright (c) 2015-2016, The Linux Foundation. All rights reserved.
5 /* Qualcomm Technologies, Inc. QDF2432 EMAC SGMII Controller driver.
19 /* SGMII digital lane registers */
44 /* SGMII digital lane register values */
112 writel(itr->val, base + itr->offset); in emac_reg_write_all()
162 struct emac_sgmii *phy = &adpt->phy; in emac_sgmii_init_qdf2432() local
163 void __iomem *phy_regs = phy->base; in emac_sgmii_init_qdf2432()
164 void __iomem *laned = phy->digital; in emac_sgmii_init_qdf2432()
168 /* PCS lane-x init */ in emac_sgmii_init_qdf2432()
[all …]
/linux/Documentation/devicetree/bindings/net/dsa/
H A Dqca8k.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - John Crispin <john@phrozen.org>
13 If the QCA8K switch is connect to an SoC's external mdio-bus, each subnode
14 describing a port needs to have a valid phandle referencing the internal PHY
15 it is connected to. This is because there is no N:N mapping of port and PHY
16 ID. To declare the internal mdio-bus configuration, declare an MDIO node in
18 PHY it is connected to. In this config, an internal mdio-bus is registered and
20 mdio-bus configurations are not supported by the hardware.
[all …]
/linux/arch/powerpc/boot/dts/fsl/
H A Dp5040ds.dts4 * Copyright 2012 - 2015 Freescale Semiconductor Inc.
35 /include/ "p5040si-pre.dtsi"
40 #address-cells = <2>;
41 #size-cells = <2>;
42 interrupt-parent = <&mpic>;
74 reserved-memory {
75 #address-cells = <2>;
76 #size-cells = <2>;
79 bman_fbpr: bman-fbpr {
83 qman_fqd: qman-fqd {
[all …]
H A Dt4240rdb.dts4 * Copyright 2014 - 2015 Freescale Semiconductor Inc.
35 /include/ "t4240si-pre.dtsi"
40 #address-cells = <2>;
41 #size-cells = <2>;
42 interrupt-parent = <&mpic>;
62 #address-cells = <1>;
63 #size-cells = <1>;
64 compatible = "cfi-flash";
67 bank-width = <2>;
68 device-width = <1>;
[all …]
H A Dp4080ds.dts4 * Copyright 2009 - 2015 Freescale Semiconductor Inc.
35 /include/ "p4080si-pre.dtsi"
40 #address-cells = <2>;
41 #size-cells = <2>;
42 interrupt-parent = <&mpic>;
62 reserved-memory {
63 #address-cells = <2>;
64 #size-cells = <2>;
67 bman_fbpr: bman-fbpr {
71 qman_fqd: qman-fqd {
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H A Dt4240qds.dts4 * Copyright 2012 - 2015 Freescale Semiconductor Inc.
35 /include/ "t4240si-pre.dtsi"
40 #address-cells = <2>;
41 #size-cells = <2>;
42 interrupt-parent = <&mpic>;
89 #address-cells = <1>;
90 #size-cells = <1>;
91 compatible = "cfi-flash";
94 bank-width = <2>;
95 device-width = <1>;
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H A Dt1042d4rdb.dts35 /include/ "t104xsi-pre.dtsi"
41 #address-cells = <2>;
42 #size-cells = <2>;
43 interrupt-parent = <&mpic>;
47 compatible = "fsl,t1040d4rdb-cpld",
48 "fsl,deepsleep-cpld";
55 phy-handle = <&phy_sgmii_0>;
56 phy-connection-type = "sgmii";
60 phy-handle = <&phy_sgmii_1>;
61 phy-connection-type = "sgmii";
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/linux/arch/arm64/boot/dts/freescale/
H A Dfsl-ls1046a-qds.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * Device Tree Include file for Freescale Layerscape-1046A family SoC.
6 * Copyright 2018-2019 NXP
11 /dts-v1/;
13 #include "fsl-ls1046a.dtsi"
17 compatible = "fsl,ls1046a-qds", "fsl,ls1046a";
20 emi1-slot1 = &ls1046mdio_s1;
21 emi1-slot2 = &ls1046mdio_s2;
22 emi1-slot4 = &ls1046mdio_s4;
27 qsgmii-s2-p1 = &qsgmii_phy_s2_p1;
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H A Dfsl-lx2162a-clearfog.dts1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
5 // Copyright 2023 Josua Mayer <josua@solid-run.com>
7 /dts-v1/;
9 #include "fsl-lx2160a.dtsi"
10 #include "fsl-lx2162a-sr-som.dtsi"
14 compatible = "solidrun,lx2162a-clearfog", "solidrun,lx2162a-som", "fsl,lx2160a";
35 stdout-path = "serial0:115200n8";
39 compatible = "gpio-leds";
41 led_sfp_at: led-sfp-at {
43 default-state = "off";
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H A Dfsl-ls1043a-qds.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * Device Tree Include file for Freescale Layerscape-1043A family SoC.
5 * Copyright 2014-2015 Freescale Semiconductor, Inc.
6 * Copyright 2018-2021 NXP
11 /dts-v1/;
12 #include "fsl-ls1043a.dtsi"
16 compatible = "fsl,ls1043a-qds", "fsl,ls1043a";
27 sgmii-riser-s1-p1 = &sgmii_phy_s1_p1;
28 sgmii-riser-s2-p1 = &sgmii_phy_s2_p1;
29 sgmii-riser-s3-p1 = &sgmii_phy_s3_p1;
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H A Dfsl-ls1028a-qds-9999.dtso1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
5 * Copyright 2019-2021 NXP
8 * Requires a SCH-24801 card in slot 1.
11 /dts-v1/;
15 #address-cells = <1>;
16 #size-cells = <0>;
19 slot1_sgmii0: ethernet-phy@1c {
23 slot1_sgmii1: ethernet-phy@1d {
27 slot1_sgmii2: ethernet-phy@1e {
31 slot1_sgmii3: ethernet-phy@1f {
[all …]
H A Dfsl-lx2160a-tqmlx2160a-mblx2160a_x_11_x.dtso1 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
3 * Copyright (c) 2020-2023 TQ-Systems GmbH <linux@ew.tq-group.com>,
4 * D-82229 Seefeld, Germany.
8 /dts-v1/;
12 phy-handle = <&dp83867_1_1>;
13 phy-connection-type = "sgmii";
14 managed = "in-band-status";
18 phy-handle = <&dp83867_1_5>;
19 phy-connection-type = "sgmii";
20 managed = "in-band-status";
[all …]
H A Dfsl-ls1028a-qds-899b.dtso1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
5 * Copyright 2019-2021 NXP
8 * Requires a SCH-24801 card in slot 1.
11 /dts-v1/;
15 #address-cells = <1>;
16 #size-cells = <0>;
19 slot1_sgmii0: ethernet-phy@1c {
23 slot1_sgmii1: ethernet-phy@1d {
27 slot1_sgmii2: ethernet-phy@1e {
31 slot1_sgmii3: ethernet-phy@1f {
[all …]
/linux/drivers/net/dsa/sja1105/
H A DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
11 This is the driver for the NXP SJA1105 (5-port) and SJA1110 (10-port)
15 - SJA1105E (Gen. 1, No TT-Ethernet)
16 - SJA1105T (Gen. 1, TT-Ethernet)
17 - SJA1105P (Gen. 2, No SGMII, No TT-Ethernet)
18 - SJA1105Q (Gen. 2, No SGMII, TT-Ethernet)
19 - SJA1105R (Gen. 2, SGMII, No TT-Ethernet)
20 - SJA1105S (Gen. 2, SGMII, TT-Ethernet)
21 - SJA1110A (Gen. 3, SGMII, TT-Ethernet, 100base-TX PHY, 10 ports)
22 - SJA1110B (Gen. 3, SGMII, TT-Ethernet, 100base-TX PHY, 9 ports)
[all …]
/linux/Documentation/devicetree/bindings/net/
H A Dqcom-emac.txt3 This network controller consists of two devices: a MAC and an SGMII
4 internal PHY. Each device is represented by a device tree node. A phandle
5 connects the MAC node to its corresponding internal phy node. Another
6 phandle points to the external PHY node.
11 - compatible : Should be "qcom,fsm9900-emac".
12 - reg : Offset and length of the register regions for the device
13 - interrupts : Interrupt number used by this controller
14 - mac-address : The 6-byte MAC address. If present, it is the default
16 - internal-phy : phandle to the internal PHY node
17 - phy-handle : phandle to the external PHY node
[all …]
H A Dxlnx,axi-ethernet.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/net/xlnx,axi-ethernet.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 provides connectivity to an external ethernet PHY supporting different
12 interfaces: MII, GMII, RGMII, SGMII, 1000BaseX. It also includes two
22 - Radhey Shyam Pandey <radhey.shyam.pandey@xilinx.com>
27 - xlnx,axi-ethernet-1.00.a
28 - xlnx,axi-ethernet-1.01.a
29 - xlnx,axi-ethernet-2.01.a
[all …]
/linux/arch/arm/boot/dts/broadcom/
H A Dbcm958625-meraki-alamo.dtsi1 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
5 * Copyright (C) 2020-2021 Matthew Hagan <mnhagan88@gmail.com>
8 #include "bcm958625-meraki-mx6x-common.dtsi"
12 compatible = "gpio-keys-polled";
14 poll-interval = <20>;
16 button-reset {
24 compatible = "gpio-leds";
26 led-0 {
27 /* green:wan1-left */
29 function-enumerator = <0>;
[all …]
/linux/arch/mips/boot/dts/mscc/
H A Docelot_pcb120.dts1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
4 /dts-v1/;
6 #include <dt-bindings/gpio/gpio.h>
7 #include <dt-bindings/interrupt-controller/irq.h>
8 #include <dt-bindings/phy/phy-ocelot-serdes.h>
12 compatible = "mscc,ocelot-pcb120", "mscc,ocelot";
15 stdout-path = "serial0:115200n8";
25 phy_int_pins: phy-int-pins {
30 phy_load_save_pins: phy-load-save-pins {
42 pinctrl-names = "default";
[all …]
/linux/arch/mips/boot/dts/cavium-octeon/
H A Docteon_68xx.dts1 // SPDX-License-Identifier: GPL-2.0
2 /dts-v1/;
7 * use. Because of this, it contains a super-set of the available
11 compatible = "cavium,octeon-6880";
12 #address-cells = <2>;
13 #size-cells = <2>;
14 interrupt-parent = <&ciu2>;
17 compatible = "simple-bus";
18 #address-cells = <2>;
19 #size-cells = <2>;
[all …]
/linux/Documentation/networking/dsa/
H A Dsja1105.rst8 The NXP SJA1105 is a family of 10 SPI-managed automotive switches:
10 - SJA1105E: First generation, no TTEthernet
11 - SJA1105T: First generation, TTEthernet
12 - SJA1105P: Second generation, no TTEthernet, no SGMII
13 - SJA1105Q: Second generation, TTEthernet, no SGMII
14 - SJA1105R: Second generation, no TTEthernet, SGMII
15 - SJA1105S: Second generation, TTEthernet, SGMII
16 - SJA1110A: Third generation, TTEthernet, SGMII, integrated 100base-T1 and
17 100base-TX PHYs
18 - SJA1110B: Third generation, TTEthernet, SGMII, 100base-T1, 100base-TX
[all …]
/linux/arch/arm64/boot/dts/marvell/
H A Dcn9131-cf-solidwan.dts1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (C) 2024 Josua Mayer <josua@solid-run.com>
9 /dts-v1/;
11 #include <dt-bindings/input/input.h>
12 #include <dt-bindings/leds/common.h>
15 #include "cn9130-sr-som.dtsi"
29 #include "armada-cp115.dtsi"
41 compatible = "solidrun,cn9131-solidwan",
42 "solidrun,cn9130-sr-som", "marvell,cn9130";
67 compatible = "gpio-leds";
[all …]
/linux/arch/arm64/boot/dts/renesas/
H A Dr8a779f0-spider-ethernet.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 * Device Tree Source for the Spider Ethernet sub-board
23 label = "ethernet-sub-board";
33 power-source = <1800>;
39 power-source = <1800>;
45 power-source = <1800>;
50 pinctrl-0 = <&tsn0_pins>, <&tsn1_pins>, <&tsn2_pins>;
51 pinctrl-names = "default";
57 phy-handle = <&u101>;
58 phy-mode = "sgmii";
[all …]
/linux/Documentation/networking/
H A Dphy-link-topology.rst1 .. SPDX-License-Identifier: GPL-2.0
5 PHY link topology
11 The PHY link topology representation in the networking stack aims at representing
19 +-----------------------+ +----------+ +--------------+
21 | MAC | ------ | PHY | ---- | Port | ---... to LP
22 +-----------------------+ +----------+ +--------------+
25 Commands that needs to configure the PHY will go through the net_device.phydev
26 field to reach the PHY and perform the relevant configuration.
32 interface, that can directly be fed to an SFP cage, such as SGMII, 1000BaseX,
37 +-----+ SGMII +------------+
[all …]

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