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Searched +full:sgmii +full:- +full:enable +full:- +full:pll (Results 1 – 17 of 17) sorted by relevance

/linux/arch/arm/boot/dts/broadcom/
H A Dbcm958625-meraki-alamo.dtsi1 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
5 * Copyright (C) 2020-2021 Matthew Hagan <mnhagan88@gmail.com>
8 #include "bcm958625-meraki-mx6x-common.dtsi"
12 compatible = "gpio-keys-polled";
14 poll-interval = <20>;
16 button-reset {
24 compatible = "gpio-leds";
26 led-0 {
27 /* green:wan1-left */
29 function-enumerator = <0>;
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/linux/Documentation/devicetree/bindings/net/dsa/
H A Dqca8k.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - John Crispin <john@phrozen.org>
13 If the QCA8K switch is connect to an SoC's external mdio-bus, each subnode
16 ID. To declare the internal mdio-bus configuration, declare an MDIO node in
18 PHY it is connected to. In this config, an internal mdio-bus is registered and
20 mdio-bus configurations are not supported by the hardware.
27 - enum:
28 - qca,qca8327
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/linux/drivers/phy/marvell/
H A Dphy-mvebu-a3700-comphy.c1 // SPDX-License-Identifier: GPL-2.0
11 * Structure inspired from phy-mvebu-cp110-comphy.c written by Antoine Tenart.
41 * since the registers are 16-bit.
184 #define COMPHY_PHY_REG(lane, reg) (((1 - (lane)) * 0x28) + ((reg) & 0x3f))
189 * (used only by SGMII code)
210 * (used only by SGMII code)
301 /*-----------------------------------------------------------*/
392 priv->lane2_phy_indirect + COMPHY_LANE2_INDIR_ADDR); in comphy_set_indirect()
393 comphy_reg_set(priv->lane2_phy_indirect + COMPHY_LANE2_INDIR_DATA, in comphy_set_indirect()
400 if (lane->id == 2) { in comphy_lane_reg_set()
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/linux/drivers/net/dsa/
H A Dmt7530.h1 /* SPDX-License-Identifier: GPL-2.0-only */
15 #define MT7530_MAX_MTU (15 * 1024 - ETH_HLEN - ETH_FCS_LEN - MTK_HDR_LEN)
106 /* Register for 01-80-C2-00-00-[01,02] MAC DA frame control */
118 /* Register for 01-80-C2-00-00-[03,0E] MAC DA frame control */
337 /* Register for port port-and-protocol based vlan 1 control */
442 /* MT7531 SGMII register group */
443 #define MT7531_SGMII_REG_BASE(p) (0x5000 + ((p) - 5) * 0x1000)
577 /* Registers for RGMII and SGMII PLL clock */
639 /* LED enable, 0: Disable, 1: Enable (Default) */
645 /* GPIO output enable, 0: Disable, 1: Enable */
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H A Dmt7530.c1 // SPDX-License-Identifier: GPL-2.0-only
81 if (priv->bus) in mt7530_mutex_lock()
82 mutex_lock_nested(&priv->bus->mdio_lock, MDIO_MUTEX_NESTED); in mt7530_mutex_lock()
88 if (priv->bus) in mt7530_mutex_unlock()
89 mutex_unlock(&priv->bus->mdio_lock); in mt7530_mutex_unlock()
95 struct mii_bus *bus = priv->bus; in core_write()
101 ret = bus->write(bus, MT753X_CTRL_PHY_ADDR(priv->mdiodev->addr), in core_write()
107 ret = bus->write(bus, MT753X_CTRL_PHY_ADDR(priv->mdiodev->addr), in core_write()
113 ret = bus->write(bus, MT753X_CTRL_PHY_ADDR(priv->mdiodev->addr), in core_write()
119 ret = bus->write(bus, MT753X_CTRL_PHY_ADDR(priv->mdiodev->addr), in core_write()
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/linux/drivers/net/phy/mscc/
H A Dmscc_serdes.c1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
25 dev_err(&phydev->mdio.dev, "%s: write error\n", __func__); in pll5g_detune()
39 dev_err(&phydev->mdio.dev, "%s: write error\n", __func__); in pll5g_tune()
56 dev_err(&phydev->mdio.dev, "%s: write error\n", __func__); in vsc85xx_sd6g_pll_cfg_wr()
72 /* qrate = 1 for SGMII, 0 for QSGMII */ in vsc85xx_sd6g_common_cfg_wr()
73 /* if_mode = 1 for SGMII, 3 for QSGMII */ in vsc85xx_sd6g_common_cfg_wr()
85 dev_err(&phydev->mdio.dev, "%s: write error\n", __func__); in vsc85xx_sd6g_common_cfg_wr()
109 dev_err(&phydev->mdio.dev, "%s: write error\n", __func__); in vsc85xx_sd6g_des_cfg_wr()
134 dev_err(&phydev->mdio.dev, "%s: write error\n", __func__); in vsc85xx_sd6g_ib_cfg0_wr()
158 dev_err(&phydev->mdio.dev, "%s: write error\n", __func__); in vsc85xx_sd6g_ib_cfg1_wr()
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/linux/drivers/net/ethernet/intel/igb/
H A De1000_82575.c1 // SPDX-License-Identifier: GPL-2.0
2 /* Copyright(c) 2007 - 2018 Intel Corporation. */
61 * igb_write_vfta_i350 - Write value to VLAN filter table
71 struct igb_adapter *adapter = hw->back; in igb_write_vfta_i350()
74 for (i = 10; i--;) in igb_write_vfta_i350()
78 adapter->shadow_vfta[offset] = value; in igb_write_vfta_i350()
82 * igb_sgmii_uses_mdio_82575 - Determine if I2C pins are for external MDIO
93 switch (hw->mac.type) { in igb_sgmii_uses_mdio_82575()
114 * igb_check_for_link_media_swap - Check which M88E1112 interface linked
121 struct e1000_phy_info *phy = &hw->phy; in igb_check_for_link_media_swap()
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H A De1000_regs.h1 /* SPDX-License-Identifier: GPL-2.0 */
2 /* Copyright(c) 2007 - 2018 Intel Corporation. */
7 #define E1000_CTRL 0x00000 /* Device Control - RW */
8 #define E1000_STATUS 0x00008 /* Device Status - RO */
9 #define E1000_EECD 0x00010 /* EEPROM/Flash Control - RW */
10 #define E1000_EERD 0x00014 /* EEPROM Read - RW */
11 #define E1000_CTRL_EXT 0x00018 /* Extended Device Control - RW */
12 #define E1000_MDIC 0x00020 /* MDI Control - RW */
13 #define E1000_MDICNFG 0x00E04 /* MDI Config - RW */
14 #define E1000_SCTL 0x00024 /* SerDes Control - RW */
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/linux/drivers/net/dsa/sja1105/
H A Dsja1105_clocking.c1 // SPDX-License-Identifier: BSD-3-Clause
2 /* Copyright 2016-2018 NXP
3 * Copyright (c) 2018-2019, Vladimir Oltean <olteanv@gmail.com>
107 sja1105_packing(buf, &idiv->clksrc, 28, 24, size, op); in sja1105_cgu_idiv_packing()
108 sja1105_packing(buf, &idiv->autoblock, 11, 11, size, op); in sja1105_cgu_idiv_packing()
109 sja1105_packing(buf, &idiv->idiv, 5, 2, size, op); in sja1105_cgu_idiv_packing()
110 sja1105_packing(buf, &idiv->pd, 0, 0, size, op); in sja1105_cgu_idiv_packing()
116 const struct sja1105_regs *regs = priv->info->regs; in sja1105_cgu_idiv_config()
117 struct device *dev = priv->ds->dev; in sja1105_cgu_idiv_config()
121 if (regs->cgu_idiv[port] == SJA1105_RSV_ADDR) in sja1105_cgu_idiv_config()
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/linux/drivers/phy/mediatek/
H A Dphy-mtk-tphy.c1 // SPDX-License-Identifier: GPL-2.0
8 #include <dt-bindings/phy/phy.h>
15 #include <linux/nvmem-consumer.h>
22 #include "phy-mtk-io.h"
24 /* version V1 sub-banks offset base address */
35 /* version V2/V3 sub-banks offset base address */
220 /* CDR Charge Pump P-pat
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/linux/drivers/net/ethernet/amd/xgbe/
H A Dxgbe-phy-v2.c125 #include "xgbe-common.h"
149 /* Rate-change complete wait/retry count */
276 ((_x)->extd[XGBE_SFP_EXTD_SFF_8472] && \
277 !((_x)->extd[XGBE_SFP_EXTD_DIAG] & XGBE_SFP_EXTD_DIAG_ADDR_CHANGE))
284 #define XGBE_BEL_FUSE_VENDOR "BEL-FUSE "
285 #define XGBE_BEL_FUSE_PARTNO "1GBT-SFP06 "
306 /* Re-driver related definitions */
375 /* Re-driver support */
399 return pdata->i2c_if.i2c_xfer(pdata, i2c_op); in xgbe_phy_i2c_xfer()
405 struct xgbe_phy_data *phy_data = pdata->phy_data; in xgbe_phy_redrv_write()
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H A Dxgbe-mdio.c9 * Copyright (c) 2014-2016 Advanced Micro Devices, Inc.
59 * Copyright (c) 2014-2016 Advanced Micro Devices, Inc.
127 #include "xgbe-common.h"
132 if (!pdata->phy_if.phy_impl.module_eeprom) in xgbe_phy_module_eeprom()
133 return -ENXIO; in xgbe_phy_module_eeprom()
135 return pdata->phy_if.phy_impl.module_eeprom(pdata, eeprom, data); in xgbe_phy_module_eeprom()
141 if (!pdata->phy_if.phy_impl.module_info) in xgbe_phy_module_info()
142 return -ENXIO; in xgbe_phy_module_info()
144 return pdata->phy_if.phy_impl.module_info(pdata, modinfo); in xgbe_phy_module_info()
199 switch (pdata->an_mode) { in xgbe_an_enable_interrupts()
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/linux/drivers/phy/
H A Dphy-xgene.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * AppliedMicro X-Gene Multi-purpose PHY driver
10 * The APM X-Gene PHY consists of two PLL clock macro's (CMU) and lanes.
11 * The first PLL clock macro is used for internal reference clock. The second
12 * PLL clock macro is used to generate the clock for the PHY. This driver
13 * configures the first PLL CMU, the second PLL CMU, and programs the PHY to
14 * operate according to the mode of operation. The first PLL CMU is only
19 * -----------------
20 * | Internal | |------|
21 * | Ref PLL CMU |----| | ------------- ---------
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/linux/drivers/net/ethernet/broadcom/bnx2x/
H A Dbnx2x_link.c1 /* Copyright 2008-2013 Broadcom Corporation
8 * at http://www.gnu.org/licenses/gpl-2.0.html (the "GPL").
43 #define I2C_WA_PWR_ITER (I2C_WA_RETRY_CNT - 1)
205 (_phy)->def_md_devad, \
211 (_phy)->def_md_devad, \
239 * bnx2x_check_lfa - This function checks if link reinitialization is required,
251 struct bnx2x *bp = params->bp; in bnx2x_check_lfa()
254 REG_RD(bp, params->lfa_base + in bnx2x_check_lfa()
257 /* NOTE: must be first condition checked - in bnx2x_check_lfa()
262 REG_WR(bp, params->lfa_base + in bnx2x_check_lfa()
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/linux/drivers/net/ethernet/mediatek/
H A Dmtk_eth_soc.c1 // SPDX-License-Identifier: GPL-2.0-only
4 * Copyright (C) 2009-2016 John Crispin <blogic@openwrt.org>
5 * Copyright (C) 2009-2016 Felix Fietkau <nbd@openwrt.org>
6 * Copyright (C) 2013-2016 Michael Lee <igvtee@gmail.com>
24 #include <linux/pcs/pcs-mtk-lynxi.h>
34 static int mtk_msg_level = -1;
36 MODULE_PARM_DESC(msg_level, "Message level (-1=defaults,0=none,...,16=all)");
294 __raw_writel(val, eth->base + reg); in mtk_w32()
299 return __raw_readl(eth->base + reg); in mtk_r32()
325 dev_err(eth->dev, "mdio: MDIO timeout\n"); in mtk_mdio_busy_wait()
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/linux/drivers/net/ethernet/sfc/siena/
H A Dmcdi_pcol.h1 /* SPDX-License-Identifier: GPL-2.0-only */
4 * Copyright 2009-2018 Solarflare Communications Inc.
5 * Copyright 2019-2020 Xilinx Inc.
13 /* Power-on reset state */
35 /* The 'doorbell' addresses are hard-wired to alert the MC when written */
38 /* The rest of these are firmware-defined */
46 /* Values to be written to the per-port status dword in shared
71 * | | \--- Response
72 * | \------- Error
73 * \------------------------------ Resync (always set)
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/linux/drivers/net/ethernet/sfc/
H A Dmcdi_pcol.h1 /* SPDX-License-Identifier: GPL-2.0-only */
4 * Copyright 2009-2018 Solarflare Communications Inc.
5 * Copyright 2019-2020 Xilinx Inc.
13 /* Power-on reset state */
35 /* The 'doorbell' addresses are hard-wired to alert the MC when written */
38 /* The rest of these are firmware-defined */
46 /* Values to be written to the per-port status dword in shared
71 * | | \--- Response
72 * | \------- Error
73 * \------------------------------ Resync (always set)
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