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Searched +full:sfc +full:- +full:no +full:- +full:dma (Results 1 – 18 of 18) sorted by relevance

/linux/drivers/spi/
H A Dspi-rockchip-sfc.c1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright (c) 2017-2021, Rockchip Inc.
6 * Author: Shawn Lin <shawn.lin@rock-chips.com>
8 * Jon Lin <Jon.lin@rock-chips.com>
14 #include <linux/dma-mapping.h>
22 #include <linux/spi/spi-mem.h>
154 * devices (0-3), however I have only been able to test a single CS (CS 0)
159 /* The SFC can transfer max 16KB - 1 at one time
164 /* DMA is only enabled for large data transmission */
168 * 150MHz. No minimum or average value is suggested.
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H A DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
13 dynamic device discovery; some are even write-only or read-only.
17 chips, analog to digital (and d-to-a) converters, and more.
44 If your system has an master-capable SPI controller (which
56 by providing a high-level interface to send memory-like commands.
66 This enables support for SPI-NAND mode on the Airoha NAND
68 is implemented as a SPI-MEM controller.
107 to a single device like spi-nor (nvram), input device controller
166 supports spi-mem interface.
245 this code to manage the per-word or per-transfer accesses to the
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/linux/Documentation/devicetree/bindings/spi/
H A Drockchip-sfc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/spi/rockchip-sfc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Rockchip Serial Flash Controller (SFC)
10 - Heiko Stuebner <heiko@sntech.de>
11 - Chris Morgan <macromorgan@hotmail.com>
14 - $ref: spi-controller.yaml#
18 const: rockchip,sfc
20 The rockchip sfc controller is a standalone IP with version register,
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/linux/sound/firewire/
H A Dfcp.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Function Control Protocol (IEC 61883-1) helper functions
10 #include <linux/firewire-constants.h>
20 #include "amdtp-stream.h"
32 unsigned int sfc; in avc_general_set_sig_fmt() local
38 for (sfc = 0; sfc < CIP_SFC_COUNT; sfc++) { in avc_general_set_sig_fmt()
39 if (amdtp_rate_table[sfc] == rate) { in avc_general_set_sig_fmt()
45 return -EINVAL; in avc_general_set_sig_fmt()
49 return -ENOMEM; in avc_general_set_sig_fmt()
59 buf[5] = 0x07 & sfc; /* FDF-hi. AM824, frequency */ in avc_general_set_sig_fmt()
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H A Damdtp-stream.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Audio and Music Data Transmission Protocol (IEC 61883-6) streams
4 * with Common Isochronous Packet (IEC 61883-1) headers
12 #include <linux/firewire-constants.h>
17 #include "amdtp-stream.h"
27 #include "amdtp-stream-trace.h"
83 * amdtp_stream_init - initialize an AMDTP stream structure
87 * @flags: the details of the streaming protocol consist of cip_flags enumeration-constants.
99 return -EINVAL; in amdtp_stream_init()
101 s->protocol = kzalloc(protocol_size, GFP_KERNEL); in amdtp_stream_init()
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/linux/arch/arm/boot/dts/rockchip/
H A Drk3128.dtsi1 // SPDX-License-Identifier: GPL-2.0+
6 #include <dt-bindings/clock/rk3128-cru.h>
7 #include <dt-bindings/gpio/gpio.h>
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
9 #include <dt-bindings/interrupt-controller/irq.h>
10 #include <dt-bindings/pinctrl/rockchip.h>
11 #include <dt-bindings/power/rk3128-power.h>
15 interrupt-parent = <&gic>;
16 #address-cells = <1>;
17 #size-cells = <1>;
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H A Drv1108.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 #include <dt-bindings/gpio/gpio.h>
4 #include <dt-bindings/interrupt-controller/irq.h>
5 #include <dt-bindings/interrupt-controller/arm-gic.h>
6 #include <dt-bindings/clock/rv1108-cru.h>
7 #include <dt-bindings/pinctrl/rockchip.h>
8 #include <dt-bindings/thermal/thermal.h>
10 #address-cells = <1>;
11 #size-cells = <1>;
15 interrupt-parent = <&gic>;
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/linux/arch/arm64/boot/dts/nvidia/
H A Dtegra186.dtsi1 // SPDX-License-Identifier: GPL-2.0
2 #include <dt-bindings/clock/tegra186-clock.h>
3 #include <dt-bindings/gpio/tegra186-gpio.h>
4 #include <dt-bindings/interrupt-controller/arm-gic.h>
5 #include <dt-bindings/mailbox/tegra186-hsp.h>
6 #include <dt-bindings/memory/tegra186-mc.h>
7 #include <dt-bindings/pinctrl/pinctrl-tegra-io-pad.h>
8 #include <dt-bindings/power/tegra186-powergate.h>
9 #include <dt-bindings/reset/tegra186-reset.h>
10 #include <dt-bindings/thermal/tegra186-bpmp-thermal.h>
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H A Dtegra194.dtsi1 // SPDX-License-Identifier: GPL-2.0
2 #include <dt-bindings/clock/tegra194-clock.h>
3 #include <dt-bindings/gpio/tegra194-gpio.h>
4 #include <dt-bindings/interrupt-controller/arm-gic.h>
5 #include <dt-bindings/mailbox/tegra186-hsp.h>
6 #include <dt-bindings/pinctrl/pinctrl-tegra-io-pad.h>
7 #include <dt-bindings/pinctrl/pinctrl-tegra.h>
8 #include <dt-bindings/power/tegra194-powergate.h>
9 #include <dt-bindings/reset/tegra194-reset.h>
10 #include <dt-bindings/thermal/tegra194-bpmp-thermal.h>
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H A Dtegra234.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 #include <dt-bindings/clock/tegra234-clock.h>
4 #include <dt-bindings/gpio/tegra234-gpio.h>
5 #include <dt-bindings/interrupt-controller/arm-gic.h>
6 #include <dt-bindings/mailbox/tegra186-hsp.h>
7 #include <dt-bindings/memory/tegra234-mc.h>
8 #include <dt-bindings/pinctrl/pinctrl-tegra-io-pad.h>
9 #include <dt-bindings/power/tegra234-powergate.h>
10 #include <dt-bindings/reset/tegra234-reset.h>
11 #include <dt-bindings/thermal/tegra234-bpmp-thermal.h>
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/linux/arch/arm64/boot/dts/rockchip/
H A Drk3308.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
7 #include <dt-bindings/clock/rk3308-cru.h>
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 #include <dt-bindings/interrupt-controller/irq.h>
11 #include <dt-bindings/pinctrl/rockchip.h>
12 #include <dt-bindings/soc/rockchip,boot-mode.h>
13 #include <dt-bindings/thermal/thermal.h>
18 interrupt-parent = <&gic>;
19 #address-cells = <2>;
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H A Drk356x-base.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 #include <dt-bindings/clock/rk3568-cru.h>
7 #include <dt-bindings/interrupt-controller/arm-gic.h>
8 #include <dt-bindings/interrupt-controller/irq.h>
9 #include <dt-bindings/phy/phy.h>
10 #include <dt-bindings/pinctrl/rockchip.h>
11 #include <dt-bindings/power/rk3568-power.h>
12 #include <dt-bindings/soc/rockchip,boot-mode.h>
13 #include <dt-bindings/thermal/thermal.h>
16 interrupt-parent = <&gic>;
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/linux/drivers/mtd/spi-nor/controllers/
H A Dhisi-sfc.c1 // SPDX-License-Identifier: GPL-2.0-or-later
5 * Copyright (c) 2015-2016 HiSilicon Technologies Co., Ltd.
9 #include <linux/dma-mapping.h>
13 #include <linux/mtd/spi-nor.h>
64 #define HIFMC_DMA_MASK (HIFMC_DMA_MAX_LEN - 1)
107 return readl_poll_timeout(host->regbase + FMC_INT, reg, in hisi_spi_nor_wait_op_finish()
144 writel(reg, host->regbase + FMC_SPI_TIMING_CFG); in hisi_spi_nor_init()
149 struct hifmc_priv *priv = nor->priv; in hisi_spi_nor_prep()
150 struct hifmc_host *host = priv->host; in hisi_spi_nor_prep()
153 mutex_lock(&host->lock); in hisi_spi_nor_prep()
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/linux/drivers/net/ethernet/sfc/siena/
H A Defx_common.c1 // SPDX-License-Identifier: GPL-2.0-only
37 * On Falcon-based NICs, this will:
38 * - Check the on-board hardware monitor;
39 * - Poll the link state and reconfigure the hardware as necessary.
40 * On Siena-based NICs for power systems with EEH support, this will give EEH a
108 * queued onto this work queue. This is not a per-nic work queue, because
118 return -ENOMEM; in efx_siena_create_reset_workqueue()
126 queue_work(reset_workqueue, &efx->reset_work); in efx_siena_queue_reset_work()
131 cancel_work_sync(&efx->reset_work); in efx_siena_flush_reset_workqueue()
142 /* We assume that efx->type->reconfigure_mac will always try to sync RX
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/linux/drivers/gpu/drm/i915/gt/
H A Dintel_engine_cs.c1 // SPDX-License-Identifier: MIT
40 * on HSW) - so the final size, including the extra state required for the
260 * intel_engine_context_size() - return the size of the context for an engine
275 struct intel_uncore *uncore = gt->uncore; in intel_engine_context_size()
284 switch (GRAPHICS_VER(gt->i915)) { in intel_engine_context_size()
286 MISSING_CASE(GRAPHICS_VER(gt->i915)); in intel_engine_context_size()
296 if (IS_HASWELL(gt->i915)) in intel_engine_context_size()
320 GRAPHICS_VER(gt->i915), cxt_size * 64, in intel_engine_context_size()
321 cxt_size - 1); in intel_engine_context_size()
337 if (GRAPHICS_VER(gt->i915) < 8) in intel_engine_context_size()
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/linux/drivers/scsi/
H A Dadvansys.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * advansys.c - Linux Host Driver for AdvanSys SCSI Adapters
5 * Copyright (c) 1995-2000 Advanced System Products, Inc.
6 * Copyright (c) 2000-2001 ConnectCom Solutions, Inc.
34 #include <linux/dma-mapping.h>
39 #include <asm/dma.h>
109 #define ASC_CHIP_LATEST_VER_EISA ((ASC_CHIP_MIN_VER_EISA - 1) + 3)
125 * Narrow boards only support 12-byte commands, while wide boards
126 * extend to 16-byte commands.
380 #define ASC_IERR_NO_CARRIER 0x0001 /* No more carrier memory */
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/linux/
H A DMAINTAINERS5 ---------------------------------------------------
16 Orphan: No current maintainer [but maybe you could take the
21 W: *Web-page* with status/info
23 B: URI for where to file *bugs*. A web-page with detailed bug
28 patches to the given subsystem. This is either an in-tree file,
29 or a URI. See Documentation/maintainer/maintainer-entry-profile.rst
46 N: [^a-z]tegra all files whose path contains tegra
64 ----------------
83 3WARE SAS/SATA-RAID SCSI DRIVERS (3W-XXXX, 3W-9XXX, 3W-SAS)
85 L: linux-scsi@vger.kernel.org
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/linux/drivers/net/ethernet/sfc/
H A Dmcdi_pcol.h1 /* SPDX-License-Identifier: GPL-2.0-only */
4 * Copyright 2009-2018 Solarflare Communications Inc.
5 * Copyright 2019-2020 Xilinx Inc.
13 /* Power-on reset state */
35 /* The 'doorbell' addresses are hard-wired to alert the MC when written */
38 /* The rest of these are firmware-defined */
46 /* Values to be written to the per-port status dword in shared
71 * | | \--- Response
72 * | \------- Error
73 * \------------------------------ Resync (always set)
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