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/linux/fs/nls/
H A DKconfig44 native language character sets. These character sets are stored
56 native language character sets. These character sets are stored
68 native language character sets. These character sets are stored
81 native language character sets. These character sets are stored in
97 native language character sets. These character sets are stored in
112 native language character sets. These character sets are stored in
123 native language character sets. These character sets are stored in
134 native language character sets. These character sets are stored in
145 native language character sets. These character sets are stored in
156 native language character sets. These character sets are stored in
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/linux/arch/riscv/boot/dts/sophgo/
H A Dsg2042-cpus.dtsi269 i-cache-sets = <512>;
272 d-cache-sets = <512>;
296 i-cache-sets = <512>;
299 d-cache-sets = <512>;
323 i-cache-sets = <512>;
326 d-cache-sets = <512>;
350 i-cache-sets = <512>;
353 d-cache-sets = <512>;
377 i-cache-sets = <512>;
380 d-cache-sets = <512>;
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H A Dsg2044-cpus.dtsi20 i-cache-sets = <512>;
23 d-cache-sets = <512>;
56 i-cache-sets = <512>;
59 d-cache-sets = <512>;
92 i-cache-sets = <512>;
95 d-cache-sets = <512>;
128 i-cache-sets = <512>;
131 d-cache-sets = <512>;
164 i-cache-sets = <512>;
167 d-cache-sets = <512>;
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/linux/arch/arm64/boot/dts/amazon/
H A Dalpine-v3.dtsi30 d-cache-sets = <256>;
33 i-cache-sets = <256>;
44 d-cache-sets = <256>;
47 i-cache-sets = <256>;
58 d-cache-sets = <256>;
61 i-cache-sets = <256>;
72 d-cache-sets = <256>;
75 i-cache-sets = <256>;
86 d-cache-sets = <256>;
89 i-cache-sets = <256>;
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/linux/arch/arm64/boot/dts/amd/
H A Damd-seattle-cpus.dtsi51 i-cache-sets = <256>;
54 d-cache-sets = <256>;
67 i-cache-sets = <256>;
70 d-cache-sets = <256>;
82 i-cache-sets = <256>;
85 d-cache-sets = <256>;
97 i-cache-sets = <256>;
100 d-cache-sets = <256>;
112 i-cache-sets = <256>;
115 d-cache-sets = <256>;
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/linux/arch/arm64/boot/dts/ti/
H A Dk3-j784s4.dtsi65 i-cache-sets = <256>;
68 d-cache-sets = <256>;
79 i-cache-sets = <256>;
82 d-cache-sets = <256>;
93 i-cache-sets = <256>;
96 d-cache-sets = <256>;
107 i-cache-sets = <256>;
110 d-cache-sets = <256>;
121 i-cache-sets = <256>;
124 d-cache-sets = <256>;
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H A Dk3-am654.dtsi43 i-cache-sets = <256>;
46 d-cache-sets = <128>;
57 i-cache-sets = <256>;
60 d-cache-sets = <128>;
71 i-cache-sets = <256>;
74 d-cache-sets = <128>;
85 i-cache-sets = <256>;
88 d-cache-sets = <128>;
99 cache-sets = <512>;
109 cache-sets = <512>;
H A Dk3-am625.dtsi46 i-cache-sets = <256>;
49 d-cache-sets = <128>;
63 i-cache-sets = <256>;
66 d-cache-sets = <128>;
80 i-cache-sets = <256>;
83 d-cache-sets = <128>;
97 i-cache-sets = <256>;
100 d-cache-sets = <128>;
157 cache-sets = <512>;
H A Dk3-am62a7.dtsi46 i-cache-sets = <256>;
49 d-cache-sets = <128>;
63 i-cache-sets = <256>;
66 d-cache-sets = <128>;
80 i-cache-sets = <256>;
83 d-cache-sets = <128>;
97 i-cache-sets = <256>;
100 d-cache-sets = <128>;
157 cache-sets = <512>;
/linux/arch/mips/mm/
H A Dc-octeon.c183 c->icache.sets = 64 << ((config1 >> 22) & 7); in probe_octeon()
187 c->icache.sets * c->icache.ways * c->icache.linesz; in probe_octeon()
191 c->dcache.sets = 2; /* CN5XXX has two Dcache sets */ in probe_octeon()
193 c->dcache.sets = 1; /* CN3XXX has one Dcache set */ in probe_octeon()
196 c->dcache.sets * c->dcache.ways * c->dcache.linesz; in probe_octeon()
203 c->icache.sets = 8; in probe_octeon()
206 icache_size = c->icache.sets * c->icache.ways * c->icache.linesz; in probe_octeon()
210 c->dcache.sets = 8; in probe_octeon()
211 dcache_size = c->dcache.sets * c->dcache.ways * c->dcache.linesz; in probe_octeon()
217 c->icache.sets = 16; in probe_octeon()
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H A Dsc-mips.c153 unsigned long sets, line_sz, assoc; in mips_sc_probe_cm3() local
158 sets = cfg & CM_GCR_L2_CONFIG_SET_SIZE; in mips_sc_probe_cm3()
159 sets >>= __ffs(CM_GCR_L2_CONFIG_SET_SIZE); in mips_sc_probe_cm3()
160 if (sets) in mips_sc_probe_cm3()
161 c->scache.sets = 64 << sets; in mips_sc_probe_cm3()
171 c->scache.waysize = c->scache.sets * c->scache.linesz; in mips_sc_probe_cm3()
214 c->scache.sets = 64 << tmp; in mips_sc_probe()
236 * According to config2 it would be 5-ways and 512-sets, in mips_sc_probe()
241 c->scache.sets = 256; in mips_sc_probe()
247 c->scache.waysize = c->scache.sets * c->scache.linesz; in mips_sc_probe()
/linux/arch/arm64/boot/dts/freescale/
H A Dimx943.dtsi38 i-cache-sets = <128>;
41 d-cache-sets = <128>;
56 i-cache-sets = <128>;
59 d-cache-sets = <128>;
74 i-cache-sets = <128>;
77 d-cache-sets = <128>;
92 i-cache-sets = <128>;
95 d-cache-sets = <128>;
103 cache-sets = <256>;
113 cache-sets = <256>;
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/linux/arch/arm64/boot/dts/marvell/
H A Darmada-ap806-quad.dtsi24 i-cache-sets = <256>;
27 d-cache-sets = <256>;
39 i-cache-sets = <256>;
42 d-cache-sets = <256>;
54 i-cache-sets = <256>;
57 d-cache-sets = <256>;
69 i-cache-sets = <256>;
72 d-cache-sets = <256>;
80 cache-sets = <512>;
89 cache-sets = <512>;
H A Darmada-ap807-quad.dtsi24 i-cache-sets = <256>;
27 d-cache-sets = <256>;
39 i-cache-sets = <256>;
42 d-cache-sets = <256>;
54 i-cache-sets = <256>;
57 d-cache-sets = <256>;
69 i-cache-sets = <256>;
72 d-cache-sets = <256>;
80 cache-sets = <512>;
89 cache-sets = <512>;
/linux/arch/riscv/boot/dts/sifive/
H A Dfu540-c000.dtsi29 i-cache-sets = <128>;
46 d-cache-sets = <64>;
48 d-tlb-sets = <1>;
52 i-cache-sets = <64>;
54 i-tlb-sets = <1>;
73 d-cache-sets = <64>;
75 d-tlb-sets = <1>;
79 i-cache-sets = <64>;
81 i-tlb-sets = <1>;
100 d-cache-sets = <64>;
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H A Dfu740-c000.dtsi29 i-cache-sets = <128>;
47 d-cache-sets = <64>;
49 d-tlb-sets = <1>;
53 i-cache-sets = <128>;
55 i-tlb-sets = <1>;
74 d-cache-sets = <64>;
76 d-tlb-sets = <1>;
80 i-cache-sets = <128>;
82 i-tlb-sets = <1>;
101 d-cache-sets = <64>;
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/linux/drivers/gpu/drm/i915/display/
H A Dintel_tv_regs.h41 /* Sets the colorburst to PAL mode. Required for non-M PAL modes. */
104 /* Sets the DAC A sense value to high */
106 /* Sets the DAC B sense value to high */
108 /* Sets the DAC C sense value to high */
112 /* Sets the slew rate. Must be preserved in software */
340 /* Sets the subcarrier DDA to reset frequency every other field */
342 /* Sets the subcarrier DDA to reset frequency every fourth field */
344 /* Sets the subcarrier DDA to reset frequency every eighth field */
346 /* Sets the subcarrier DDA to never reset the frequency */
348 /* Sets the peak amplitude of the colorburst.*/
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/linux/arch/arm/boot/dts/broadcom/
H A Dbcm2836.dtsi43 /* Source for d/i-cache-line-size and d/i-cache-sets
58 d-cache-sets = <128>; // 32KiB(size)/64(line-size)=512ways/4-way set
61 i-cache-sets = <512>; // 32KiB(size)/32(line-size)=1024ways/2-way set
72 d-cache-sets = <128>; // 32KiB(size)/64(line-size)=512ways/4-way set
75 i-cache-sets = <512>; // 32KiB(size)/32(line-size)=1024ways/2-way set
86 d-cache-sets = <128>; // 32KiB(size)/64(line-size)=512ways/4-way set
89 i-cache-sets = <512>; // 32KiB(size)/32(line-size)=1024ways/2-way set
100 d-cache-sets = <128>; // 32KiB(size)/64(line-size)=512ways/4-way set
103 i-cache-sets = <512>; // 32KiB(size)/32(line-size)=1024ways/2-way set
107 /* Source for cache-line-size + cache-sets
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H A Dbcm2837.dtsi42 /* Source for d/i-cache-line-size and d/i-cache-sets
57 d-cache-sets = <128>; // 32KiB(size)/64(line-size)=512ways/4-way set
60 i-cache-sets = <256>; // 32KiB(size)/64(line-size)=512ways/2-way set
72 d-cache-sets = <128>; // 32KiB(size)/64(line-size)=512ways/4-way set
75 i-cache-sets = <256>; // 32KiB(size)/64(line-size)=512ways/2-way set
87 d-cache-sets = <128>; // 32KiB(size)/64(line-size)=512ways/4-way set
90 i-cache-sets = <256>; // 32KiB(size)/64(line-size)=512ways/2-way set
102 d-cache-sets = <128>; // 32KiB(size)/64(line-size)=512ways/4-way set
105 i-cache-sets = <256>; // 32KiB(size)/64(line-size)=512ways/2-way set
109 /* Source for cache-line-size + cache-sets
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/linux/arch/arm64/boot/dts/arm/
H A Djuno-r1.dts95 i-cache-sets = <256>;
98 d-cache-sets = <256>;
112 i-cache-sets = <256>;
115 d-cache-sets = <256>;
129 i-cache-sets = <256>;
132 d-cache-sets = <128>;
146 i-cache-sets = <256>;
149 d-cache-sets = <128>;
163 i-cache-sets = <256>;
166 d-cache-sets = <128>;
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H A Djuno.dts94 i-cache-sets = <256>;
97 d-cache-sets = <256>;
112 i-cache-sets = <256>;
115 d-cache-sets = <256>;
130 i-cache-sets = <256>;
133 d-cache-sets = <128>;
148 i-cache-sets = <256>;
151 d-cache-sets = <128>;
166 i-cache-sets = <256>;
169 d-cache-sets = <128>;
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H A Djuno-r2.dts95 i-cache-sets = <256>;
98 d-cache-sets = <256>;
113 i-cache-sets = <256>;
116 d-cache-sets = <256>;
131 i-cache-sets = <256>;
134 d-cache-sets = <128>;
149 i-cache-sets = <256>;
152 d-cache-sets = <128>;
167 i-cache-sets = <256>;
170 d-cache-sets = <128>;
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H A Dfvp-base-revc.dts78 i-cache-sets = <256>;
81 d-cache-sets = <256>;
92 i-cache-sets = <256>;
95 d-cache-sets = <256>;
106 i-cache-sets = <256>;
109 d-cache-sets = <256>;
120 i-cache-sets = <256>;
123 d-cache-sets = <256>;
134 i-cache-sets = <256>;
137 d-cache-sets = <256>;
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/linux/arch/s390/kernel/
H A Dperf_cpum_cf.c26 #define PERF_EVENT_CPUM_CF_DIAG 0xBC000UL /* Event: Counter sets */
35 /* Maximum number of counter sets */
92 unsigned int sets; /* # Counter set saved in memory */ member
103 * of counter sets. Extract this information at device driver initialization.
163 /* Disable counter sets on dedicated CPU */
325 /* Counter sets are stored as data stream in a page sized memory buffer and
335 * All counter sets are followed by a 64 byte trailer.
340 * - the time stamp the counter sets have been collected
344 * The counter sets are saved when the process is prepared to be executed on a
346 * The difference of both counter sets are calculated and stored in the event
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/linux/Documentation/firmware-guide/acpi/
H A DDSD-properties-rules.rst7 Properties, Property Sets and Property Subsets
45 Property sets may be hierarchical. That is, a property set may contain
49 General Validity Rule for Property Sets
52 Valid property sets must follow the guidance given by the Device Properties UUID
59 return property sets which do not follow that rule from _DSD in data packages
82 Property Sets and Device Tree Bindings
85 It often is useful to make _DSD return property sets that follow Device Tree
89 account in the first place and returning invalid property sets from _DSD must be
96 In any case, property sets following DT bindings literally should not be

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