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/linux/Documentation/devicetree/bindings/phy/
H A Dti,phy-am654-serdes.yaml4 $id: http://devicetree.org/schemas/phy/ti,phy-am654-serdes.yaml#
7 title: TI AM654 SERDES
10 This binding describes the TI AM654 SERDES. AM654 SERDES can be configured
19 - ti,phy-am654-serdes
26 - const: serdes
41 include/dt-bindings/phy/phy.h) and the 2nd cell should be the serdes lane function.
43 ti,serdes-clk:
44 description: Phandle to the SYSCON entry required for configuring SERDES clock selection.
52 description: Phandle to the SYSCON entry required for configuring SERDES lane function.
56 - description: Clock output names for SERDES 0
[all …]
H A Dmscc,vsc7514-serdes.yaml4 $id: http://devicetree.org/schemas/phy/mscc,vsc7514-serdes.yaml#
7 title: Microsemi Ocelot SerDes muxing
15 space for setting up the SerDes to switch port muxing.
17 A SerDes X can be "muxed" to work with switch port Y or Z for example.
18 One specific SerDes can also be used as a PCIe interface.
20 Hence, a SerDes represents an interface, be it an Ethernet or a PCIe one.
22 There are two kinds of SerDes: SERDES1G supports 10/100Mbps in
35 - mscc,vsc7514-serdes
40 The first number defines the input port to use for a given SerDes macro.
42 dt-bindings/phy/phy-ocelot-serdes.h
[all …]
H A Dmicrochip,lan966x-serdes.yaml4 $id: http://devicetree.org/schemas/phy/microchip,lan966x-serdes.yaml#
7 title: Microchip Lan966x Serdes controller
16 interfaces. The Serdes controller will allow to configure these interfaces
23 interface SerDes 2.
27 pattern: "^serdes@[0-9a-f]+$"
30 const: microchip,lan966x-serdes
42 dt-bindings/phy/phy-lan966x-serdes.
53 serdes: serdes@e2004010 {
54 compatible = "microchip,lan966x-serdes";
H A Drenesas,r8a779f0-ether-serdes.yaml4 $id: http://devicetree.org/schemas/phy/renesas,r8a779f0-ether-serdes.yaml#
7 title: Renesas Ethernet SERDES
14 const: renesas,r8a779f0-ether-serdes
29 description: Port number of SERDES.
48 compatible = "renesas,r8a779f0-ether-serdes";
/linux/arch/arm64/boot/dts/microchip/
H A Dsparx5_pcb135_board.dtsi367 phys = <&serdes 13>;
374 phys = <&serdes 13>;
381 phys = <&serdes 13>;
388 phys = <&serdes 13>;
395 phys = <&serdes 14>;
402 phys = <&serdes 14>;
409 phys = <&serdes 14>;
416 phys = <&serdes 14>;
423 phys = <&serdes 15>;
430 phys = <&serdes 15>;
[all …]
H A Dsparx5_pcb134_board.dtsi726 phys = <&serdes 13>;
736 phys = <&serdes 14>;
745 phys = <&serdes 15>;
754 phys = <&serdes 16>;
763 phys = <&serdes 17>;
772 phys = <&serdes 18>;
781 phys = <&serdes 19>;
790 phys = <&serdes 20>;
799 phys = <&serdes 21>;
808 phys = <&serdes 22>;
[all …]
/linux/arch/arm/boot/dts/microchip/
H A Dlan966x-pcb8290.dts11 #include "dt-bindings/phy/phy-lan966x-serdes.h"
121 phys = <&serdes 0 SERDES6G(1)>;
129 phys = <&serdes 1 SERDES6G(1)>;
137 phys = <&serdes 2 SERDES6G(1)>;
145 phys = <&serdes 3 SERDES6G(1)>;
153 phys = <&serdes 4 SERDES6G(2)>;
161 phys = <&serdes 5 SERDES6G(2)>;
169 phys = <&serdes 6 SERDES6G(2)>;
177 phys = <&serdes 7 SERDES6G(2)>;
181 &serdes {
H A Dlan966x-kontron-kswitch-d10-mmt.dtsi8 #include "dt-bindings/phy/phy-lan966x-serdes.h"
155 phys = <&serdes 0 CU(0)>;
162 phys = <&serdes 1 CU(1)>;
169 phys = <&serdes 4 SERDES6G(2)>;
176 phys = <&serdes 5 SERDES6G(2)>;
183 phys = <&serdes 6 SERDES6G(2)>;
190 phys = <&serdes 7 SERDES6G(2)>;
196 &serdes {
H A Dlan966x-pcb8309.dts7 #include "dt-bindings/phy/phy-lan966x-serdes.h"
181 phys = <&serdes 0 CU(0)>;
188 phys = <&serdes 1 CU(1)>;
196 phys = <&serdes 2 SERDES6G(0)>;
204 phys = <&serdes 3 SERDES6G(1)>;
208 &serdes {
/linux/Documentation/devicetree/bindings/net/
H A Dhisilicon-hns-dsaf.txt17 The second region is SerDes base register and size(optional, only used when
18 serdes-syscon in port node does not exist). It is recommended using
19 serdes-syscon rather than this address.
40 - serdes-syscon: is syscon handle for SerDes register.
81 serdes-syscon = <&serdes>;
87 serdes-syscon = <&serdes>;
H A Dmicrochip,sparx5-switch.yaml117 phandle of a Ethernet SerDes PHY. This defines which SerDes
228 phys = <&serdes 13>;
237 phys = <&serdes 29>;
246 phys = <&serdes 30>;
255 phys = <&serdes 31>;
264 phys = <&serdes 32>;
274 phys = <&serdes 0>;
H A Dmicrochip,lan966x-switch.yaml15 it supports up to 2RGMII/RMII, up to 3BASE-X/SERDES/2.5GBASE-X and up to
91 Phandle of a Ethernet SerDes PHY
95 This specifies the interface used by the Ethernet SerDes towards
157 phys = <&serdes 0 0>;
165 phys = <&serdes 2 4>;
/linux/drivers/phy/mscc/
H A Dphy-ocelot-serdes.c3 * SerDes PHY driver for Microsemi Ocelot
19 #include <dt-bindings/phy/phy-ocelot-serdes.h>
60 static int serdes_init_s6g(struct regmap *regmap, u8 serdes, int mode) in serdes_init_s6g() argument
89 ret = serdes_update_mcb_s6g(regmap, serdes); in serdes_init_s6g()
146 ret = serdes_commit_mcb_s6g(regmap, serdes); in serdes_init_s6g()
222 ret = serdes_commit_mcb_s6g(regmap, serdes); in serdes_init_s6g()
230 ret = serdes_commit_mcb_s6g(regmap, serdes); in serdes_init_s6g()
244 ret = serdes_commit_mcb_s6g(regmap, serdes); in serdes_init_s6g()
292 static int serdes_init_s1g(struct regmap *regmap, u8 serdes) in serdes_init_s1g() argument
296 ret = serdes_update_mcb_s1g(regmap, serdes); in serdes_init_s1g()
[all …]
/linux/drivers/net/dsa/mv88e6xxx/
H A Dpcs-639x.c3 * Marvell 88E6352 family SERDES PCS support
18 #include "serdes.h"
79 "mv88e6xxx-%s-serdes-%d", dev_name(dev), port); in mv88e639x_pcs_alloc()
219 * After chip reset, SERDES reconfiguration or SERDES core in mv88e6390_erratum_3_14()
220 * Software Reset, the SERDES lanes may not be properly aligned in mv88e6390_erratum_3_14()
271 "can't read Serdes PHY %s: %pe\n", in mv88e639x_sgmii_pcs_get_state()
280 "can't read Serdes PHY %s: %pe\n", in mv88e639x_sgmii_pcs_get_state()
289 "can't read Serdes PHY %s: %pe\n", in mv88e639x_sgmii_pcs_get_state()
366 "can't access Serdes PHY %s: %pe\n", in mv88e639x_sgmii_pcs_link_up()
412 "can't read Serdes PHY %s: %pe\n", in mv88e639x_xg_pcs_get_state()
[all …]
/linux/drivers/net/ethernet/sfc/siena/
H A Denum.h17 * @LOOPBACK_XAUI: loopback within BPX before XAUI serdes
21 * @LOOPBACK_XFI: loopback within BPX before XFI serdes
22 * @LOOPBACK_XAUI_FAR: loopback within BPX after XAUI serdes
25 * @LOOPBACK_XFI_FAR: loopback after XFI serdes
32 * @LOOPBACK_XAUI_WS: wireside loopback within BPX within XAUI serdes
33 * @LOOPBACK_XAUI_WS_FAR: wireside loopback within BPX including XAUI serdes
34 * @LOOPBACK_XAUI_WS_NEAR: wireside loopback within BPX excluding XAUI serdes
36 * @LOOPBACK_XFI_WS: wireside loopback excluding XFI serdes
37 * @LOOPBACK_XFI_WS_FAR: wireside loopback including XFI serdes
/linux/drivers/net/ethernet/sfc/falcon/
H A Denum.h17 * @LOOPBACK_XAUI: loopback within BPX before XAUI serdes
21 * @LOOPBACK_XFI: loopback within BPX before XFI serdes
22 * @LOOPBACK_XAUI_FAR: loopback within BPX after XAUI serdes
25 * @LOOPBACK_XFI_FAR: loopback after XFI serdes
32 * @LOOPBACK_XAUI_WS: wireside loopback within BPX within XAUI serdes
33 * @LOOPBACK_XAUI_WS_FAR: wireside loopback within BPX including XAUI serdes
34 * @LOOPBACK_XAUI_WS_NEAR: wireside loopback within BPX excluding XAUI serdes
36 * @LOOPBACK_XFI_WS: wireside loopback excluding XFI serdes
37 * @LOOPBACK_XFI_WS_FAR: wireside loopback including XFI serdes
/linux/drivers/net/ethernet/sfc/
H A Denum.h17 * @LOOPBACK_XAUI: loopback within BPX before XAUI serdes
21 * @LOOPBACK_XFI: loopback within BPX before XFI serdes
22 * @LOOPBACK_XAUI_FAR: loopback within BPX after XAUI serdes
25 * @LOOPBACK_XFI_FAR: loopback after XFI serdes
32 * @LOOPBACK_XAUI_WS: wireside loopback within BPX within XAUI serdes
33 * @LOOPBACK_XAUI_WS_FAR: wireside loopback within BPX including XAUI serdes
34 * @LOOPBACK_XAUI_WS_NEAR: wireside loopback within BPX excluding XAUI serdes
36 * @LOOPBACK_XFI_WS: wireside loopback excluding XFI serdes
37 * @LOOPBACK_XFI_WS_FAR: wireside loopback including XFI serdes
/linux/drivers/phy/freescale/
H A DKconfig59 tristate "Freescale Layerscape Lynx 10G SerDes PHY support"
66 Enable this to add support for the Lynx 10G SerDes PHY as found on
70 tristate "Freescale Layerscape Lynx 28G SerDes PHY support"
76 Enable this to add support for the Lynx SerDes 28G PHY as
78 Used to change the protocol running on SerDes lanes at runtime.
/linux/drivers/phy/microchip/
H A DKconfig7 tristate "Microchip Sparx5 SerDes PHY driver"
13 Enable this for support of the 10G/25G SerDes on Microchip Sparx5.
16 tristate "SerDes PHY driver for Microchip LAN966X"
22 Enable this for supporting SerDes muxing with Microchip LAN966X
/linux/drivers/phy/marvell/
H A DKconfig36 shared serdes PHYs on Marvell Armada 3700. Its serdes lanes can be
55 shared serdes PHYs on Marvell Armada 38x. Its serdes lanes can be
66 shared serdes PHYs on Marvell Armada 7k/8k (in the CP110). Its serdes
/linux/Documentation/devicetree/bindings/soc/ti/
H A Dti,am654-serdes-ctrl.yaml4 $id: http://devicetree.org/schemas/soc/ti/ti,am654-serdes-ctrl.yaml#
7 title: Texas Instruments AM654 Serdes Control Syscon
15 - const: ti,am654-serdes-ctrl
35 compatible = "ti,am654-serdes-ctrl", "syscon", "simple-mfd";
/linux/arch/mips/boot/dts/mscc/
H A Docelot_pcb120.dts8 #include <dt-bindings/phy/phy-ocelot-serdes.h>
99 phys = <&serdes 4 SERDES1G(2)>;
106 phys = <&serdes 5 SERDES1G(5)>;
113 phys = <&serdes 6 SERDES1G(3)>;
120 phys = <&serdes 9 SERDES1G(4)>;
/linux/drivers/phy/qualcomm/
H A Dphy-qcom-qmp-ufs.c1143 u16 serdes; member
1152 /* Init sequence for PHY blocks - serdes, tx, rx, pcs */
1153 const struct qmp_phy_init_tbl *serdes; member
1173 /* Main init sequence for PHY blocks - serdes, tx, rx, pcs */
1196 void __iomem *serdes; member
1325 .serdes = 0,
1334 .serdes = 0,
1343 .serdes = 0,
1358 .serdes = milos_ufsphy_serdes,
1368 .serdes = sm8550_ufsphy_hs_b_serdes,
[all …]
/linux/include/linux/bcma/
H A Dbcma_driver_pci.h78 #define BCMA_CORE_PCI_MDIODATA_DEV_ADDR 0x0 /* dev address for serdes */
79 #define BCMA_CORE_PCI_MDIODATA_BLK_ADDR 0x1F /* blk address for serdes */
80 #define BCMA_CORE_PCI_MDIODATA_DEV_PLL 0x1d /* SERDES PLL Dev */
81 #define BCMA_CORE_PCI_MDIODATA_DEV_TX 0x1e /* SERDES TX Dev */
82 #define BCMA_CORE_PCI_MDIODATA_DEV_RX 0x1f /* SERDES RX Dev */
126 #define BCMA_CORE_PCI_PLP_SERDESCTRLOVRDREG 0x230 /* SERDES Control Override */
157 /* SERDES RX registers */
165 /* SERDES PLL registers */
187 /* MDIO devices (SERDES modules) */
/linux/arch/arm64/boot/dts/ti/
H A Dk3-j784s4-evm-quad-port-eth-exp1.dtso22 #include "k3-serdes.h"
43 phy-names = "mac", "serdes";
52 phy-names = "mac", "serdes";
61 phy-names = "mac", "serdes";
70 phy-names = "mac", "serdes";

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