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/linux/Documentation/devicetree/bindings/mtd/
H A Dnand-chip.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/mtd/nand-chip.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Miquel Raynal <miquel.raynal@bootlin.com>
13 - $ref: mtd.yaml#
18 SPI-NAND devices are concerned by this description.
23 Contains the chip-select IDs.
25 nand-ecc-engine:
31 2/ The ECC engine is part of the NAND part (on-die), in this
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/linux/Documentation/devicetree/bindings/mailbox/
H A Dti,secure-proxy.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/mailbox/ti,secure-proxy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Texas Instruments' Secure Proxy
10 - Nishanth Menon <nm@ti.com>
13 The Texas Instruments' secure proxy is a mailbox controller that has
15 Message manager is broken up into different address regions that are
16 called "threads" or "proxies" - each instance is unidirectional and is
22 pattern: "^mailbox@[0-9a-f]+$"
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/linux/Documentation/networking/devlink/
H A Diosm.rst1 .. SPDX-License-Identifier: GPL-2.0
13 The ``iosm`` driver implements the following driver-specific parameters.
15 .. list-table:: Driver-specific parameters implemented
18 * - Name
19 - Type
20 - Mode
21 - Description
22 * - ``erase_full_flash``
23 - u8
24 - runtime
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/linux/drivers/nvdimm/
H A DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
3 tristate "NVDIMM (Non-Volatile Memory Device) Support"
9 Generic support for non-volatile memory devices including
10 ACPI-6-NFIT defined resources. On platforms that define an
28 non-standard OEM-specific E820 memory type (type-12, see
31 Documentation/admin-guide/kernel-parameters.rst). This driver converts
33 capable of DAX (direct-access) file system mappings. See
34 Documentation/driver-api/nvdimm/nvdimm.rst for more details.
69 management sub-system. By default persistent memory does
85 sub-divide a namespace into character devices that can only be
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/linux/include/linux/firmware/qcom/
H A Dqcom_qseecom.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 * Driver for Qualcomm Secure Execution Environment (SEE) interface (QSEECOM).
13 #include <linux/dma-mapping.h>
19 * struct qseecom_client - QSEECOM client device.
29 * qcom_qseecom_app_send() - Send to and receive data from a given QSEE app.
37 * back its response. The caller must provide two DMA memory regions, one for
39 * respective (app-specific) request data. The QSEE app reads this and returns
51 return qcom_scm_qseecom_app_send(client->app_id, req, req_size, rsp, rsp_size); in qcom_qseecom_app_send()
/linux/drivers/nvmem/
H A Dstm32-romem.c1 // SPDX-License-Identifier: GPL-2.0
3 * STM32 Factory-programmed memory read access driver
5 * Copyright (C) 2017, STMicroelectronics - All Rights Reserved
9 #include <linux/arm-smccc.h>
12 #include <linux/nvmem-provider.h>
18 #include "stm32-bsec-optee-ta.h"
20 /* BSEC secure service access from non-secure */
51 *buf8++ = readb_relaxed(priv->base + i); in stm32_romem_read()
63 return -EIO; in stm32_bsec_smc()
70 return -ENXIO; in stm32_bsec_smc()
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/linux/drivers/soc/qcom/
H A Docmem.c1 // SPDX-License-Identifier: GPL-2.0-only
64 struct ocmem_region *regions; member
104 writel(data, ocmem->mmio + reg); in ocmem_write()
109 return readl(ocmem->mmio + reg); in ocmem_read()
118 for (i = 0; i < ocmem->config->num_regions; i++) { in update_ocmem()
119 struct ocmem_region *region = &ocmem->regions[i]; in update_ocmem()
121 if (region->mode == THIN_MODE) in update_ocmem()
125 dev_dbg(ocmem->dev, "ocmem_region_mode_control %x\n", in update_ocmem()
130 for (i = 0; i < ocmem->config->num_regions; i++) { in update_ocmem()
131 struct ocmem_region *region = &ocmem->regions[i]; in update_ocmem()
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/linux/Documentation/admin-guide/
H A Dthunderbolt.rst1 .. SPDX-License-Identifier: GPL-2.0
25 -----------------------------------
27 should be a userspace tool that handles all the low-level details, keeps
31 found in ``Documentation/ABI/testing/sysfs-bus-thunderbolt``.
35 ``/etc/udev/rules.d/99-local.rules``::
66 secure
68 addition to UUID the device (if it supports secure connect) is sent
92 If the security level reads as ``user`` or ``secure`` the connected
101 Authorizing devices when security level is ``user`` or ``secure``
102 -----------------------------------------------------------------
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H A Dperf-security.rst7 --------
50 -------------------------------
66 independently enabled and disabled on per-thread basis for processes and
74 observability operations in the kernel and provides a secure approach to
79 processes but CAP_SYS_ADMIN usage for secure monitoring and observability
84 is recommended as the preferred secure approach to resolve double access
103 ---------------------------------
105 Mechanisms of capabilities, privileged capability-dumb files [6]_,
118 # ls -alhF
119 -rwxr-xr-x 2 root root 11M Oct 19 15:12 perf
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/linux/arch/arm64/boot/dts/sprd/
H A Dums9620.dtsi1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 interrupt-parent = <&gic>;
12 #address-cells = <2>;
13 #size-cells = <2>;
16 #address-cells = <2>;
17 #size-cells = <0>;
19 cpu-map {
50 compatible = "arm,cortex-a55";
52 enable-method = "psci";
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/linux/drivers/irqchip/
H A Dirq-gic-v3.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2013-2017 ARM Limited, All Rights Reserved.
26 #include <linux/irqchip/arm-gic-common.h>
27 #include <linux/irqchip/arm-gic-v3.h>
28 #include <linux/irqchip/arm-gic-v3-prio.h>
29 #include <linux/irqchip/irq-partition-percpu.h>
32 #include <linux/arm-smccc.h>
39 #include "irq-gic-common.h"
91 * are potentially stolen by the secure side. Some code, especially code dealing
98 * SCR_EL3.FIQ, and the behaviour of non-secure priority registers of the
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/linux/Documentation/arch/s390/
H A Dmm.rst1 .. SPDX-License-Identifier: GPL-2.0
12 - Some aspects of the virtual memory layout setup are not
15 - Unused gaps in the virtual memory layout could be present
16 or not - depending on how partucular system is configured.
19 - The virtual memory regions are tracked or untracked by KASAN
28 +- 0 --------------+- 0 --------------+
29 | | S390_lowcore | Low-address memory
30 | +- 8 KB -----------+
35 +- AMODE31_START --+- AMODE31_START --+ .amode31 rand. phys/virt start
37 +- AMODE31_END ----+- AMODE31_END ----+ .amode31 rand. phys/virt end (<2GB)
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/linux/drivers/firmware/efi/libstub/
H A Dfdt.c1 // SPDX-License-Identifier: GPL-2.0
24 /* Set the #address-cells and #size-cells values for an empty tree */ in fdt_update_cell_size()
26 fdt_setprop_u32(fdt, offset, "#address-cells", EFI_DT_ADDR_CELLS_DEFAULT); in fdt_update_cell_size()
27 fdt_setprop_u32(fdt, offset, "#size-cells", EFI_DT_SIZE_CELLS_DEFAULT); in fdt_update_cell_size()
61 * non-critical: in update_fdt()
72 * kernel will use the UEFI memory map to find reserved regions. in update_fdt()
75 while (num_rsv-- > 0) in update_fdt()
99 status = fdt_setprop_var(fdt, node, "linux,uefi-system-table", fdt_val64); in update_fdt()
105 status = fdt_setprop_var(fdt, node, "linux,uefi-mmap-start", fdt_val64); in update_fdt()
111 status = fdt_setprop_var(fdt, node, "linux,uefi-mmap-size", fdt_val32); in update_fdt()
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/linux/drivers/xen/
H A DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
32 2) control domain: xl mem-max <target-domain> <maxmem>
35 3) control domain: xl mem-set <target-domain> <memory>
51 …SUBSYSTEM=="memory", ACTION=="add", RUN+="/bin/sh -c '[ -f /sys$devpath/state ] && echo online > /…
76 secure, but slightly less efficient. This can be controlled with
145 bool "Add support for dma-buf grant access device driver extension"
150 dma-buf implementation. With this extension grant references to
151 the pages of an imported dma-buf can be exported for other domain
153 converted into a local dma-buf for local export.
156 tristate "User-space grant reference allocator driver"
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/linux/drivers/mailbox/
H A Dti-msgmgr.c1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (C) 2015-2022 Texas Instruments Incorporated - https://www.ti.com/
22 #include <linux/soc/ti/ti-msgmgr.h>
41 * struct ti_msgmgr_valid_queue_desc - SoC valid queues meant for this processor
53 * struct ti_msgmgr_desc - Description of message manager integration
68 * @is_sproxy: Is this an Secure Proxy instance?
92 * struct ti_queue_inst - Description of a queue instance
122 * struct ti_msgmgr_inst - Description of a Message Manager Instance
126 * @queue_state_debug_region: Queue status register regions
127 * @queue_ctrl_region: Queue Control register regions
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/linux/Documentation/arch/x86/
H A Dtdx.rst1 .. SPDX-License-Identifier: GPL-2.0
16 TDX introduces a new CPU mode called Secure Arbitration Mode (SEAM) and
18 CPU-attested software module called 'the TDX module' runs inside the new
22 TDX also leverages Intel Multi-Key Total Memory Encryption (MKTME) to
23 provide crypto-protection to the VMs. TDX reserves part of MKTME KeyIDs
32 TDX boot-time detection
33 -----------------------
41 ---------------------------------------
59 Besides initializing the TDX module, a per-cpu initialization SEAMCALL
103 ------------------------------------------
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/linux/Documentation/userspace-api/
H A Dvduse.rst2 VDUSE - "vDPA Device in Userspace"
9 possible to implement software-emulated vDPA devices in userspace. And
10 to make the device emulation more secure, the emulated vDPA device's
21 ----------------------------
49 .. code-block:: c
59 return -ENOMEM;
92 return -1;
96 ---------------
104 add per-virtqueue configuration such as the max size of virtqueue to the device.
111 .. code-block:: c
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/linux/Documentation/ABI/testing/
H A Dsysfs-bus-coresight-devices-etm4x76 Description: (Read) Indicates the number of single-shot comparator controls that
135 Description: (RW) Controls which regions in the memory map are enabled to
148 Description: (RW) In Secure state, each bit controls whether instruction
155 Description: (RW) In non-secure state, each bit controls whether instruction
289 Description: (RW) Set the Exception Level matching bits for secure and
290 non-secure exception levels.
486 Description: (Read) Returns the number of P0 right-hand keys that the trace unit
493 Description: (Read) Returns the number of P1 right-hand keys that the trace unit
500 Description: (Read) Returns the number of special P1 right-hand keys that the
508 Description: (Read) Returns the number of conditional P1 right-hand keys that
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H A Dsysfs-bus-cxl4 Contact: linux-cxl@vger.kernel.org
14 Contact: linux-cxl@vger.kernel.org
17 Memory Device Output Payload in the CXL-2.0
24 Contact: linux-cxl@vger.kernel.org
28 Payload in the CXL-2.0 specification.
34 Contact: linux-cxl@vger.kernel.org
40 class-ids can be compared against a similar "qos_class"
42 that the endpoints map their local memory-class to a
45 side-effects that may result. First class-id is displayed.
51 Contact: linux-cxl@vger.kernel.org
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/linux/arch/arm/boot/dts/qcom/
H A Dqcom-sdx55-telit-fn980-tlb.dts1 // SPDX-License-Identifier: BSD-3-Clause
6 /dts-v1/;
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/regulator/qcom,rpmh-regulator.h>
10 #include "qcom-sdx55.dtsi"
15 compatible = "qcom,sdx55-telit-fn980-tlb", "qcom,sdx55";
16 qcom,board-id = <0xb010008 0x0>;
23 stdout-path = "serial0:921600n8";
26 reserved-memory {
27 #address-cells = <1>;
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H A Dqcom-sdx55-t55.dts1 // SPDX-License-Identifier: BSD-3-Clause
6 /dts-v1/;
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/regulator/qcom,rpmh-regulator.h>
10 #include "qcom-sdx55.dtsi"
15 compatible = "qcom,sdx55-t55", "qcom,sdx55";
16 qcom,board-id = <0xb010008 0x4>;
23 stdout-path = "serial0:115200n8";
26 reserved-memory {
27 #address-cells = <1>;
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H A Dqcom-sdx65-mtp.dts1 // SPDX-License-Identifier: BSD-3-Clause
5 /dts-v1/;
11 #include "qcom-sdx65.dtsi"
12 #include <dt-bindings/regulator/qcom,rpmh-regulator.h>
19 compatible = "qcom,sdx65-mtp", "qcom,sdx65";
20 qcom,board-id = <0x2010008 0x302>;
27 stdout-path = "serial0:115200n8";
30 reserved-memory {
31 #address-cells = <1>;
32 #size-cells = <1>;
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/linux/Documentation/devicetree/bindings/display/msm/
H A Dgpu.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - Rob Clark <robdclark@gmail.com>
14 # as a work-around:
20 - qcom,adreno
21 - amd,imageon
23 - compatible
28 - description: |
30 figure out the chip-id.
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/linux/arch/x86/kernel/
H A Dsetup.c1 // SPDX-License-Identifier: GPL-2.0-only
5 * This file contains the setup_arch() code, which handles the architecture-dependent
12 #include <linux/dma-map-ops.h>
24 #include <linux/usb/xhci-dbgp.h>
52 #include <asm/pci-direct.h>
64 * The direct mapping only covers E820_TYPE_RAM regions, s
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/linux/include/linux/mtd/
H A Drawnand.h1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * Copyright © 2000-2010 David Woodhouse <dwmw2@infradead.org>
75 #define NAND_CMD_NONE -1
84 #define NAND_DATA_IFACE_CHECK_ONLY -1
98 * ecc.correct() returns -EBADMSG.
124 * Chip requires ready check on read (for auto-incremented sequential read).
142 #define NAND_HAS_SUBPAGE_READ(chip) ((chip->options & NAND_SUBPAGE_READ))
174 * In case your controller is implementing ->legacy.cmd_ctrl() and is relying
175 * on the default ->cmdfunc() implementation, you may want to let the core
225 * struct nand_parameters - NAND generic parameters from the parameter page
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