| /linux/Documentation/devicetree/bindings/bus/ |
| H A D | st,stm32mp25-rifsc.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/bus/st,stm32mp25-rifsc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Gatien Chevallier <gatien.chevallier@foss.st.com>
19 - RISC registers associated with RISUP logic (resource isolation device unit
20 for peripherals), assign all non-RIF aware peripherals to zero, one or
21 any security domains (secure, privilege, compartment).
22 - RIMC registers: associated with RIMU logic (resource isolation master
23 unit), assign all non RIF-aware bus master to one security domain by
[all …]
|
| /linux/Documentation/devicetree/bindings/arm/tegra/ |
| H A D | nvidia,tegra194-cbb.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/arm/tegra/nvidia,tegra194-cbb.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Sumit Gupta <sumitg@nvidia.com>
15 multiple hierarchical sub-NOCs (Network-on-Chip) and connects various
20 "AON-NOC, SCE-NOC, RCE-NOC, BPMP-NOC, CV-NOC" and "CBB Central NOC"
23 By default, the access issuing initiator is informed about the error
28 - For CCPLEX (CPU Complex) initiator, the driver sets ERD bit. So, the
31 - For other initiators, the ERD is disabled. So, the access issuing
[all …]
|
| /linux/Documentation/devicetree/bindings/nvmem/ |
| H A D | st,stm32-romem.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/nvmem/st,stm32-romem.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: STMicroelectronics STM32 Factory-programmed data
10 This represents STM32 Factory-programmed read only non-volatile area: locked
11 flash, OTP, read-only HW regs... This contains various information such as:
16 - Fabrice Gasnier <fabrice.gasnier@foss.st.com>
19 - $ref: nvmem.yaml#
20 - $ref: nvmem-deprecated-cells.yaml#
[all …]
|
| H A D | qcom,sec-qfprom.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/nvmem/qcom,sec-qfprom.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm Technologies Inc, Secure QFPROM Efuse
10 - Komal Bajaj <quic_kbajaj@quicinc.com>
14 protected from non-secure access. In such situations, the OS have to use
15 secure calls to read the region.
18 - $ref: nvmem.yaml#
19 - $ref: nvmem-deprecated-cells.yaml#
[all …]
|
| /linux/drivers/nvmem/ |
| H A D | sec-qfprom.c | 1 // SPDX-License-Identifier: GPL-2.0-only
8 #include <linux/nvmem-provider.h>
13 * struct sec_qfprom - structure holding secure qfprom attributes
15 * @base: starting physical address for secure qfprom corrected address space.
23 static int sec_qfprom_reg_read(void *context, unsigned int reg, void *_val, size_t bytes) in sec_qfprom_reg_read() argument
31 for (i = 0; i < bytes; i++, reg++) { in sec_qfprom_reg_read()
32 if (i == 0 || reg % 4 == 0) { in sec_qfprom_reg_read()
33 if (qcom_scm_io_readl(priv->base + (reg & ~3), &read_val)) { in sec_qfprom_reg_read()
34 dev_err(priv->dev, "Couldn't access fuse register\n"); in sec_qfprom_reg_read()
35 return -EINVAL; in sec_qfprom_reg_read()
[all …]
|
| /linux/drivers/mfd/ |
| H A D | intel-m10-bmc-core.c | 1 // SPDX-License-Identifier: GPL-2.0
3 * Intel MAX 10 Board Management Controller chip - common code
5 * Copyright (C) 2018-2020 Intel Corporation. All rights reserved.
12 #include <linux/mfd/intel-m10-bmc.h>
18 if (!m10bmc->info->handshake_sys_reg_nranges) in m10bmc_fw_state_set()
21 down_write(&m10bmc->bmcfw_lock); in m10bmc_fw_state_set()
22 m10bmc->bmcfw_state = new_state; in m10bmc_fw_state_set()
23 up_write(&m10bmc->bmcfw_lock); in m10bmc_fw_state_set()
29 * handshake registers during a secure update.
33 if (!m10bmc->info->handshake_sys_reg_nranges) in m10bmc_reg_always_available()
[all …]
|
| /linux/Documentation/devicetree/bindings/interrupt-controller/ |
| H A D | marvell,icu.txt | 2 --------------------------------
5 responsible for collecting all wired-interrupt sources in the CP and
8 These messages will access a different GIC memory area depending on
13 - compatible: Should be "marvell,cp110-icu"
15 - reg: Should contain ICU registers location and length.
22 - compatible: Should be one of:
23 * "marvell,cp110-icu-nsr"
24 * "marvell,cp110-icu-sr"
25 * "marvell,cp110-icu-sei"
26 * "marvell,cp110-icu-rei"
[all …]
|
| /linux/drivers/perf/ |
| H A D | arm_pmu_platform.c | 1 // SPDX-License-Identifier: GPL-2.0
30 int ret = -ENODEV; in probe_current_pmu()
34 for (; info->init != NULL; info++) { in probe_current_pmu()
35 if ((cpuid & info->mask) != info->cpuid) in probe_current_pmu()
37 ret = info->init(pmu); in probe_current_pmu()
48 struct pmu_hw_events __percpu *hw_events = pmu->hw_events; in pmu_parse_percpu_irq()
50 ret = irq_get_percpu_devid_partition(irq, &pmu->supported_cpus); in pmu_parse_percpu_irq()
54 for_each_cpu(cpu, &pmu->supported_cpus) in pmu_parse_percpu_irq()
55 per_cpu(hw_events->irq, cpu) = irq; in pmu_parse_percpu_irq()
62 return of_property_present(node, "interrupt-affinity"); in pmu_has_irq_affinity()
[all …]
|
| /linux/Documentation/devicetree/bindings/timer/ |
| H A D | ti,timer-dm.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/timer/ti,timer-dm.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: TI dual-mode timer
10 - Tony Lindgren <tony@atomide.com>
13 The TI dual-mode timer is a general purpose timer with PWM capabilities.
18 - items:
19 - enum:
20 - ti,am335x-timer
[all …]
|
| /linux/drivers/rtc/ |
| H A D | rtc-mxc_v2.c | 1 // SPDX-License-Identifier: GPL-2.0
4 * Copyright (c) 2004-2011 Freescale Semiconductor, Inc.
21 #define SRTC_LPCR_NSA BIT(11) /* lp non secure access */
26 #define SRTC_LPSR_NVES BIT(14) /* lp non-valid state exit status */
29 #define SRTC_LPSCMR 0x00 /* LP Secure Counter MSB Reg */
30 #define SRTC_LPSCLR 0x04 /* LP Secure Counter LSB Reg */
31 #define SRTC_LPSAR 0x08 /* LP Secure Alarm Reg */
32 #define SRTC_LPCR 0x10 /* LP Control Reg */
33 #define SRTC_LPSR 0x14 /* LP Status Reg */
34 #define SRTC_LPPDR 0x18 /* LP Power Supply Glitch Detector Reg */
[all …]
|
| /linux/drivers/iommu/ |
| H A D | ipmmu-vmsa.c | 1 // SPDX-License-Identifier: GPL-2.0
3 * IOMMU API for Renesas VMSA-compatible IPMMU
6 * Copyright (C) 2014-2020 Renesas Electronics Corporation
11 #include <linux/dma-mapping.h>
18 #include <linux/io-pgtable.h>
29 #include <asm/dma-iommu.h>
32 #define arm_iommu_attach_device(...) -ENODEV
37 #define IPMMU_CTX_INVALID -1
93 /* -----------------------------------------------------------------------------
100 #define IMCTR 0x0000 /* R-Car Gen2/3 */
[all …]
|
| /linux/arch/xtensa/include/asm/ |
| H A D | thread_info.h | 2 * include/asm-xtensa/thread_info.h
8 * Copyright (C) 2001 - 2005 Tensilica Inc.
24 * low level task data that entry.S needs immediate access to
25 * - this struct should fit entirely inside of one cache line
26 * - this struct shares the supervisor stack pages
27 * - if the contents of this structure are changed, the assembly constants
51 unsigned long status; /* thread-synchronous flags */
65 * If i-th bit is set then coprocessor state is loaded into the
80 * macros/functions for gaining access to the thread information structure
105 #define GET_THREAD_INFO(reg,sp) \ argument
[all …]
|
| /linux/drivers/net/wireless/silabs/wfx/ |
| H A D | fwio.c | 1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright (c) 2017-2020, Silicon Laboratories, Inc.
6 * Copyright (c) 2010, ST-Ericsson
88 return -ENOMEM; in wfx_sram_write_dma_safe()
107 wdev->pdata.file_fw, keyset_chip); in get_firmware()
108 ret = firmware_request_nowarn(fw, filename, wdev->dev); in get_firmware()
110 dev_info(wdev->dev, "can't load %s, falling back to %s.sec\n", in get_firmware()
111 filename, wdev->pdata.file_fw); in get_firmware()
112 snprintf(filename, sizeof(filename), "%s.sec", wdev->pdata.file_fw); in get_firmware()
113 ret = request_firmware(fw, filename, wdev->dev); in get_firmware()
[all …]
|
| /linux/Documentation/devicetree/bindings/interconnect/ |
| H A D | fsl,imx8m-noc.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/interconnect/fsl,imx8m-noc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Peng Fan <peng.fan@nxp.com>
17 ("Global Programmers View") but not all. Access to this area might be denied
18 for normal (non-secure) world.
20 The buses are based on externally licensed IPs such as ARM NIC-301 and
27 - items:
28 - enum:
[all …]
|
| /linux/drivers/crypto/caam/ |
| H A D | regs.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
3 * CAAM hardware register-level view
5 * Copyright 2008-2011 Freescale Semiconductor, Inc.
15 #include <linux/io-64-nonatomic-hi-lo.h>
18 * Architecture-specific register access methods
20 * CAAM's bus-addressable registers are 64 bits internally.
21 * They have been wired to be safely accessible on 32-bit
24 * can be treated as two 32-bit entities, or finally (c) if they
25 * must be treated as a single 64-bit value, then this can safely
26 * be done with two 32-bit cycles.
[all …]
|
| /linux/drivers/mailbox/ |
| H A D | ti-msgmgr.c | 1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (C) 2015-2022 Texas Instruments Incorporated - https://www.ti.com/
22 #include <linux/soc/ti/ti-msgmgr.h>
24 #define Q_DATA_OFFSET(proxy, queue, reg) \ argument
25 ((0x10000 * (proxy)) + (0x80 * (queue)) + ((reg) * 4))
30 #define SPROXY_THREAD_DATA_OFFSET(tid, reg) \ argument
31 (SPROXY_THREAD_OFFSET(tid) + ((reg) * 0x4) + 0x4)
41 * struct ti_msgmgr_valid_queue_desc - SoC valid queues meant for this processor
53 * struct ti_msgmgr_desc - Description of message manager integration
63 * @valid_queues: List of Valid queues that the processor can access
[all …]
|
| /linux/arch/arm64/kvm/hyp/nvhe/ |
| H A D | ffa.c | 1 // SPDX-License-Identifier: GPL-2.0-only
3 * FF-A v1.0 proxy to filter out invalid memory-sharing SMC calls issued by
4 * the host. FF-A is a slightly more palatable abbreviation of "Arm Firmware
5 * Framework for Arm A-profile", which is specified by Arm in document
8 * Copyright (C) 2022 - Google LLC
12 * all calls falling within the FF-A range. Each call is either:
14 * - Forwarded on unmodified to the SPMD at EL3
15 * - Rejected as "unsupported"
16 * - Accompanied by a host stage-2 page-table check/update and reissued
19 * accessible to the secure world using FF-A will be detected either here
[all …]
|
| /linux/Documentation/devicetree/bindings/arm/ |
| H A D | arm,cci-400.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/arm/arm,cci-400.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
13 ARM multi-cluster systems maintain intra-cluster coherency through a cache
24 pattern: "^cci(@[0-9a-f]+)?$"
28 - arm,cci-400
29 - arm,cci-500
30 - arm,cci-550
[all …]
|
| /linux/Documentation/devicetree/bindings/memory-controllers/ |
| H A D | nvidia,tegra186-mc.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/memory-controllers/nvidia,tegra186-mc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Jon Hunter <jonathanh@nvidia.com>
11 - Thierry Reding <thierry.reding@gmail.com>
16 handles memory requests for 40-bit virtual addresses from internal clients
21 available for video and other secure applications, as well as DRAM ECC for
27 pattern: "^memory-controller@[0-9a-f]+$"
31 - enum:
[all …]
|
| /linux/arch/arm/mach-omap2/ |
| H A D | control.h | 2 * arch/arm/mach-omap2/control.h
6 * Copyright (C) 2007-2010 Texas Instruments, Inc.
7 * Copyright (C) 2007-2008, 2010 Nokia Corporation
22 #define OMAP242X_CTRL_REGADDR(reg) \ argument
23 OMAP2_L4_IO_ADDRESS(OMAP242X_CTRL_BASE + (reg))
24 #define OMAP243X_CTRL_REGADDR(reg) \ argument
25 OMAP2_L4_IO_ADDRESS(OMAP243X_CTRL_BASE + (reg))
26 #define OMAP343X_CTRL_REGADDR(reg) \ argument
27 OMAP2_L4_IO_ADDRESS(OMAP343X_CTRL_BASE + (reg))
28 #define AM33XX_CTRL_REGADDR(reg) \ argument
[all …]
|
| /linux/drivers/crypto/inside-secure/ |
| H A D | safexcel.c | 1 // SPDX-License-Identifier: GPL-2.0
5 * Antoine Tenart <antoine.tenart@free-electrons.com>
10 #include <linux/dma-mapping.h>
45 writel(0, priv->base + EIP197_FLUE_IFC_LUT(i)); in eip197_trc_cache_setupvirt()
51 for (i = 0; i < priv->config.rings; i++) { in eip197_trc_cache_setupvirt()
52 writel(0, priv->base + EIP197_FLUE_CACHEBASE_LO(i)); in eip197_trc_cache_setupvirt()
53 writel(0, priv->base + EIP197_FLUE_CACHEBASE_HI(i)); in eip197_trc_cache_setupvirt()
55 priv->base + EIP197_FLUE_CONFIG(i)); in eip197_trc_cache_setupvirt()
57 writel(0, priv->base + EIP197_FLUE_OFFSETS); in eip197_trc_cache_setupvirt()
58 writel(0, priv->base + EIP197_FLUE_ARC4_OFFSET); in eip197_trc_cache_setupvirt()
[all …]
|
| /linux/arch/powerpc/ |
| H A D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0
5 def_bool PPC64 && $(cc-option, -mabi=elfv2)
8 def_bool PPC64 && $(cc-option, -mcpu=power10 -mprefixed)
11 # Clang has a bug (https://github.com/llvm/llvm-project/issues/62372)
12 # where pcrel code is not generated if -msoft-float, -mno-altivec, or
13 # -mno-vsx options are also given. Without these options, fp/vec
16 def_bool PPC64 && CC_IS_GCC && $(cc-option, -mcpu=power10 -mpcrel)
35 # On Book3S 64, the default virtual address space for 64-bit processes
38 # between bottom-up and top-down allocations for applications that
41 default 29 if PPC_BOOK3S_64 && PPC_64K_PAGES # 29 = 45 (32T) - 16 (64K)
[all …]
|
| /linux/arch/arm/mach-imx/ |
| H A D | cpu-imx5.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Copyright 2008-2010 Freescale Semiconductor, Inc. All Rights Reserved.
19 static int mx5_cpu_rev = -1;
43 u32 rev = imx5_read_srev_reg("fsl,imx51-iim"); in get_mx51_srev()
61 if (mx5_cpu_rev == -1) in mx51_revision()
72 * Dependent on link order - so the assumption is that vfp_init is called
89 u32 rev = imx5_read_srev_reg("fsl,imx53-iim"); in get_mx53_srev()
109 if (mx5_cpu_rev == -1) in mx53_revision()
135 np = of_find_compatible_node(NULL, NULL, "arm,cortex-a8-pmu"); in imx5_pmu_init()
139 if (!of_property_read_bool(np, "secure-reg-access")) in imx5_pmu_init()
[all …]
|
| /linux/Documentation/devicetree/bindings/firmware/xilinx/ |
| H A D | xlnx,zynqmp-firmware.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/firmware/xilinx/xlnx,zynqmp-firmware.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Nava kishore Manne <nava.kishore.manne@amd.com>
12 description: The zynqmp-firmware node describes the interface to platform
13 firmware. ZynqMP has an interface to communicate with secure firmware.
23 - description: For implementations complying for Zynq Ultrascale+ MPSoC.
24 const: xlnx,zynqmp-firmware
26 - description: For implementations complying for Versal.
[all …]
|
| /linux/arch/arm/mm/ |
| H A D | cache-l2x0.c | 1 // SPDX-License-Identifier: GPL-2.0-only
3 * arch/arm/mm/cache-l2x0.c - L210/L220/L310 cache controller support
20 #include <asm/hardware/cache-l2x0.h>
21 #include <asm/hardware/cache-aurora-l2.h>
22 #include "cache-tauros3.h"
54 static inline void l2c_wait_mask(void __iomem *reg, unsigned long mask) in l2c_wait_mask() argument
57 while (readl_relaxed(reg) & mask) in l2c_wait_mask()
62 * By default, we write directly to secure registers. Platforms must
63 * override this if they are running non-secure.
65 static void l2c_write_sec(unsigned long val, void __iomem *base, unsigned reg) in l2c_write_sec() argument
[all …]
|