| /freebsd/sys/contrib/device-tree/Bindings/iommu/ |
| H A D | qcom,iommu.txt | 3 Qualcomm "B" family devices which are not compatible with arm-smmu have
4 a similar looking IOMMU but without access to the global register space,
6 to non-secure vs secure interrupt line.
10 - compatible : Should be one of:
12 "qcom,msm8916-iommu"
13 "qcom,msm8953-iommu"
15 Followed by "qcom,msm-iommu-v1".
17 - clock-names : Should be a pair of "iface" (required for IOMMUs
18 register group access) and "bus" (required for
19 the IOMMUs underlying bus access).
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| H A D | qcom,iommu.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Konrad Dybcio <konradybcio@kernel.org>
13 Qualcomm "B" family devices which are not compatible with arm-smmu have
14 a similar looking IOMMU, but without access to the global register space
16 to non-secure vs secure interrupt line.
21 - items:
22 - enum:
23 - qcom,msm8916-iommu
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| H A D | arm,smmu.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Will Deacon <will@kernel.org>
11 - Robin Murphy <Robin.Murphy@arm.com>
23 pattern: "^iommu@[0-9a-f]*"
26 - description: Qcom SoCs implementing "arm,smmu-v2"
28 - enum:
29 - qcom,msm8996-smmu-v2
30 - qcom,msm8998-smmu-v2
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| H A D | msm,iommu-v0.txt | 5 of the CPU, each connected to the IOMMU through a port called micro-TLB.
9 - compatible: Must contain "qcom,apq8064-iommu".
10 - reg: Base address and size of the IOMMU registers.
11 - interrupts: Specifiers for the MMU fault interrupts. For instances that
12 support secure mode two interrupts must be specified, for non-secure and
13 secure mode, in that order. For instances that don't support secure mode a
15 - #iommu-cells: The number of cells needed to specify the stream id. This
17 - qcom,ncb: The total number of context banks in the IOMMU.
18 - clocks : List of clocks to be used during SMMU register access. See
19 Documentation/devicetree/bindings/clock/clock-bindings.txt
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| /freebsd/sys/contrib/device-tree/Bindings/bus/ |
| H A D | st,stm32mp25-rifsc.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/bus/st,stm32mp25-rifsc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Gatien Chevallier <gatien.chevallier@foss.st.com>
19 - RISC registers associated with RISUP logic (resource isolation device unit
20 for peripherals), assign all non-RIF aware peripherals to zero, one or
21 any security domains (secure, privilege, compartment).
22 - RIMC registers: associated with RIMU logic (resource isolation master
23 unit), assign all non RIF-aware bus master to one security domain by
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| /freebsd/sys/contrib/device-tree/Bindings/arm/tegra/ |
| H A D | nvidia,tegra194-cbb.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/arm/tegra/nvidia,tegra194-cbb.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Sumit Gupta <sumitg@nvidia.com>
15 multiple hierarchical sub-NOCs (Network-on-Chip) and connects various
20 "AON-NOC, SCE-NOC, RCE-NOC, BPMP-NOC, CV-NOC" and "CBB Central NOC"
23 By default, the access issuing initiator is informed about the error
28 - For CCPLEX (CPU Complex) initiator, the driver sets ERD bit. So, the
31 - For other initiators, the ERD is disabled. So, the access issuing
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| /freebsd/sys/contrib/device-tree/Bindings/nvmem/ |
| H A D | st,stm32-romem.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/nvmem/st,stm32-romem.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: STMicroelectronics STM32 Factory-programmed data
10 This represents STM32 Factory-programmed read only non-volatile area: locked
11 flash, OTP, read-only HW regs... This contains various information such as:
16 - Fabrice Gasnier <fabrice.gasnier@foss.st.com>
19 - $ref: nvmem.yaml#
20 - $ref: nvmem-deprecated-cells.yaml#
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| /freebsd/sys/contrib/device-tree/Bindings/interrupt-controller/ |
| H A D | marvell,icu.txt | 2 --------------------------------
5 responsible for collecting all wired-interrupt sources in the CP and
8 These messages will access a different GIC memory area depending on
13 - compatible: Should be "marvell,cp110-icu"
15 - reg: Should contain ICU registers location and length.
22 - compatible: Should be one of:
23 * "marvell,cp110-icu-nsr"
24 * "marvell,cp110-icu-sr"
25 * "marvell,cp110-icu-sei"
26 * "marvell,cp110-icu-rei"
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| /freebsd/sys/contrib/device-tree/Bindings/timer/ |
| H A D | ti,timer-dm.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/timer/ti,timer-dm.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: TI dual-mode timer
10 - Tony Lindgren <tony@atomide.com>
13 The TI dual-mode timer is a general purpose timer with PWM capabilities.
18 - items:
19 - enum:
20 - ti,am335x-timer
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| /freebsd/contrib/wpa/hostapd/ |
| H A D | README-WPS | 1 hostapd and Wi-Fi Protected Setup (WPS)
10 -------------------
12 Wi-Fi Protected Setup (WPS) is a mechanism for easy configuration of a
14 passphrase/PSK) and configuration of an access point and client
16 with PIN method and push-button configuration (PBC) being the most
22 not very secure. As such, use of WPS may not be suitable for
23 environments that require secure network access without chance for
24 allowing outsiders to gain access during the setup phase.
28 - access point: the WLAN access point
29 - Registrar: a device that control a network and can authorize
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| /freebsd/sys/contrib/device-tree/Bindings/arm/ |
| H A D | pmu.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Mark Rutland <mark.rutland@arm.com>
11 - Will Deacon <will.deacon@arm.com>
16 representation in the device tree should be done as under:-
21 - enum:
22 - apm,potenza-pmu
23 - apple,avalanche-pmu
24 - apple,blizzard-pmu
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| H A D | arm,cci-400.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/arm/arm,cci-400.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
13 ARM multi-cluster systems maintain intra-cluster coherency through a cache
24 pattern: "^cci(@[0-9a-f]+)?$"
28 - arm,cci-400
29 - arm,cci-500
30 - arm,cci-550
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| H A D | cci.txt | 5 ARM multi-cluster systems maintain intra-cluster coherency through a
24 - compatible
28 "arm,cci-400"
29 "arm,cci-500"
30 "arm,cci-550"
32 - reg
40 - ranges:
53 - CCI control interface nodes
55 Node name must be "slave-if".
61 - compatible
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| H A D | arm,scmi.txt | 2 ----------------------------------------------------------
17 - compatible : shall be "arm,scmi" or "arm,scmi-smc" for smc/hvc transports
18 - mboxes: List of phandle and mailbox channel specifiers. It should contain
22 - shmem : List of phandle pointing to the shared memory(SHM) area as per
24 - #address-cells : should be '1' if the device has sub-nodes, maps to
25 protocol identifier for a given sub-node.
26 - #size-cells : should be '0' as 'reg' property doesn't have any size
28 - arm,smc-id : SMC id required when using smc or hvc transports
32 - mbox-names: shall be "tx" or "rx" depending on mboxes entries.
34 - interrupts : when using smc or hvc transports, this optional
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| /freebsd/sys/arm64/vmm/io/ |
| H A D | vgic_v3.c | 1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
5 * Copyright (C) 2020-2022 Andrew Turner
79 #define VGIC_SGI_NUM (GIC_LAST_SGI - GIC_FIRST_SGI + 1)
80 #define VGIC_PPI_NUM (GIC_LAST_PPI - GIC_FIRST_PPI + 1)
81 #define VGIC_SPI_NUM (GIC_LAST_SPI - GIC_FIRST_SPI + 1)
127 /* Per-CPU data not needed by EL2 */
209 /* GICD_STATUSR - RAZ/WI as we don't report errors (yet) */
212 /* GICD_SETSPI_SR - RAZ/WI */
213 /* GICD_CLRSPI_SR - RAZ/WI */
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| /freebsd/sys/arm/arm/ |
| H A D | generic_timer.c | 1 /*-
2 * SPDX-License-Identifier: BSD-3-Clause
36 * Cortex-A7, Cortex-A15, ARMv8 and later Generic Timer
91 #define GT_CNTKCTL_PL0PTEN (1 << 9) /* PL0 Physical timer reg access */
92 #define GT_CNTKCTL_PL0VTEN (1 << 8) /* PL0 Virtual timer reg access */
96 #define GT_CNTKCTL_PL0VCTEN (1 << 1) /* PL0 CNTVCT and CNTFRQ access */
97 #define GT_CNTKCTL_PL0PCTEN (1 << 0) /* PL0 CNTPCT and CNTFRQ access */
131 .name = "sec-phys",
146 .name = "hyp-phys",
151 .name = "hyp-virt",
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| H A D | cpuinfo.c | 1 /*-
61 * Be careful, ACTRL cannot be changed if CPU is started in secure
80 uint32_t reg; in sysctl_hw_cpu_quirks_actrl_value() local
82 reg = cp15_actlr_get(); in sysctl_hw_cpu_quirks_actrl_value()
83 return (SYSCTL_OUT(req, ®, sizeof(reg))); in sysctl_hw_cpu_quirks_actrl_value()
127 /* non ARM -> must be new id scheme */ in cpuinfo_init()
136 /* CP15 c0,c0 regs 0-7 exist on all CPUs (although aliased with MIDR) */ in cpuinfo_init()
161 /* Not yet - CBAR only exist on ARM SMP Cortex A CPUs in cpuinfo_init()
203 cpuinfo.dcache_line_mask = cpuinfo.dcache_line_size - 1; in cpuinfo_init()
204 cpuinfo.icache_line_mask = cpuinfo.icache_line_size - 1; in cpuinfo_init()
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| /freebsd/sys/contrib/device-tree/Bindings/interconnect/ |
| H A D | fsl,imx8m-noc.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/interconnect/fsl,imx8m-noc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Peng Fan <peng.fan@nxp.com>
17 ("Global Programmers View") but not all. Access to this area might be denied
18 for normal (non-secure) world.
20 The buses are based on externally licensed IPs such as ARM NIC-301 and
27 - items:
28 - enum:
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| /freebsd/sys/contrib/device-tree/Bindings/memory-controllers/ |
| H A D | nvidia,tegra186-mc.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/memory-controllers/nvidia,tegra186-mc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Jon Hunter <jonathanh@nvidia.com>
11 - Thierry Reding <thierry.reding@gmail.com>
16 handles memory requests for 40-bit virtual addresses from internal clients
21 available for video and other secure applications, as well as DRAM ECC for
27 pattern: "^memory-controller@[0-9a-f]+$"
31 - enum:
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| /freebsd/sys/contrib/device-tree/Bindings/firmware/xilinx/ |
| H A D | xlnx,zynqmp-firmware.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/firmware/xilinx/xlnx,zynqmp-firmware.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Nava kishore Manne <nava.kishore.manne@amd.com>
12 description: The zynqmp-firmware node describes the interface to platform
13 firmware. ZynqMP has an interface to communicate with secure firmware.
23 - description: For implementations complying for Zynq Ultrascale+ MPSoC.
24 const: xlnx,zynqmp-firmware
26 - description: For implementations complying for Versal.
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| /freebsd/sys/contrib/device-tree/src/arm/ti/omap/ |
| H A D | omap3-tao3530.dtsi | 1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2012 Texas Instruments Incorporated - https://www.ti.com/
6 /dts-v1/;
10 /* Secure omaps have some devices inaccessible depending on the firmware */
26 cpu0-supply = <&vcc>;
32 reg = <0x80000000 0x10000000>; /* 256 MB */
37 compatible = "regulator-fixed";
38 regulator-name = "hsusb2_vbus";
39 regulator-min-microvolt = <3300000>;
40 regulator-max-microvolt = <3300000>;
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| H A D | dra7.dtsi | 1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2013 Texas Instruments Incorporated - https://www.ti.com/
8 #include <dt-bindings/bus/ti-sysc.h>
9 #include <dt-bindings/clock/dra7.h>
10 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 #include <dt-bindings/pinctrl/dra.h>
12 #include <dt-bindings/clock/dra7.h>
17 #address-cells = <2>;
18 #size-cells = <2>;
21 interrupt-parent = <&crossbar_mpu>;
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| H A D | omap3-n900.dts | 1 // SPDX-License-Identifier: GPL-2.0-or-later
4 * Copyright (C) 2013-2014 Aaro Koskinen <aaro.koskinen@iki.fi>
7 /dts-v1/;
10 #include <dt-bindings/input/input.h>
11 #include <dt-bindings/leds/common.h>
12 #include <dt-bindings/media/video-interfaces.h>
15 * Default secure signed bootloader (Nokia X-Loader) does not enable L3 firewall
16 * for omap AES HW crypto support. When linux kernel try to access memory of AES
17 * blocks then kernel receive "Unhandled fault: external abort on non-linefetch"
18 * and crash. Until somebody fix omap-aes.c and omap_hwmod_3xxx_data.c code (no
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| /freebsd/sys/arm64/nvidia/tegra210/ |
| H A D | tegra210_pmc.c | 1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
137 /* Secure access */
142 #define PMC_LOCK(_sc) mtx_lock(&(_sc)->mtx)
143 #define PMC_UNLOCK(_sc) mtx_unlock(&(_sc)->mtx)
144 #define PMC_LOCK_INIT(_sc) mtx_init(&(_sc)->mtx, \
145 device_get_nameunit(_sc->dev), "tegra210_pmc", MTX_DEF)
146 #define PMC_LOCK_DESTROY(_sc) mtx_destroy(&(_sc)->mtx);
147 #define PMC_ASSERT_LOCKED(_sc) mtx_assert(&(_sc)->mtx, MA_OWNED);
148 #define PMC_ASSERT_UNLOCKED(_sc) mtx_assert(&(_sc)->mtx, MA_NOTOWNED);
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| /freebsd/sys/contrib/device-tree/src/arm/nxp/imx/ |
| H A D | imx6q-bx50v3.dtsi | 5 * This file is dual-licensed: you can use it either under the terms
43 #include "imx6q-ba16.dtsi"
46 mclk: clock-mclk {
47 compatible = "fixed-clock";
48 #clock-cells = <0>;
49 clock-frequency = <22000000>;
52 gpio-poweroff {
53 compatible = "gpio-poweroff";
58 reg_wl18xx_vmmc: regulator-wl18xx {
59 compatible = "regulator-fixe
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