Lines Matching +full:secure +full:- +full:reg +full:- +full:access
1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
137 /* Secure access */
142 #define PMC_LOCK(_sc) mtx_lock(&(_sc)->mtx)
143 #define PMC_UNLOCK(_sc) mtx_unlock(&(_sc)->mtx)
144 #define PMC_LOCK_INIT(_sc) mtx_init(&(_sc)->mtx, \
145 device_get_nameunit(_sc->dev), "tegra210_pmc", MTX_DEF)
146 #define PMC_LOCK_DESTROY(_sc) mtx_destroy(&(_sc)->mtx);
147 #define PMC_ASSERT_LOCKED(_sc) mtx_assert(&(_sc)->mtx, MA_OWNED);
148 #define PMC_ASSERT_UNLOCKED(_sc) mtx_assert(&(_sc)->mtx, MA_NOTOWNED);
173 {"nvidia,tegra210-pmc", 1},
192 if (sc->secure_access) { in WR4()
195 device_printf(sc->dev," PMC SMC write failed: %lu\n", in WR4()
199 bus_write_4(sc->mem_res, r, v); in WR4()
207 if (sc->secure_access) { in RD4()
210 device_printf(sc->dev," PMC SMC write failed: %lu\n", in RD4()
215 return(bus_read_4(sc->mem_res, r)); in RD4()
222 uint32_t reg; in tegra210_pmc_set_powergate() local
227 reg = RD4(sc, PMC_PWRGATE_STATUS) & PMC_PWRGATE_STATUS_PARTID(id); in tegra210_pmc_set_powergate()
228 if (((reg != 0) && ena) || ((reg == 0) && !ena)) { in tegra210_pmc_set_powergate()
233 for (i = 100; i > 0; i--) { in tegra210_pmc_set_powergate()
234 reg = RD4(sc, PMC_PWRGATE_TOGGLE); in tegra210_pmc_set_powergate()
235 if ((reg & PMC_PWRGATE_TOGGLE_START) == 0) in tegra210_pmc_set_powergate()
240 device_printf(sc->dev, in tegra210_pmc_set_powergate()
246 for (i = 100; i > 0; i--) { in tegra210_pmc_set_powergate()
247 reg = RD4(sc, PMC_PWRGATE_TOGGLE); in tegra210_pmc_set_powergate()
248 if ((reg & PMC_PWRGATE_TOGGLE_START) == 0) in tegra210_pmc_set_powergate()
253 device_printf(sc->dev, in tegra210_pmc_set_powergate()
263 uint32_t reg; in tegra_powergate_remove_clamping() local
274 reg = RD4(sc, PMC_PWRGATE_STATUS); in tegra_powergate_remove_clamping()
275 if ((reg & PMC_PWRGATE_STATUS_PARTID(id)) == 0) in tegra_powergate_remove_clamping()
286 for (i = 100; i > 0; i--) { in tegra_powergate_remove_clamping()
287 reg = RD4(sc, PMC_REMOVE_CLAMPING_CMD); in tegra_powergate_remove_clamping()
288 if ((reg & PMC_REMOVE_CLAMPING_CMD_PARTID(swid)) == 0) in tegra_powergate_remove_clamping()
293 device_printf(sc->dev, "Timeout when remove clamping\n"); in tegra_powergate_remove_clamping()
295 reg = RD4(sc, PMC_CLAMP_STATUS); in tegra_powergate_remove_clamping()
296 if ((reg & PMC_CLAMP_STATUS_PARTID(id)) != 0) in tegra_powergate_remove_clamping()
306 uint32_t reg; in tegra_powergate_is_powered() local
310 reg = RD4(sc, PMC_PWRGATE_STATUS); in tegra_powergate_is_powered()
311 return ((reg & PMC_PWRGATE_STATUS_PARTID(id)) ? 1 : 0); in tegra_powergate_is_powered()
324 device_printf(sc->dev, "Cannot set powergate: %d\n", id); in tegra_powergate_power_on()
328 for (i = 100; i > 0; i--) { in tegra_powergate_power_on()
334 device_printf(sc->dev, "Timeout when waiting on power up\n"); in tegra_powergate_power_on()
351 device_printf(sc->dev, "Cannot set powergate: %d\n", id); in tegra_powergate_power_off()
354 for (i = 100; i > 0; i--) { in tegra_powergate_power_off()
360 device_printf(sc->dev, "Timeout when waiting on power off\n"); in tegra_powergate_power_off()
376 device_printf(sc->dev, "Cannot assert reset\n"); in tegra_powergate_sequence_power_up()
382 device_printf(sc->dev, "Cannot stop clock\n"); in tegra_powergate_sequence_power_up()
388 device_printf(sc->dev, "Cannot power on powergate\n"); in tegra_powergate_sequence_power_up()
394 device_printf(sc->dev, "Cannot enable clock\n"); in tegra_powergate_sequence_power_up()
401 device_printf(sc->dev, "Cannot remove clamping\n"); in tegra_powergate_sequence_power_up()
406 device_printf(sc->dev, "Cannot unreset reset\n"); in tegra_powergate_sequence_power_up()
426 rv = OF_getencprop(node, "nvidia,suspend-mode", &tmp, sizeof(tmp)); in tegra210_pmc_parse_fdt()
430 sc->suspend_mode = TEGRA_SUSPEND_LP0; in tegra210_pmc_parse_fdt()
434 sc->suspend_mode = TEGRA_SUSPEND_LP1; in tegra210_pmc_parse_fdt()
438 sc->suspend_mode = TEGRA_SUSPEND_LP2; in tegra210_pmc_parse_fdt()
442 sc->suspend_mode = TEGRA_SUSPEND_NONE; in tegra210_pmc_parse_fdt()
447 rv = OF_getencprop(node, "nvidia,cpu-pwr-good-time", &tmp, sizeof(tmp)); in tegra210_pmc_parse_fdt()
449 sc->cpu_good_time = tmp; in tegra210_pmc_parse_fdt()
450 sc->suspend_mode = TEGRA_SUSPEND_NONE; in tegra210_pmc_parse_fdt()
453 rv = OF_getencprop(node, "nvidia,cpu-pwr-off-time", &tmp, sizeof(tmp)); in tegra210_pmc_parse_fdt()
455 sc->cpu_off_time = tmp; in tegra210_pmc_parse_fdt()
456 sc->suspend_mode = TEGRA_SUSPEND_NONE; in tegra210_pmc_parse_fdt()
459 rv = OF_getencprop(node, "nvidia,core-pwr-good-time", tmparr, in tegra210_pmc_parse_fdt()
462 sc->core_osc_time = tmparr[0]; in tegra210_pmc_parse_fdt()
463 sc->core_pmu_time = tmparr[1]; in tegra210_pmc_parse_fdt()
464 sc->suspend_mode = TEGRA_SUSPEND_NONE; in tegra210_pmc_parse_fdt()
467 rv = OF_getencprop(node, "nvidia,core-pwr-off-time", &tmp, sizeof(tmp)); in tegra210_pmc_parse_fdt()
469 sc->core_off_time = tmp; in tegra210_pmc_parse_fdt()
470 sc->suspend_mode = TEGRA_SUSPEND_NONE; in tegra210_pmc_parse_fdt()
473 sc->corereq_high = in tegra210_pmc_parse_fdt()
474 OF_hasprop(node, "nvidia,core-power-req-active-high"); in tegra210_pmc_parse_fdt()
475 sc->sysclkreq_high = in tegra210_pmc_parse_fdt()
476 OF_hasprop(node, "nvidia,sys-clock-req-active-high"); in tegra210_pmc_parse_fdt()
477 sc->combined_req = in tegra210_pmc_parse_fdt()
478 OF_hasprop(node, "nvidia,combined-power-req"); in tegra210_pmc_parse_fdt()
479 sc->cpu_pwr_good_en = in tegra210_pmc_parse_fdt()
480 OF_hasprop(node, "nvidia,cpu-pwr-good-en"); in tegra210_pmc_parse_fdt()
482 rv = OF_getencprop(node, "nvidia,lp0-vec", tmparr, sizeof(tmparr)); in tegra210_pmc_parse_fdt()
485 sc->lp0_vec_phys = tmparr[0]; in tegra210_pmc_parse_fdt()
486 sc->core_pmu_time = tmparr[1]; in tegra210_pmc_parse_fdt()
487 sc->lp0_vec_size = TEGRA_SUSPEND_NONE; in tegra210_pmc_parse_fdt()
488 if (sc->suspend_mode == TEGRA_SUSPEND_LP0) in tegra210_pmc_parse_fdt()
489 sc->suspend_mode = TEGRA_SUSPEND_LP1; in tegra210_pmc_parse_fdt()
499 sc->secure_access = false; in tegra210_pmc_check_secure()
502 * If PMC is coverd by secure trust zone, all reads returns 0, in tegra210_pmc_check_secure()
508 sc->secure_access = true; in tegra210_pmc_check_secure()
513 sc->secure_access = true; in tegra210_pmc_check_secure()
526 if (!ofw_bus_search_compatible(dev, compat_data)->ocd_data) in tegra210_pmc_probe()
546 uint32_t reg; in tegra210_pmc_attach() local
550 sc->dev = dev; in tegra210_pmc_attach()
556 device_printf(sc->dev, "Cannot parse FDT data\n"); in tegra210_pmc_attach()
560 rv = clk_get_by_ofw_name(sc->dev, 0, "pclk", &sc->clk); in tegra210_pmc_attach()
562 device_printf(sc->dev, "Cannot get \"pclk\" clock\n"); in tegra210_pmc_attach()
567 sc->mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, in tegra210_pmc_attach()
569 if (sc->mem_res == NULL) { in tegra210_pmc_attach()
577 reg = RD4(sc, PMC_CNTRL); in tegra210_pmc_attach()
578 reg |= PMC_CNTRL_CPU_PWRREQ_OE; in tegra210_pmc_attach()
579 WR4(sc, PMC_CNTRL, reg); in tegra210_pmc_attach()
582 reg = RD4(sc, PMC_CNTRL); in tegra210_pmc_attach()
583 if (sc->sysclkreq_high) in tegra210_pmc_attach()
584 reg &= ~PMC_CNTRL_SYSCLK_POLARITY; in tegra210_pmc_attach()
586 reg |= PMC_CNTRL_SYSCLK_POLARITY; in tegra210_pmc_attach()
587 WR4(sc, PMC_CNTRL, reg); in tegra210_pmc_attach()
590 reg = RD4(sc, PMC_CNTRL); in tegra210_pmc_attach()
591 reg |= PMC_CNTRL_SYSCLK_OE; in tegra210_pmc_attach()
592 WR4(sc, PMC_CNTRL, reg); in tegra210_pmc_attach()
598 reg = RD4(sc, PMC_IO_DPD_STATUS); in tegra210_pmc_attach()
599 reg &= ~ PMC_IO_DPD_STATUS_HDMI; in tegra210_pmc_attach()
600 WR4(sc, PMC_IO_DPD_STATUS, reg); in tegra210_pmc_attach()
602 reg = RD4(sc, PMC_IO_DPD2_STATUS); in tegra210_pmc_attach()
603 reg &= ~ PMC_IO_DPD2_STATUS_HV; in tegra210_pmc_attach()
604 WR4(sc, PMC_IO_DPD2_STATUS, reg); in tegra210_pmc_attach()