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Searched +full:sdma +full:- +full:event +full:- +full:remap (Results 1 – 9 of 9) sorted by relevance

/linux/arch/arm/boot/dts/nxp/imx/
H A Dimx6sx-sdb-sai.dts1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
5 #include "imx6sx-sdb.dts"
9 audio-cpu = <&sai1>;
22 &sdma {
24 /* SDMA event remap for SAI1 */
25 fsl,sdma-event-remap = <0 15 1>, <0 16 1>;
H A Dimx6sx-sdb-mqs.dts1 // SPDX-License-Identifier: GPL-2.0
5 #include "imx6sx-sdb.dts"
12 sound-mqs {
13 compatible = "fsl,imx6sx-sdb-mqs",
14 "fsl,imx-audio-mqs";
15 model = "mqs-audio";
16 audio-cpu = <&sai1>;
17 audio-asrc = <&asrc>;
18 audio-codec = <&mqs>;
28 pinctrl-names = "default";
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/linux/drivers/dma/
H A Dimx-sdma.c1 // SPDX-License-Identifier: GPL-2.0+
3 // drivers/dma/imx-sdma.c
11 // Copyright 2004-2009 Freescale Semiconductor, Inc. All Rights Reserved.
28 #include <linux/dma-mapping.h>
39 #include <linux/dma/imx-dma.h>
42 #include <linux/mfd/syscon/imx6q-iomuxc-gpr.h>
45 #include "virt-dma.h"
47 /* SDMA registers */
105 * Error bit set in the CCB status field by the SDMA,
130 * 0-7 Lower WML Lower watermark level
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/linux/drivers/gpu/drm/amd/amdgpu/
H A Damdgpu_ucode.c16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
40 DRM_DEBUG("size_bytes: %u\n", le32_to_cpu(hdr->size_bytes)); in amdgpu_ucode_print_common_hdr()
41 DRM_DEBUG("header_size_bytes: %u\n", le32_to_cpu(hdr->header_size_bytes)); in amdgpu_ucode_print_common_hdr()
42 DRM_DEBUG("header_version_major: %u\n", le16_to_cpu(hdr->header_version_major)); in amdgpu_ucode_print_common_hdr()
43 DRM_DEBUG("header_version_minor: %u\n", le16_to_cpu(hdr->header_version_minor)); in amdgpu_ucode_print_common_hdr()
44 DRM_DEBUG("ip_version_major: %u\n", le16_to_cpu(hdr->ip_version_major)); in amdgpu_ucode_print_common_hdr()
45 DRM_DEBUG("ip_version_minor: %u\n", le16_to_cpu(hdr->ip_version_minor)); in amdgpu_ucode_print_common_hdr()
46 DRM_DEBUG("ucode_version: 0x%08x\n", le32_to_cpu(hdr->ucode_version)); in amdgpu_ucode_print_common_hdr()
47 DRM_DEBUG("ucode_size_bytes: %u\n", le32_to_cpu(hdr->ucode_size_bytes)); in amdgpu_ucode_print_common_hdr()
49 le32_to_cpu(hdr->ucode_array_offset_bytes)); in amdgpu_ucode_print_common_hdr()
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H A Dgfx_v11_0.c16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
349 struct amdgpu_device *adev = kiq_ring->adev; in gfx11_kiq_set_resources()
353 shader_mc_addr = adev->gfx.cleaner_shader_gpu_addr >> 8; in gfx11_kiq_set_resources()
370 uint64_t mqd_addr = amdgpu_bo_gpu_offset(ring->mqd_obj); in gfx11_kiq_map_queues()
371 uint64_t wptr_addr = ring->wptr_gpu_addr; in gfx11_kiq_map_queues()
374 switch (ring->funcs->type) { in gfx11_kiq_map_queues()
396 PACKET3_MAP_QUEUES_QUEUE(ring->queue) | in gfx11_kiq_map_queues()
397 PACKET3_MAP_QUEUES_PIPE(ring->pipe) | in gfx11_kiq_map_queues()
403 amdgpu_ring_write(kiq_ring, PACKET3_MAP_QUEUES_DOORBELL_OFFSET(ring->doorbell_index)); in gfx11_kiq_map_queues()
415 struct amdgpu_device *adev = kiq_ring->adev; in gfx11_kiq_unmap_queues()
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H A Dgfx_v12_0.c16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
310 uint64_t mqd_addr = amdgpu_bo_gpu_offset(ring->mqd_obj); in gfx_v12_0_kiq_map_queues()
311 uint64_t wptr_addr = ring->wptr_gpu_addr; in gfx_v12_0_kiq_map_queues()
314 switch (ring->funcs->type) { in gfx_v12_0_kiq_map_queues()
336 PACKET3_MAP_QUEUES_QUEUE(ring->queue) | in gfx_v12_0_kiq_map_queues()
337 PACKET3_MAP_QUEUES_PIPE(ring->pipe) | in gfx_v12_0_kiq_map_queues()
343 amdgpu_ring_write(kiq_ring, PACKET3_MAP_QUEUES_DOORBELL_OFFSET(ring->doorbell_index)); in gfx_v12_0_kiq_map_queues()
355 struct amdgpu_device *adev = kiq_ring->adev; in gfx_v12_0_kiq_unmap_queues()
356 uint32_t eng_sel = ring->funcs->type == AMDGPU_RING_TYPE_GFX ? 4 : 0; in gfx_v12_0_kiq_unmap_queues()
358 if (adev->enable_mes && !adev->gfx.kiq[0].ring.sched.ready) { in gfx_v12_0_kiq_unmap_queues()
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/linux/include/uapi/drm/
H A Damdgpu_drm.h1 /* amdgpu_drm.h -- Public header for the amdgpu driver -*- linux-c -*-
20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
90 * GPU's virtual address space via gart. Gart memory linearizes non-contiguous
97 * %AMDGPU_GEM_DOMAIN_GDS Global on-chip data storage used to share data
109 * %AMDGPU_GEM_DOMAIN_MMIO_REMAP MMIO remap page (special mapping for HDP flushing).
178 /* Flag that BO should be coherent across devices when using device-level
186 /* Set PTE.D and recompress during GTT->VRAM moves according to TILING flags. */
279 #define AMDGPU_CTX_PRIORITY_UNSET -2048
280 #define AMDGPU_CTX_PRIORITY_VERY_LOW -1023
281 #define AMDGPU_CTX_PRIORITY_LOW -512
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/linux/drivers/infiniband/hw/hfi1/
H A Dchip.c1 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
3 * Copyright(c) 2015 - 2020 Intel Corporation.
20 #include "sdma.h"
32 MODULE_PARM_DESC(num_vls, "Set number of Virtual Lanes to use (1-8)");
78 #define SEC_SC_HALTED 0x4 /* per-context only */
79 #define SEC_SPC_FREEZE 0x8 /* per-HFI only */
87 * 0 - User Fecn Handling
88 * 1 - Vnic
89 * 2 - AIP
90 * 3 - Verbs
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/linux/drivers/bus/
H A Dti-sysc.c1 // SPDX-License-Identifier: GPL-2.0
3 * ti-sysc.c - Texas Instruments sysc interconnect target driver
8 * Copyright (C) 2017-2024 Texas Instruments Incorporated - https://www.ti.com/
13 * Copyright (C) 2009-2011 Nokia Corporation
14 * Copyright (C) 2011-2021 Texas Instruments Incorporated - https://www.ti.com/
35 #include <linux/platform_data/ti-sysc.h>
37 #include <dt-bindings/bus/ti-sysc.h>
107 * struct sysc - TI sysc interconnect target module registers and capabilities
113 * @mdata: ti-sysc to hwmod translation data for a module
130 * @pre_reset_quirk: module specific pre-reset quirk
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