Lines Matching +full:sdma +full:- +full:event +full:- +full:remap
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
203 return -EINVAL; in soc15_query_video_codecs()
235 return -EINVAL; in soc15_query_video_codecs()
248 spin_lock_irqsave(&adev->uvd_ctx_idx_lock, flags); in soc15_uvd_ctx_rreg()
251 spin_unlock_irqrestore(&adev->uvd_ctx_idx_lock, flags); in soc15_uvd_ctx_rreg()
262 spin_lock_irqsave(&adev->uvd_ctx_idx_lock, flags); in soc15_uvd_ctx_wreg()
265 spin_unlock_irqrestore(&adev->uvd_ctx_idx_lock, flags); in soc15_uvd_ctx_wreg()
276 spin_lock_irqsave(&adev->didt_idx_lock, flags); in soc15_didt_rreg()
279 spin_unlock_irqrestore(&adev->didt_idx_lock, flags); in soc15_didt_rreg()
290 spin_lock_irqsave(&adev->didt_idx_lock, flags); in soc15_didt_wreg()
293 spin_unlock_irqrestore(&adev->didt_idx_lock, flags); in soc15_didt_wreg()
301 spin_lock_irqsave(&adev->gc_cac_idx_lock, flags); in soc15_gc_cac_rreg()
304 spin_unlock_irqrestore(&adev->gc_cac_idx_lock, flags); in soc15_gc_cac_rreg()
312 spin_lock_irqsave(&adev->gc_cac_idx_lock, flags); in soc15_gc_cac_wreg()
315 spin_unlock_irqrestore(&adev->gc_cac_idx_lock, flags); in soc15_gc_cac_wreg()
323 spin_lock_irqsave(&adev->se_cac_idx_lock, flags); in soc15_se_cac_rreg()
326 spin_unlock_irqrestore(&adev->se_cac_idx_lock, flags); in soc15_se_cac_rreg()
334 spin_lock_irqsave(&adev->se_cac_idx_lock, flags); in soc15_se_cac_wreg()
337 spin_unlock_irqrestore(&adev->se_cac_idx_lock, flags); in soc15_se_cac_wreg()
342 return adev->nbio.funcs->get_memsize(adev); in soc15_get_config_memsize()
347 u32 reference_clock = adev->clock.spll.reference_freq; in soc15_get_xclk()
409 mutex_lock(&adev->grbm_idx_mutex); in soc15_read_indexed_register()
417 mutex_unlock(&adev->grbm_idx_mutex); in soc15_read_indexed_register()
429 return adev->gfx.config.gb_addr_config; in soc15_get_register_value()
431 return adev->gfx.config.db_debug2; in soc15_get_register_value()
445 if (!adev->reg_offset[en->hwip][en->inst]) in soc15_read_register()
447 else if (reg_offset != (adev->reg_offset[en->hwip][en->inst][en->seg] in soc15_read_register()
448 + en->reg_offset)) in soc15_read_register()
456 return -EINVAL; in soc15_read_register()
461 * soc15_program_register_sequence - program an array of registers.
481 reg = adev->reg_offset[entry->hwip][entry->instance][entry->segment] + entry->reg; in soc15_program_register_sequence()
483 if (entry->and_mask == 0xffffffff) { in soc15_program_register_sequence()
484 tmp = entry->or_mask; in soc15_program_register_sequence()
486 tmp = (entry->hwip == GC_HWIP) ? in soc15_program_register_sequence()
489 tmp &= ~(entry->and_mask); in soc15_program_register_sequence()
490 tmp |= (entry->or_mask & entry->and_mask); in soc15_program_register_sequence()
499 (entry->hwip == GC_HWIP) ? in soc15_program_register_sequence()
512 if (ras && adev->ras_enabled) in soc15_asic_baco_reset()
513 adev->nbio.funcs->enable_doorbell_interrupt(adev, false); in soc15_asic_baco_reset()
519 /* re-enable doorbell interrupt after BACO exit */ in soc15_asic_baco_reset()
520 if (ras && adev->ras_enabled) in soc15_asic_baco_reset()
521 adev->nbio.funcs->enable_doorbell_interrupt(adev, true); in soc15_asic_baco_reset()
533 if (adev->gmc.xgmi.supported && adev->gmc.xgmi.connected_to_cpu) in soc15_asic_reset_method()
546 if (amdgpu_reset_method != -1) in soc15_asic_reset_method()
547 dev_warn(adev->dev, "Specified reset method:%d isn't supported, using AUTO instead.\n", in soc15_asic_reset_method()
558 if (adev->asic_type == CHIP_VEGA20) { in soc15_asic_reset_method()
559 if (adev->psp.sos.fw_version >= 0x80067) in soc15_asic_reset_method()
565 if (ras && adev->ras_enabled && in soc15_asic_reset_method()
566 adev->pm.fw_version <= 0x283400) in soc15_asic_reset_method()
587 if (adev->pcie_reset_ctx.in_link_reset) in soc15_asic_reset_method()
591 else if (!(adev->flags & AMD_IS_APU)) in soc15_asic_reset_method()
611 if (adev->in_s3 && !pm_resume_via_firmware()) in soc15_need_reset_on_resume()
625 if ((adev->apu_flags & AMD_APU_IS_PICASSO || in soc15_asic_reset()
626 !(adev->apu_flags & AMD_APU_IS_RAVEN)) && in soc15_asic_reset()
630 if ((adev->apu_flags & AMD_APU_IS_RAVEN) || in soc15_asic_reset()
631 (adev->apu_flags & AMD_APU_IS_RAVEN2)) in soc15_asic_reset()
637 dev_info(adev->dev, "PCI reset\n"); in soc15_asic_reset()
640 dev_info(adev->dev, "BACO reset\n"); in soc15_asic_reset()
643 dev_info(adev->dev, "MODE2 reset\n"); in soc15_asic_reset()
646 dev_info(adev->dev, "Link reset\n"); in soc15_asic_reset()
649 dev_info(adev->dev, "MODE1 reset\n"); in soc15_asic_reset()
659 if (adev->asic_type == CHIP_VEGA20) { in soc15_supports_baco()
660 if (adev->psp.sos.fw_version >= 0x80067) in soc15_supports_baco()
703 if (adev->nbio.funcs->program_aspm) in soc15_program_aspm()
704 adev->nbio.funcs->program_aspm(adev); in soc15_program_aspm()
719 switch (adev->asic_type) { in soc15_reg_base_init()
736 DRM_ERROR("Unsupported asic type: %d!\n", adev->asic_type); in soc15_reg_base_init()
743 adev->virt.ops = &xgpu_ai_virt_ops; in soc15_set_virt_ops()
766 if (adev->flags & AMD_IS_APU) in soc15_get_pcie_usage()
813 if (adev->flags & AMD_IS_APU) in vega20_get_pcie_usage()
866 if (adev->flags & AMD_IS_APU) in soc15_need_reset_on_init()
962 struct amdgpu_device *adev = ip_block->adev; in soc15_common_early_init()
964 adev->nbio.funcs->set_reg_remap(adev); in soc15_common_early_init()
965 adev->smc_rreg = NULL; in soc15_common_early_init()
966 adev->smc_wreg = NULL; in soc15_common_early_init()
967 adev->pcie_rreg = &amdgpu_device_indirect_rreg; in soc15_common_early_init()
968 adev->pcie_wreg = &amdgpu_device_indirect_wreg; in soc15_common_early_init()
969 adev->pcie_rreg_ext = &amdgpu_device_indirect_rreg_ext; in soc15_common_early_init()
970 adev->pcie_wreg_ext = &amdgpu_device_indirect_wreg_ext; in soc15_common_early_init()
971 adev->pcie_rreg64 = &amdgpu_device_indirect_rreg64; in soc15_common_early_init()
972 adev->pcie_wreg64 = &amdgpu_device_indirect_wreg64; in soc15_common_early_init()
973 adev->pcie_rreg64_ext = &amdgpu_device_indirect_rreg64_ext; in soc15_common_early_init()
974 adev->pcie_wreg64_ext = &amdgpu_device_indirect_wreg64_ext; in soc15_common_early_init()
975 adev->uvd_ctx_rreg = &soc15_uvd_ctx_rreg; in soc15_common_early_init()
976 adev->uvd_ctx_wreg = &soc15_uvd_ctx_wreg; in soc15_common_early_init()
977 adev->didt_rreg = &soc15_didt_rreg; in soc15_common_early_init()
978 adev->didt_wreg = &soc15_didt_wreg; in soc15_common_early_init()
979 adev->gc_cac_rreg = &soc15_gc_cac_rreg; in soc15_common_early_init()
980 adev->gc_cac_wreg = &soc15_gc_cac_wreg; in soc15_common_early_init()
981 adev->se_cac_rreg = &soc15_se_cac_rreg; in soc15_common_early_init()
982 adev->se_cac_wreg = &soc15_se_cac_wreg; in soc15_common_early_init()
984 adev->rev_id = amdgpu_device_get_rev_id(adev); in soc15_common_early_init()
985 adev->external_rev_id = 0xFF; in soc15_common_early_init()
991 adev->asic_funcs = &soc15_asic_funcs; in soc15_common_early_init()
992 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | in soc15_common_early_init()
1011 adev->pg_flags = 0; in soc15_common_early_init()
1012 adev->external_rev_id = 0x1; in soc15_common_early_init()
1015 adev->asic_funcs = &soc15_asic_funcs; in soc15_common_early_init()
1016 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | in soc15_common_early_init()
1034 adev->pg_flags = 0; in soc15_common_early_init()
1035 adev->external_rev_id = adev->rev_id + 0x14; in soc15_common_early_init()
1038 adev->asic_funcs = &vega20_asic_funcs; in soc15_common_early_init()
1039 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | in soc15_common_early_init()
1057 adev->pg_flags = 0; in soc15_common_early_init()
1058 adev->external_rev_id = adev->rev_id + 0x28; in soc15_common_early_init()
1062 adev->asic_funcs = &soc15_asic_funcs; in soc15_common_early_init()
1064 if (adev->rev_id >= 0x8) in soc15_common_early_init()
1065 adev->apu_flags |= AMD_APU_IS_RAVEN2; in soc15_common_early_init()
1067 if (adev->apu_flags & AMD_APU_IS_RAVEN2) in soc15_common_early_init()
1068 adev->external_rev_id = adev->rev_id + 0x79; in soc15_common_early_init()
1069 else if (adev->apu_flags & AMD_APU_IS_PICASSO) in soc15_common_early_init()
1070 adev->external_rev_id = adev->rev_id + 0x41; in soc15_common_early_init()
1071 else if (adev->rev_id == 1) in soc15_common_early_init()
1072 adev->external_rev_id = adev->rev_id + 0x20; in soc15_common_early_init()
1074 adev->external_rev_id = adev->rev_id + 0x01; in soc15_common_early_init()
1076 if (adev->apu_flags & AMD_APU_IS_RAVEN2) { in soc15_common_early_init()
1077 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | in soc15_common_early_init()
1092 adev->pg_flags = AMD_PG_SUPPORT_SDMA | AMD_PG_SUPPORT_VCN; in soc15_common_early_init()
1093 } else if (adev->apu_flags & AMD_APU_IS_PICASSO) { in soc15_common_early_init()
1094 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | in soc15_common_early_init()
1112 adev->pg_flags = AMD_PG_SUPPORT_SDMA | in soc15_common_early_init()
1115 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | in soc15_common_early_init()
1134 adev->pg_flags = AMD_PG_SUPPORT_SDMA | AMD_PG_SUPPORT_VCN; in soc15_common_early_init()
1138 adev->asic_funcs = &vega20_asic_funcs; in soc15_common_early_init()
1139 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | in soc15_common_early_init()
1153 adev->pg_flags = AMD_PG_SUPPORT_VCN | AMD_PG_SUPPORT_VCN_DPG; in soc15_common_early_init()
1154 adev->external_rev_id = adev->rev_id + 0x32; in soc15_common_early_init()
1157 adev->asic_funcs = &soc15_asic_funcs; in soc15_common_early_init()
1159 if (adev->apu_flags & AMD_APU_IS_RENOIR) in soc15_common_early_init()
1160 adev->external_rev_id = adev->rev_id + 0x91; in soc15_common_early_init()
1162 adev->external_rev_id = adev->rev_id + 0xa1; in soc15_common_early_init()
1163 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | in soc15_common_early_init()
1182 adev->pg_flags = AMD_PG_SUPPORT_SDMA | in soc15_common_early_init()
1188 adev->asic_funcs = &vega20_asic_funcs; in soc15_common_early_init()
1189 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG | in soc15_common_early_init()
1197 adev->pg_flags = AMD_PG_SUPPORT_VCN_DPG; in soc15_common_early_init()
1198 adev->external_rev_id = adev->rev_id + 0x3c; in soc15_common_early_init()
1203 adev->asic_funcs = &aqua_vanjaram_asic_funcs; in soc15_common_early_init()
1204 adev->cg_flags = in soc15_common_early_init()
1210 adev->pg_flags = in soc15_common_early_init()
1215 adev->external_rev_id = adev->rev_id + 0x46; in soc15_common_early_init()
1217 adev->external_rev_id = adev->rev_id + 0x50; in soc15_common_early_init()
1221 return -EINVAL; in soc15_common_early_init()
1234 struct amdgpu_device *adev = ip_block->adev; in soc15_common_late_init()
1242 adev->nbio.funcs->enable_doorbell_selfring_aperture(adev, true); in soc15_common_late_init()
1249 struct amdgpu_device *adev = ip_block->adev; in soc15_common_sw_init()
1254 if (adev->df.funcs && in soc15_common_sw_init()
1255 adev->df.funcs->sw_init) in soc15_common_sw_init()
1256 adev->df.funcs->sw_init(adev); in soc15_common_sw_init()
1263 struct amdgpu_device *adev = ip_block->adev; in soc15_common_sw_fini()
1265 if (adev->df.funcs && in soc15_common_sw_fini()
1266 adev->df.funcs->sw_fini) in soc15_common_sw_fini()
1267 adev->df.funcs->sw_fini(adev); in soc15_common_sw_fini()
1275 /* sdma doorbell range is programed by hypervisor */ in soc15_sdma_doorbell_range_init()
1277 for (i = 0; i < adev->sdma.num_instances; i++) { in soc15_sdma_doorbell_range_init()
1278 adev->nbio.funcs->sdma_doorbell_range(adev, i, in soc15_sdma_doorbell_range_init()
1279 true, adev->doorbell_index.sdma_engine[i] << 1, in soc15_sdma_doorbell_range_init()
1280 adev->doorbell_index.sdma_doorbell_range); in soc15_sdma_doorbell_range_init()
1287 struct amdgpu_device *adev = ip_block->adev; in soc15_common_hw_init()
1292 adev->nbio.funcs->init_registers(adev); in soc15_common_hw_init()
1293 /* remap HDP registers to a hole in mmio space, in soc15_common_hw_init()
1297 if (adev->nbio.funcs->remap_hdp_registers && !amdgpu_sriov_vf(adev)) in soc15_common_hw_init()
1298 adev->nbio.funcs->remap_hdp_registers(adev); in soc15_common_hw_init()
1301 adev->nbio.funcs->enable_doorbell_aperture(adev, true); in soc15_common_hw_init()
1304 * in SDMA/IH/MM/ACV range will be routed to CP. So in soc15_common_hw_init()
1305 * we need to init SDMA doorbell range prior in soc15_common_hw_init()
1316 struct amdgpu_device *adev = ip_block->adev; in soc15_common_hw_fini()
1323 adev->nbio.funcs->enable_doorbell_aperture(adev, false); in soc15_common_hw_fini()
1324 adev->nbio.funcs->enable_doorbell_selfring_aperture(adev, false); in soc15_common_hw_fini()
1334 (adev->init_lvl->level != AMDGPU_INIT_LEVEL_MINIMAL_XGMI) && in soc15_common_hw_fini()
1335 adev->nbio.ras_if && in soc15_common_hw_fini()
1336 amdgpu_ras_is_supported(adev, adev->nbio.ras_if->block)) { in soc15_common_hw_fini()
1337 if (adev->nbio.ras && in soc15_common_hw_fini()
1338 adev->nbio.ras->init_ras_controller_interrupt) in soc15_common_hw_fini()
1339 amdgpu_irq_put(adev, &adev->nbio.ras_controller_irq, 0); in soc15_common_hw_fini()
1340 if (adev->nbio.ras && in soc15_common_hw_fini()
1341 adev->nbio.ras->init_ras_err_event_athub_interrupt) in soc15_common_hw_fini()
1342 amdgpu_irq_put(adev, &adev->nbio.ras_err_event_athub_irq, 0); in soc15_common_hw_fini()
1355 struct amdgpu_device *adev = ip_block->adev; in soc15_common_resume()
1358 dev_info(adev->dev, "S3 suspend abort case, let's reset ASIC.\n"); in soc15_common_resume()
1375 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_DRM_MGCG)) in soc15_update_drm_clock_gating()
1404 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_DRM_LS)) in soc15_update_drm_light_sleep()
1416 struct amdgpu_device *adev = ip_block->adev; in soc15_common_set_clockgating_state()
1425 adev->nbio.funcs->update_medium_grain_clock_gating(adev, in soc15_common_set_clockgating_state()
1427 adev->nbio.funcs->update_medium_grain_light_sleep(adev, in soc15_common_set_clockgating_state()
1429 adev->hdp.funcs->update_clock_gating(adev, in soc15_common_set_clockgating_state()
1435 adev->smuio.funcs->update_rom_clock_gating(adev, in soc15_common_set_clockgating_state()
1437 adev->df.funcs->update_medium_grain_clock_gating(adev, in soc15_common_set_clockgating_state()
1443 adev->nbio.funcs->update_medium_grain_clock_gating(adev, in soc15_common_set_clockgating_state()
1445 adev->nbio.funcs->update_medium_grain_light_sleep(adev, in soc15_common_set_clockgating_state()
1447 adev->hdp.funcs->update_clock_gating(adev, in soc15_common_set_clockgating_state()
1456 adev->hdp.funcs->update_clock_gating(adev, in soc15_common_set_clockgating_state()
1467 struct amdgpu_device *adev = ip_block->adev; in soc15_common_get_clockgating_state()
1473 if (adev->nbio.funcs && adev->nbio.funcs->get_clockgating_state) in soc15_common_get_clockgating_state()
1474 adev->nbio.funcs->get_clockgating_state(adev, flags); in soc15_common_get_clockgating_state()
1476 if (adev->hdp.funcs && adev->hdp.funcs->get_clock_gating_state) in soc15_common_get_clockgating_state()
1477 adev->hdp.funcs->get_clock_gating_state(adev, flags); in soc15_common_get_clockgating_state()
1495 if (adev->smuio.funcs && adev->smuio.funcs->get_clock_gating_state) in soc15_common_get_clockgating_state()
1496 adev->smuio.funcs->get_clock_gating_state(adev, flags); in soc15_common_get_clockgating_state()
1498 if (adev->df.funcs && adev->df.funcs->get_clockgating_state) in soc15_common_get_clockgating_state()
1499 adev->df.funcs->get_clockgating_state(adev, flags); in soc15_common_get_clockgating_state()