Searched +full:sdfec +full:- +full:code (Results 1 – 2 of 2) sorted by relevance
| /freebsd/sys/contrib/device-tree/Bindings/misc/ |
| H A D | xlnx,sd-fec.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/misc/xlnx,sd-fec.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Xilinx SDFEC(16nm) IP
10 - Cvetic, Dragan <dragan.cvetic@amd.com>
11 - Erim, Salih <salih.erim@amd.com>
14 The Soft Decision Forward Error Correction (SDFEC) Engine is a Hard IP block
15 which provides high-throughput LDPC and Turbo Code implementations.
17 customer specified Quasi-cyclic (QC) codes. The Turbo decode functionality
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| H A D | xlnx,sd-fec.txt | 1 * Xilinx SDFEC(16nm) IP *
3 The Soft Decision Forward Error Correction (SDFEC) Engine is a Hard IP block
4 which provides high-throughput LDPC and Turbo Code implementations.
6 customer specified Quasi-cyclic (QC) codes. The Turbo decode functionality
12 - compatible: Must be "xlnx,sd-fec-1.1"
13 - clock-names : List of input clock names from the following:
14 - "core_clk", Main processing clock for processing core (required)
15 - "s_axi_aclk", AXI4-Lite memory-mapped slave interface clock (required)
16 - "s_axis_din_aclk", DIN AXI4-Stream Slave interface clock (optional)
17 - "s_axis_din_words-aclk", DIN_WORDS AXI4-Stream Slave interface clock (optional)
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