| /linux/drivers/mmc/host/ |
| H A D | sdhci-xenon-phy.c | 238 * 1. SDCLK frequency changes.
239 * 2. SDCLK is stopped and re-enabled.
490 * 2. SDCLK is higher than 52MHz in xenon_emmc_phy_strobe_delay_adj()
512 * If eMMC PHY Slow Mode is required in lower speed mode (SDCLK < 55MHz)
805 * PHY setting should be adjusted when SDCLK frequency, Bus Width
|
| H A D | uniphier-sd.c | 25 #define UNIPHIER_SD_CLKCTL_OFFEN BIT(9) // auto SDCLK stop
|
| H A D | sdhci.c | 2345 * Preset Values are: Driver Strength, Clock Generator and SDCLK/RCLK in sdhci_presetable_values_change()
|
| /linux/Documentation/devicetree/bindings/mmc/ |
| H A D | marvell,xenon-sdhci.yaml | 213 clocks = <&sdclk 0>, <&axi_clk 0>;
255 clocks = <&sdclk 0>;
|
| /linux/drivers/cpufreq/ |
| H A D | sa1110-cpufreq.c | 152 * If SDCLK would invalidate the SDRAM timings, in sdram_calculate_timing()
153 * run SDCLK at half speed. in sdram_calculate_timing()
|
| /linux/arch/arm64/boot/dts/socionext/ |
| H A D | uniphier-ld11.dtsi | 464 cdns,phy-dll-delay-sdclk = <21>;
465 cdns,phy-dll-delay-sdclk-hsmmc = <21>;
|
| /linux/drivers/clk/aspeed/ |
| H A D | clk-ast2700.c | 478 MUX_CLK(SCU1_CLK_SDMUX, "sdclk-mux", sdclk_parent_ids, ARRAY_SIZE(sdclk_parent_ids),
484 DIVIDER_CLK(SCU1_CLK_SDCLK, "sdclk", SCU1_CLK_SDMUX,
526 GATE_CLK(SCU1_CLK_GATE_SDCLK, CLK_GATE_ASPEED, "sdclk-gate", SCU1_CLK_SDCLK,
|
| H A D | clk-aspeed.c | 71 [ASPEED_CLK_GATE_SDCLK] = { 27, 16, "sdclk-gate", NULL, 0 }, /* SDIO/SD */
|
| H A D | clk-ast2600.c | 135 [ASPEED_CLK_GATE_SDCLK] = { 36, 56, "sdclk-gate", NULL, 0 }, /* SDIO/SD */
|
| /linux/drivers/pinctrl/uniphier/ |
| H A D | pinctrl-uniphier-nx1.c | 18 UNIPHIER_PINCTRL_PIN(1, "SDCLK", UNIPHIER_PIN_IECTRL_EXIST,
|
| H A D | pinctrl-uniphier-sld8.c | 111 UNIPHIER_PINCTRL_PIN(32, "SDCLK", 8,
|
| H A D | pinctrl-uniphier-ld4.c | 147 UNIPHIER_PINCTRL_PIN(44, "SDCLK", UNIPHIER_PIN_IECTRL_NONE,
|
| H A D | pinctrl-uniphier-ld6b.c | 156 UNIPHIER_PINCTRL_PIN(47, "SDCLK", UNIPHIER_PIN_IECTRL_NONE,
|
| H A D | pinctrl-uniphier-pro5.c | 765 UNIPHIER_PINCTRL_PIN(250, "SDCLK", UNIPHIER_PIN_IECTRL_NONE,
|
| H A D | pinctrl-uniphier-pxs2.c | 156 UNIPHIER_PINCTRL_PIN(47, "SDCLK", UNIPHIER_PIN_IECTRL_NONE,
|
| H A D | pinctrl-uniphier-pxs3.c | 144 UNIPHIER_PINCTRL_PIN(43, "SDCLK", UNIPHIER_PIN_IECTRL_EXIST,
|
| /linux/drivers/pinctrl/ |
| H A D | pinctrl-ep93xx.c | 129 PINCTRL_PIN(10, "SDCLK"),
437 PINCTRL_PIN(53, "SDCLK"), /* D3 */
858 PINCTRL_PIN(117, "SDCLK"), /* G4 */
|
| /linux/include/linux/mmc/ |
| H A D | host.h | 190 * switching might fail because the SDCLK is not really quiet.
|
| /linux/arch/m68k/include/asm/ |
| H A D | MC68VZ328.h | 591 #define PM_SDCLK 0x01 /* Use SDCLK as PM[0] */
|
| /linux/drivers/comedi/drivers/ |
| H A D | ni_mio_common.c | 3842 * Assert SDCLK (active low, inverted), wait for half of in ni_serial_sw_readwrite8()
3843 * the delay, deassert SDCLK, and wait for the other half. in ni_serial_sw_readwrite8()
|