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Searched full:sdclk (Results 1 – 18 of 18) sorted by relevance

/linux/Documentation/devicetree/bindings/mmc/
H A Dcdns,sdhci.yaml94 cdns,phy-dll-delay-sdclk:
96 Value of the delay introduced on the sdclk output for all modes except
102 cdns,phy-dll-delay-sdclk-hsmmc:
104 Value of the delay introduced on the sdclk output for HS200, HS400 and
157 cdns,phy-dll-delay-sdclk = <0>;
H A Dmarvell,xenon-sdhci.yaml213 clocks = <&sdclk 0>, <&axi_clk 0>;
255 clocks = <&sdclk 0>;
/linux/drivers/mmc/host/
H A Dsdhci-xenon-phy.c238 * 1. SDCLK frequency changes.
239 * 2. SDCLK is stopped and re-enabled.
490 * 2. SDCLK is higher than 52MHz in xenon_emmc_phy_strobe_delay_adj()
512 * If eMMC PHY Slow Mode is required in lower speed mode (SDCLK < 55MHz)
805 * PHY setting should be adjusted when SDCLK frequency, Bus Width
H A Dsdhci-of-aspeed.c261 * period of SDCLK = period of SDMCLK. in aspeed_sdhci_set_clock()
264 * period of SDCLK = period of SDMCLK * 2 * (EMMC12C[7:6], EMMC[15:8]) in aspeed_sdhci_set_clock()
538 dev_err(&pdev->dev, "Unable to enable SDCLK\n"); in aspeed_sdc_probe()
H A Duniphier-sd.c25 #define UNIPHIER_SD_CLKCTL_OFFEN BIT(9) // auto SDCLK stop
/linux/drivers/cpufreq/
H A Dsa1110-cpufreq.c152 * If SDCLK would invalidate the SDRAM timings, in sdram_calculate_timing()
153 * run SDCLK at half speed. in sdram_calculate_timing()
/linux/arch/arm64/boot/dts/socionext/
H A Duniphier-ld11.dtsi464 cdns,phy-dll-delay-sdclk = <21>;
465 cdns,phy-dll-delay-sdclk-hsmmc = <21>;
/linux/drivers/pinctrl/uniphier/
H A Dpinctrl-uniphier-nx1.c18 UNIPHIER_PINCTRL_PIN(1, "SDCLK", UNIPHIER_PIN_IECTRL_EXIST,
H A Dpinctrl-uniphier-sld8.c111 UNIPHIER_PINCTRL_PIN(32, "SDCLK", 8,
H A Dpinctrl-uniphier-ld4.c147 UNIPHIER_PINCTRL_PIN(44, "SDCLK", UNIPHIER_PIN_IECTRL_NONE,
H A Dpinctrl-uniphier-ld6b.c156 UNIPHIER_PINCTRL_PIN(47, "SDCLK", UNIPHIER_PIN_IECTRL_NONE,
H A Dpinctrl-uniphier-pro5.c765 UNIPHIER_PINCTRL_PIN(250, "SDCLK", UNIPHIER_PIN_IECTRL_NONE,
H A Dpinctrl-uniphier-pxs2.c156 UNIPHIER_PINCTRL_PIN(47, "SDCLK", UNIPHIER_PIN_IECTRL_NONE,
H A Dpinctrl-uniphier-pxs3.c144 UNIPHIER_PINCTRL_PIN(43, "SDCLK", UNIPHIER_PIN_IECTRL_EXIST,
/linux/drivers/pinctrl/
H A Dpinctrl-ep93xx.c129 PINCTRL_PIN(10, "SDCLK"),
437 PINCTRL_PIN(53, "SDCLK"), /* D3 */
858 PINCTRL_PIN(117, "SDCLK"), /* G4 */
/linux/drivers/clk/
H A Dclk-aspeed.c71 [ASPEED_CLK_GATE_SDCLK] = { 27, 16, "sdclk-gate", NULL, 0 }, /* SDIO/SD */
/linux/arch/m68k/include/asm/
H A DMC68VZ328.h591 #define PM_SDCLK 0x01 /* Use SDCLK as PM[0] */
/linux/drivers/comedi/drivers/
H A Dni_mio_common.c3842 * Assert SDCLK (active low, inverted), wait for half of in ni_serial_sw_readwrite8()
3843 * the delay, deassert SDCLK, and wait for the other half. in ni_serial_sw_readwrite8()