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/linux/net/netfilter/ipvs/
H A Dip_vs_proto_sctp.c285 #define sCL IP_VS_SCTP_S_CLOSED macro
290 /* sNO, sI1, sIN, sCS, sCR, sCW, sCO, sCE, sES, sSS, sSR, sSA, sRJ, sCL*/
291 /* d */{sES, sI1, sIN, sCS, sCR, sCW, sCO, sCE, sES, sSS, sSR, sSA, sRJ, sCL},
293 /* i_a */{sCW, sCW, sCW, sCS, sCR, sCO, sCO, sCE, sES, sSS, sSR, sSA, sRJ, sCL},
294 /* c_e */{sCR, sIN, sIN, sCR, sCR, sCW, sCO, sCE, sES, sSS, sSR, sSA, sRJ, sCL},
295 /* c_a */{sES, sI1, sIN, sCS, sCR, sCW, sCO, sES, sES, sSS, sSR, sSA, sRJ, sCL},
296 /* s */{sSR, sI1, sIN, sCS, sCR, sCW, sCO, sCE, sSR, sSS, sSR, sSA, sRJ, sCL},
297 /* s_a */{sCL, sIN, sIN, sCS, sCR, sCW, sCO, sCE, sES, sCL, sSR, sCL, sRJ, sCL},
298 /* s_c */{sCL, sCL, sCL, sCS, sCR, sCW, sCO, sCE, sES, sSS, sSR, sCL, sRJ, sCL},
299 /* err */{sCL, sI1, sIN, sCS, sCR, sCW, sCO, sCL, sES, sSS, sSR, sSA, sRJ, sCL},
[all …]
H A Dip_vs_proto_tcp.c415 #define sCL IP_VS_TCP_S_CLOSE macro
441 /* sNO, sES, sSS, sSR, sFW, sTW, sCL, sCW, sLA, sLI, sSA */
443 /*fin*/ {{sCL, sCW, sSS, sTW, sTW, sTW, sCL, sCW, sLA, sLI, sTW }},
444 /*ack*/ {{sES, sES, sSS, sES, sFW, sTW, sCL, sCW, sCL, sLI, sES }},
445 /*rst*/ {{sCL, sCL, sCL, sSR, sCL, sCL, sCL, sCL, sLA, sLI, sSR }},
448 /* sNO, sES, sSS, sSR, sFW, sTW, sCL, sCW, sLA, sLI, sSA */
450 /*fin*/ {{sTW, sFW, sSS, sTW, sFW, sTW, sCL, sTW, sLA, sLI, sTW }},
451 /*ack*/ {{sES, sES, sSS, sES, sFW, sTW, sCL, sCW, sLA, sES, sES }},
452 /*rst*/ {{sCL, sCL, sSS, sCL, sCL, sTW, sCL, sCL, sCL, sCL, sCL }},
455 /* sNO, sES, sSS, sSR, sFW, sTW, sCL, sCW, sLA, sLI, sSA */
[all …]
/linux/net/netfilter/
H A Dnf_conntrack_proto_sctp.c61 #define sCL SCTP_CONNTRACK_CLOSED macro
107 /* sNO, sCL, sCW, sCE, sES, sSS, sSR, sSA, sHS */
108 /* init */ {sCL, sCL, sCW, sCE, sES, sCL, sCL, sSA, sCW},
109 /* init_ack */ {sCL, sCL, sCW, sCE, sES, sSS, sSR, sSA, sCL},
110 /* abort */ {sCL, sCL, sCL, sCL, sCL, sCL, sCL, sCL, sCL},
111 /* shutdown */ {sCL, sCL, sCW, sCE, sSS, sSS, sSR, sSA, sCL},
112 /* shutdown_ack */ {sSA, sCL, sCW, sCE, sES, sSA, sSA, sSA, sSA},
113 /* error */ {sCL, sCL, sCW, sCE, sES, sSS, sSR, sSA, sCL},/* Can't have Stale cookie*/
114 /* cookie_echo */ {sCL, sCL, sCE, sCE, sES, sSS, sSR, sSA, sCL},/* 5.2.4 - Big TODO */
115 /* cookie_ack */ {sCL, sCL, sCW, sES, sES, sSS, sSR, sSA, sCL},/* Can't come in orig dir */
[all …]
H A Dnf_conntrack_proto_tcp.c86 #define sCL TCP_CONNTRACK_CLOSE macro
137 /* sNO, sSS, sSR, sES, sFW, sCW, sLA, sTW, sCL, sS2 */
152 * sCL -> sSS
154 /* sNO, sSS, sSR, sES, sFW, sCW, sLA, sTW, sCL, sS2 */
166 * sCL -> sIV
168 /* sNO, sSS, sSR, sES, sFW, sCW, sLA, sTW, sCL, sS2 */
169 /*fin*/ { sIV, sIV, sFW, sFW, sLA, sLA, sLA, sTW, sCL, sIV },
183 * sCL -> sCL
185 /* sNO, sSS, sSR, sES, sFW, sCW, sLA, sTW, sCL, sS2 */
186 /*ack*/ { sES, sIV, sES, sES, sCW, sCW, sTW, sTW, sCL, sIV },
[all …]
/linux/Documentation/devicetree/bindings/i2c/
H A Di2c-gpio.yaml28 scl-gpios:
30 gpio used for the scl signal, this should be flagged as
40 i2c-gpio,scl-output-only:
41 description: scl as output only
54 description: sda and scl gpio, alternative for {sda,scl}-gpios
63 i2c-gpio,scl-open-drain:
67 GPIO line used for SCL into open drain mode, and that something is not
76 i2c-gpio,scl-has-no-pullup:
78 description: scl is used in a non-compliant way and has no pull-up.
80 with i2c-gpio,scl-open-drain.
[all …]
H A Di2c-rk3x.yaml81 SCL frequency to use (in Hz). If omitted, 100kHz is used.
83 i2c-scl-rising-time-ns:
86 Number of nanoseconds the SCL signal takes to rise
91 i2c-scl-falling-time-ns:
94 Number of nanoseconds the SCL signal takes to fall
103 (t(f) in the I2C specification). If not specified we will use the SCL
139 i2c-scl-falling-time-ns = <100>;
140 i2c-scl-rising-time-ns = <800>;
H A Drenesas,rcar-i2c.yaml94 i2c-scl-falling-time-ns:
97 Number of nanoseconds the SCL signal takes to fall; t(f) in the I2C
100 i2c-scl-internal-delay-ns:
103 Number of nanoseconds the IP core additionally needs to setup SCL.
105 i2c-scl-rising-time-ns:
108 Number of nanoseconds the SCL signal takes to rise; t(r) in the I2C
163 i2c-scl-internal-delay-ns = <6>;
H A Dhisilicon,ascend910-i2c.yaml38 i2c-scl-falling-time-ns:
44 i2c-scl-rising-time-ns:
66 i2c-scl-falling-time-ns = <56>;
68 i2c-scl-rising-time-ns = <56>;
/linux/drivers/gpu/drm/amd/display/dc/dce/
H A Ddce_transform.h76 SRI(SCL_MODE, SCL, id), \
77 SRI(SCL_TAP_CONTROL, SCL, id), \
78 SRI(SCL_CONTROL, SCL, id), \
79 SRI(SCL_BYPASS_CONTROL, SCL, id), \
80 SRI(EXT_OVERSCAN_LEFT_RIGHT, SCL, id), \
81 SRI(EXT_OVERSCAN_TOP_BOTTOM, SCL, id), \
82 SRI(SCL_VERT_FILTER_CONTROL, SCL, id), \
83 SRI(SCL_HORZ_FILTER_CONTROL, SCL, id), \
84 SRI(SCL_COEF_RAM_SELECT, SCL, id), \
85 SRI(SCL_COEF_RAM_TAP_DATA, SCL, id), \
[all …]
H A Ddce_i2c_sw.c29 #define SCL false macro
85 if (read_bit_from_ddc(ddc, SCL)) in wait_for_scl_high_sw()
113 write_bit_to_ddc(ddc_handle, SCL, true); in write_byte_sw()
118 write_bit_to_ddc(ddc_handle, SCL, false); in write_byte_sw()
124 * after the SCL pulse we use to send our last data bit. in write_byte_sw()
134 write_bit_to_ddc(ddc_handle, SCL, true); in write_byte_sw()
145 write_bit_to_ddc(ddc_handle, SCL, false); in write_byte_sw()
164 * bit is read while SCL is high in read_byte_sw()
168 write_bit_to_ddc(ddc_handle, SCL, true); in read_byte_sw()
176 write_bit_to_ddc(ddc_handle, SCL, false); in read_byte_sw()
[all …]
/linux/drivers/staging/sm750fb/
H A Dddk750_swi2c.c19 * a point in time where the SCL or SDA may be changed.
23 * | SCL set LOW |SCL no change| SCL set HIGH|SCL no change|
26 * SCL == XXXX _____________ ____________ /
28 * I.e. the SCL may only be changed in section 1. and section 3. while
39 * SCL | L | | H | |
42 * SCL | L | | H | |
45 * SCL | L | | H | |
48 * SCL | L | | H | |
104 * This function set/reset the SCL GPIO pin
107 * value - Bit value to set to the SCL or SDA (0 = low, 1 = high)
[all …]
/linux/drivers/i2c/busses/
H A Di2c-acorn.c19 #define SCL 0x02 macro
24 * Note also that we need to preserve the value of SCL and
32 u_int ioc_control = ioc_readb(IOC_CONTROL) & ~(SCL | SDA); in ioc_setscl()
36 ones |= SCL; in ioc_setscl()
38 ones &= ~SCL; in ioc_setscl()
47 u_int ioc_control = ioc_readb(IOC_CONTROL) & ~(SCL | SDA); in ioc_setsda()
62 return (ioc_readb(IOC_CONTROL) & SCL) != 0; in ioc_getscl()
87 force_ones = FORCE_ONES | SCL | SDA; in i2c_ioc_init()
H A Di2c-rcar.c45 #define ICMPR 0x2C /* SCL mask control */
46 #define ICHPR 0x30 /* SCL HIGH control */
47 #define ICLPR 0x34 /* SCL LOW control */
59 #define FSCL BIT(6) /* override SCL pin */
95 #define SME BIT(0) /* SCL Mask Enable */
98 #define TCYC17 0x0f /* 17*Tcyc delay 1st bit between SDA and SCL */
102 /* SCL low/high ratio 5:4 to meet all I2C timing specs (incl safety margin) */
285 u32 cdf, round, ick, sum, scl, cdf_width; in rcar_i2c_clock_calculate() local
300 * calculate SCL clock in rcar_i2c_clock_calculate()
305 * SCL = ick / (20 + SCGD * 8 + F[(ticf + tr + intd) * ick]) in rcar_i2c_clock_calculate()
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H A Di2c-omap.c139 /* I2C SCL time value when Master */
149 #define OMAP_I2C_SYSTEST_SCL_I_FUNC (1 << 8) /* SCL line input value */
150 #define OMAP_I2C_SYSTEST_SCL_O_FUNC (1 << 7) /* SCL line output value */
153 /* SDA/SCL IO mode */
154 #define OMAP_I2C_SYSTEST_SCL_I (1 << 3) /* SCL line sense in */
155 #define OMAP_I2C_SYSTEST_SCL_O (1 << 2) /* SCL line drive out */
286 /* SCL low and high time values */ in __omap_i2c_init()
429 unsigned long scl; in omap_i2c_init() local
432 scl = internal_clk / 400; in omap_i2c_init()
433 fsscll = scl - (scl / 3) - 7; in omap_i2c_init()
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/linux/arch/arm/boot/dts/st/
H A Dstih407-pinctrl.dtsi164 scl = <&pio4 5 ALT1 BIDIR>;
173 scl = <&pio5 0 ALT1 BIDIR>;
322 scl = <&pio4 5 ALT1 OUT>;
329 scl = <&pio4 5 ALT1 OUT>;
339 scl = <&pio3 2 ALT2 OUT>;
346 scl = <&pio3 2 ALT2 OUT>;
356 scl = <&pio3 7 ALT2 OUT>;
363 scl = <&pio3 7 ALT2 OUT>;
519 scl = <&pio10 5 ALT2 BIDIR>;
528 scl = <&pio11 0 ALT2 BIDIR>;
[all …]
/linux/Documentation/i2c/
H A Dgpio-fault-injection.rst20 "scl"
23 By reading this file, you get the current state of SCL. By writing, you can
25 "echo 0 > scl" you force SCL low and thus, no communication will be possible
27 the condition of SCL being unresponsive and report an error to the upper
62 being pulled low by the device while SCL is high. So, similar to the "sda" file
65 SDA after toggling SCL.
81 register 0x00 (if it has registers) when further clock pulses happen on SCL.
99 Arbitration lost is achieved by waiting for SCL going down by the master under
104 should be detected beforehand. Also note, that SCL going down is monitored
129 Start of a transfer is detected by waiting for SCL going down by the master
/linux/include/linux/platform_data/
H A Di2c-gpio.h12 * @udelay: signal toggle delay. SCL frequency is (500 / udelay) kHz
14 * SCL low for longer than this, the transfer will time out.
20 * This is for clients that can only read SDA/SCL.
23 * @scl_is_open_drain: SCL is set up as open drain. Same requirements
25 * @scl_is_output_only: SCL output drivers cannot be turned off.
26 * @scl_has_no_pullup: SCL is used in a non-compliant way and has no pull-up.
/linux/drivers/i2c/algos/
H A Di2c-algo-bit.c72 * Raise scl line, and do checking for delays. This is necessary for slower
81 /* Not all adapters have scl sense line... */ in sclhi()
104 pr_debug("i2c-algo-bit: needed %ld jiffies for SCL to go high\n", in sclhi()
117 /* assert: scl, sda are high */ in i2c_start()
125 /* assert: scl is low */ in i2c_repstart()
136 /* assert: scl is low */ in i2c_stop()
150 * -ETIMEDOUT if an error occurred (while raising the scl line)
159 /* assert: scl is low */ in i2c_outb()
195 /* assert: scl is low (sda undef) */ in i2c_outb()
207 /* assert: scl is low */ in i2c_inb()
[all …]
/linux/drivers/rtc/
H A Drtc-rs5c313.c73 #define SCL SCSPTR1_SPB0DT macro
94 /* And Initialize SCL for RS5C313 clock */ in rs5c313_init_port()
95 scsptr1_data = __raw_readb(SCSPTR1) | SCL; /* SCL:H */ in rs5c313_init_port()
97 scsptr1_data = __raw_readb(SCSPTR1) | SCL_OEN; /* SCL output enable */ in rs5c313_init_port()
116 scsptr1_data &= ~SCL; /* SCL:L */ in rs5c313_write_data()
119 scsptr1_data |= SCL; /* SCL:H */ in rs5c313_write_data()
136 scsptr1_data &= ~SCL; /* SCL:L */ in rs5c313_read_data()
139 scsptr1_data |= SCL; /* SCL:H */ in rs5c313_read_data()
/linux/drivers/gpu/drm/loongson/
H A Dlsdc_i2c.c83 /* set state on the li2c->scl pin */ in lsdc_gpio_i2c_set_scl()
84 return __lsdc_gpio_i2c_set(li2c, li2c->scl, state); in lsdc_gpio_i2c_set_scl()
97 /* read the value from the li2c->scl pin */ in lsdc_gpio_i2c_get_scl()
98 return __lsdc_gpio_i2c_get(li2c, li2c->scl); in lsdc_gpio_i2c_get_scl()
134 li2c->scl = 0x02; /* pin 1 */ in lsdc_create_i2c_chan()
137 li2c->scl = 0x08; /* pin 3 */ in lsdc_create_i2c_chan()
174 drm_info(ddev, "%s(sda pin mask=%u, scl pin mask=%u) created\n", in lsdc_create_i2c_chan()
175 adapter->name, li2c->sda, li2c->scl); in lsdc_create_i2c_chan()
/linux/drivers/gpu/drm/imx/dcss/
H A Ddcss-dev.h166 void dcss_scaler_exit(struct dcss_scaler *scl);
167 void dcss_scaler_set_filter(struct dcss_scaler *scl, int ch_num,
169 void dcss_scaler_setup(struct dcss_scaler *scl, int ch_num,
173 void dcss_scaler_ch_enable(struct dcss_scaler *scl, int ch_num, bool en);
174 int dcss_scaler_get_min_max_ratios(struct dcss_scaler *scl, int ch_num,
176 void dcss_scaler_write_sclctrl(struct dcss_scaler *scl);
/linux/Documentation/devicetree/bindings/i3c/
H A Di3c.yaml42 i3c-scl-hz:
44 Frequency of the SCL signal used for I3C transfers. When undefined, the
49 i2c-scl-hz:
51 Frequency of the SCL signal used for I2C transfers. When undefined, the
99 supports high frequency on SCL
167 i2c-scl-hz = <100000>;
/linux/drivers/gpu/drm/amd/pm/powerplay/hwmgr/
H A Dvega10_processpptables.c375 static void get_scl_sda_value(uint8_t line, uint8_t *scl, uint8_t *sda) in get_scl_sda_value() argument
379 *scl = Vega10_I2C_DDC1CLK; in get_scl_sda_value()
383 *scl = Vega10_I2C_DDC2CLK; in get_scl_sda_value()
387 *scl = Vega10_I2C_DDC3CLK; in get_scl_sda_value()
391 *scl = Vega10_I2C_DDC4CLK; in get_scl_sda_value()
395 *scl = Vega10_I2C_DDC5CLK; in get_scl_sda_value()
399 *scl = Vega10_I2C_DDC6CLK; in get_scl_sda_value()
403 *scl = Vega10_I2C_SCL; in get_scl_sda_value()
407 *scl = Vega10_I2C_DDCVGACLK; in get_scl_sda_value()
411 *scl = 0; in get_scl_sda_value()
[all …]
/linux/drivers/media/pci/ivtv/
H A Divtv-i2c.c20 when putting out bits on the scl/sda lines. The general strategy taken
23 which poll the SCL line 5 times (ivtv_scldelay). I would guess that
35 The i2c bus is a 2 wire serial bus, with clock (SCL) and data (SDA)
388 IVTV_DEBUG_HI_I2C("SCL was high starting an ack\n"); in ivtv_ack()
391 IVTV_DEBUG_I2C("Could not set SCL low starting an ack\n"); in ivtv_ack()
404 IVTV_DEBUG_I2C("Failed to set SCL low after ACK\n"); in ivtv_ack()
419 IVTV_DEBUG_I2C("Error setting SCL low\n"); in ivtv_sendbyte()
436 IVTV_DEBUG_I2C("Error setting SCL low\n"); in ivtv_sendbyte()
457 IVTV_DEBUG_I2C("Error setting SCL high\n"); in ivtv_readbyte()
492 IVTV_DEBUG_I2C("SCL stuck low at start\n"); in ivtv_start()
[all …]
/linux/include/linux/
H A Di2c-algo-pca.h36 #define I2C_PCA_ISCLL 0x02 /* SCL LOW period */
37 #define I2C_PCA_ISCLH 0x03 /* SCL HIGH period */
59 * @tlow: Configured SCL LOW period
60 * @thi: Configured SCL HIGH period

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