Lines Matching full:scl
20 when putting out bits on the scl/sda lines. The general strategy taken
23 which poll the SCL line 5 times (ivtv_scldelay). I would guess that
35 The i2c bus is a 2 wire serial bus, with clock (SCL) and data (SDA)
388 IVTV_DEBUG_HI_I2C("SCL was high starting an ack\n"); in ivtv_ack()
391 IVTV_DEBUG_I2C("Could not set SCL low starting an ack\n"); in ivtv_ack()
404 IVTV_DEBUG_I2C("Failed to set SCL low after ACK\n"); in ivtv_ack()
419 IVTV_DEBUG_I2C("Error setting SCL low\n"); in ivtv_sendbyte()
436 IVTV_DEBUG_I2C("Error setting SCL low\n"); in ivtv_sendbyte()
457 IVTV_DEBUG_I2C("Error setting SCL high\n"); in ivtv_readbyte()
492 IVTV_DEBUG_I2C("SCL stuck low at start\n"); in ivtv_start()
507 IVTV_DEBUG_HI_I2C("SCL not low when stopping\n"); in ivtv_stop()
510 IVTV_DEBUG_I2C("SCL could not be set low\n"); in ivtv_stop()
517 IVTV_DEBUG_I2C("SCL could not be set high\n"); in ivtv_stop()
722 IVTV_DEBUG_I2C("setting scl and sda to 1\n"); in init_ivtv_i2c()