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/linux/Documentation/devicetree/bindings/phy/
H A Dbrcm,sata-phy.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/phy/brcm,sata-phy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Broadcom SATA3 PHY
10 - Florian Fainelli <f.fainelli@gmail.com>
14 pattern: "^sata[-|_]phy(@.*)?$"
18 - items:
19 - enum:
20 - brcm,bcm7216-sata-phy
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H A Dmarvell,berlin2-sata-phy.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/phy/marvell,berlin2-sata-phy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Marvell Berlin SATA PHY
10 - Antoine Tenart <atenart@kernel.org>
15 - marvell,berlin2-sata-phy
16 - marvell,berlin2q-sata-phy
24 '#address-cells':
27 '#size-cells':
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H A Dqcom,sata-phy.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/phy/qcom,sata-phy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm SATA PHY Controller
10 - Bjorn Andersson <andersson@kernel.org>
11 - Konrad Dybcio <konrad.dybcio@linaro.org>
14 The Qualcomm SATA PHY describes on-chip SATA Physical layer controllers.
19 - qcom,ipq806x-sata-phy
20 - qcom,apq8064-sata-phy
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H A Dphy-miphy365x.txt1 STMicroelectronics STi MIPHY365x PHY binding
4 This binding describes a miphy device that is used to control PHY hardware
5 for SATA and PCIe.
8 - compatible : Should be "st,miphy365x-phy"
9 - st,syscfg : Phandle / integer array property. Phandle of sysconfig group
11 an entry for each port sub-node, specifying the control
14 Required nodes : A sub-node is required for each channel the controller
16 'reg' and 'reg-names' properties are used inside these
21 - #phy-cells : Should be 1 (See second example)
23 - PHY_TYPE_SATA
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H A Dmarvell,mvebu-sata-phy.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/phy/marvell,mvebu-sata-phy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Marvell MVEBU SATA PHY
10 - Andrew Lunn <andrew@lunn.ch>
11 - Gregory Clement <gregory.clement@bootlin.com>
15 const: marvell,mvebu-sata-phy
23 clock-names:
25 - const: sata
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H A Dhisilicon,hix5hd2-sata-phy.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/phy/hisilicon,hix5hd2-sata-phy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: HiSilicon hix5hd2 SATA PHY
10 - Jiancheng Xue <xuejiancheng@huawei.com>
14 const: hisilicon,hix5hd2-sata-phy
19 '#phy-cells':
22 hisilicon,peripheral-syscon:
26 hisilicon,power-reg:
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H A Dfsl,imx8qm-hsio.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/phy/fsl,imx8qm-hsio.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Freescale i.MX8QM SoC series High Speed IO(HSIO) SERDES PHY
10 - Richard Zhu <hongxing.zhu@nxp.com>
15 - fsl,imx8qm-hsio
16 - fsl,imx8qxp-hsio
19 - description: Base address and length of the PHY block
20 - description: HSIO control and status registers(CSR) of the PHY
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H A Dphy-miphy28lp.txt1 STMicroelectronics STi MIPHY28LP PHY binding
4 This binding describes a miphy device that is used to control PHY hardware
5 for SATA, PCIe or USB3.
8 - compatible : Should be "st,miphy28lp-phy".
9 - st,syscfg : Should be a phandle of the system configuration register group
10 which contain the SATA, PCIe or USB3 mode setting bits.
12 Required nodes : A sub-node is required for each channel the controller
14 'reg' and 'reg-names' properties are used inside these
19 - #phy-cells : Should be 1 (See second example)
21 - PHY_TYPE_SATA
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H A Dsamsung,exynos5250-sata-phy.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/phy/samsung,exynos5250-sata-phy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Samsung Exynos5250 SoC SATA PHY
10 - Krzysztof Kozlowski <krzk@kernel.org>
11 - Marek Szyprowski <m.szyprowski@samsung.com>
12 - Sylwester Nawrocki <s.nawrocki@samsung.com>
16 const: samsung,exynos5250-sata-phy
21 clock-names:
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H A Dcalxeda-combophy.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/phy/calxeda-combophy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Calxeda Highbank Combination PHYs for SATA
11 and to SATA connectors. The PHYs support multiple protocols (SATA,
12 SGMII, PCIe) and can be assigned to different devices (SATA or XGMAC
15 not by a dedicated PHY driver.
18 - Andre Przywara <andre.przywara@arm.com>
22 const: calxeda,hb-combophy
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/linux/drivers/phy/st/
H A Dphy-spear1340-miphy.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * ST spear1340-miphy driver
12 #include <linux/dma-mapping.h>
17 #include <linux/phy/phy.h>
33 /* PCIE - SATA configuration registers */
76 SATA, enumerator
81 /* phy mode: 0 for SATA 1 for PCIe */
85 /* phy struct pointer */
86 struct phy *phy; member
91 regmap_update_bits(priv->misc, SPEAR1340_PCIE_SATA_CFG, in spear1340_miphy_sata_init()
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/linux/Documentation/devicetree/bindings/ata/
H A Dahci-common.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/ata/ahci-common.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Hans de Goede <hdegoede@redhat.com>
11 - Damien Le Moal <dlemoal@kernel.org>
14 This document defines device tree properties for a common AHCI SATA
18 document doesn't constitute a DT-node binding by itself but merely
19 defines a set of common properties for the AHCI-compatible devices.
24 - $ref: sata-common.yaml#
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H A Dimx-sata.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/ata/imx-sata.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Freescale i.MX AHCI SATA Controller
10 - Shawn Guo <shawn.guo@linaro.org>
13 The Freescale i.MX SATA controller mostly conforms to the AHCI interface
19 - fsl,imx53-ahci
20 - fsl,imx6q-ahci
21 - fsl,imx6qp-ahci
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H A Dnvidia,tegra-ahci.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/ata/nvidia,tegra-ahci.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Tegra AHCI SATA Controller
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Jonathan Hunter <jonathanh@nvidia.com>
16 - nvidia,tegra124-ahci
17 - nvidia,tegra132-ahci
18 - nvidia,tegra210-ahci
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/linux/drivers/phy/samsung/
H A DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
3 # Phy drivers for Samsung platforms
6 tristate "Exynos SoC series Display Port PHY driver"
12 Support for Display Port PHY found on Samsung Exynos SoCs.
15 tristate "S5P/Exynos SoC series MIPI CSI-2/DSI PHY driver"
21 Support for MIPI CSI-2 and MIPI DSI DPHY found on Samsung S5P
25 bool "Exynos PCIe PHY driver"
29 Enable PCIe PHY support for Exynos SoC series.
30 This driver provides PHY interface for Exynos PCIe controller.
33 tristate "Exynos SoC series UFS PHY driver"
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/linux/drivers/phy/marvell/
H A Dphy-mvebu-sata.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * phy-mvebu-sata.c: SATA Phy driver for the Marvell mvebu SoCs.
11 #include <linux/phy/phy.h>
29 static int phy_mvebu_sata_power_on(struct phy *phy) in phy_mvebu_sata_power_on() argument
31 struct priv *priv = phy_get_drvdata(phy); in phy_mvebu_sata_power_on()
34 clk_prepare_enable(priv->clk); in phy_mvebu_sata_power_on()
37 reg = readl(priv->base + SATA_PHY_MODE_2); in phy_mvebu_sata_power_on()
40 writel(reg , priv->base + SATA_PHY_MODE_2); in phy_mvebu_sata_power_on()
42 /* Enable PHY */ in phy_mvebu_sata_power_on()
43 reg = readl(priv->base + SATA_IF_CTRL); in phy_mvebu_sata_power_on()
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H A DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
3 # Phy drivers for Marvell platforms
6 bool "Armada 375 USB cluster PHY support" if COMPILE_TEST
12 tristate "Marvell Berlin SATA PHY driver"
17 Enable this to support the SATA PHY on Marvell Berlin SoCs.
20 tristate "Marvell Berlin USB PHY Driver"
25 Enable this to support the USB PHY on Marvell Berlin SoCs.
37 used by various controllers: Ethernet, SATA, USB3, PCIe.
46 Enable this to support Marvell A3700 UTMI PHY driver.
56 used by various controllers (Ethernet, sata, usb, PCIe...).
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H A Dphy-berlin-sata.c1 // SPDX-License-Identifier: GPL-2.0
3 * Marvell Berlin SATA PHY driver
7 * Antoine Ténart <antoine.tenart@free-electrons.com>
13 #include <linux/phy/phy.h>
52 struct phy *phy; member
81 static int phy_berlin_sata_power_on(struct phy *phy) in phy_berlin_sata_power_on() argument
83 struct phy_berlin_desc *desc = phy_get_drvdata(phy); in phy_berlin_sata_power_on()
84 struct phy_berlin_priv *priv = dev_get_drvdata(phy->dev.parent); in phy_berlin_sata_power_on()
85 void __iomem *ctrl_reg = priv->base + 0x60 + (desc->index * 0x80); in phy_berlin_sata_power_on()
88 clk_prepare_enable(priv->clk); in phy_berlin_sata_power_on()
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/linux/drivers/phy/tegra/
H A Dxusb-tegra124.c1 // SPDX-License-Identifier: GPL-2.0-only
11 #include <linux/phy/phy.h>
229 mutex_lock(&padctl->lock); in tegra124_xusb_padctl_enable()
231 if (padctl->enable++ > 0) in tegra124_xusb_padctl_enable()
251 mutex_unlock(&padctl->lock); in tegra124_xusb_padctl_enable()
259 mutex_lock(&padctl->lock); in tegra124_xusb_padctl_disable()
261 if (WARN_ON(padctl->enable == 0)) in tegra124_xusb_padctl_disable()
264 if (--padctl->enable > 0) in tegra124_xusb_padctl_disable()
284 mutex_unlock(&padctl->lock); in tegra124_xusb_padctl_disable()
297 return -ENODEV; in tegra124_usb3_save_context()
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/linux/drivers/scsi/mvsas/
H A Dmv_defs.h1 /* SPDX-License-Identifier: GPL-2.0-only */
7 * Copyright 2009-2011 Marvell. <yuxiangl@marvell.com>
28 /* driver compile-time configuration */
30 MVS_TX_RING_SZ = 1024, /* TX ring size (12-bit) */
31 MVS_RX_RING_SZ = 1024, /* RX ring size (12-bit) */
32 /* software requires power-of-2
40 MVS_ATA_CMD_SZ = 96, /* SATA command table buffer size */
44 MVS_SOC_CAN_QUEUE = MVS_SOC_SLOTS - 2,
77 INT_SAS_SATA = (1U << 0), /* SAS/SATA event */
79 /* MVS_GBL_PORT_TYPE */ /* shl for ports 1-3 */
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/linux/Documentation/devicetree/bindings/pinctrl/
H A Dnvidia,tegra124-xusb-padctl.txt6 required for PCIe and SATA, it lacks the flexibility to represent the features
7 needed for USB. For the new binding, see ../phy/nvidia,tegra-xusb-padctl.txt.
12 associated PHY that must be powered up before the pad can be used.
14 This document defines the device-specific binding for the XUSB pad controller.
16 Refer to pinctrl-bindings.txt in this directory for generic information about
17 pin controller device tree bindings and ../phy/phy-bindings.txt for details on
21 --------------------
22 - compatible: For Tegra124, must contain "nvidia,tegra124-xusb-padctl".
23 Otherwise, must contain '"nvidia,<chip>-xusb-padctl",
24 "nvidia-tegra124-xusb-padctl"', where <chip> is tegra132 or tegra210.
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/linux/drivers/scsi/isci/
H A Dphy.h7 * Copyright(c) 2008 - 2011 Intel Corporation. All rights reserved.
20 * Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
26 * Copyright(c) 2008 - 2011 Intel Corporation. All rights reserved.
63 /* This is the timeout value for the SATA phy to wait for a SIGNATURE FIS
71 /* This is the timeout for the SATA OOB/SN because the hardware does not
80 * isci_phy - hba local phy infrastructure
83 * @phy_index: physical index relative to the controller (0-3)
85 * @sata_timer: timeout SATA signature FIS arrival
120 * to 0 if the PHY CAPABILITIES were either not
162 * struct sci_phy_properties - This structure defines the properties common to
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H A Dphy.c7 * Copyright(c) 2008 - 2011 Intel Corporation. All rights reserved.
20 * Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
26 * Copyright(c) 2008 - 2011 Intel Corporation. All rights reserved.
58 #include "phy.h"
72 /* Maximum arbitration wait time in micro-seconds */
77 return iphy->max_negotiated_speed; in sci_phy_linkrate()
82 struct isci_phy *table = iphy - iphy->phy_index; in phy_to_host()
90 return &phy_to_host(iphy)->pdev->dev; in sciphy_to_dev()
99 iphy->transport_layer_registers = reg; in sci_phy_transport_layer_initialization()
102 &iphy->transport_layer_registers->stp_rni); in sci_phy_transport_layer_initialization()
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/linux/Documentation/devicetree/bindings/scsi/
H A Dhisilicon-sas.txt3 The HiSilicon SAS controller supports SAS/SATA.
6 - compatible : value should be as follows:
7 (a) "hisilicon,hip05-sas-v1" for v1 hw in hip05 chipset
8 (b) "hisilicon,hip06-sas-v2" for v2 hw in hip06 chipset
9 (c) "hisilicon,hip07-sas-v2" for v2 hw in hip07 chipset
10 - sas-addr : array of 8 bytes for host SAS address
11 - reg : Contains two regions. The first is the address and length of the SAS
15 - hisilicon,sas-syscon: phandle of syscon used for sas control
16 - ctrl-reset-reg : offset to controller reset register in ctrl reg
17 - ctrl-reset-sts-reg : offset to controller reset status register in ctrl reg
[all …]
/linux/drivers/ata/
H A Dahci_imx.c1 // SPDX-License-Identifier: GPL-2.0-only
4 * Freescale IMX AHCI SATA platform driver
6 * based on the AHCI SATA platform driver by Jeff Garzik and Anton Vorontsov
18 #include <linux/mfd/syscon/imx6q-iomuxc-gpr.h>
21 #include <linux/hwmon-sysfs.h>
22 #include <linux/phy/phy.h>
26 #define DRV_NAME "ahci-imx"
29 /* Timer 1-ms Register */
31 /* Port0 PHY Control Register */
38 /* Port0 PHY Status Register */
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